The branch main has been updated by kbowling (ports committer):
URL:
https://cgit.FreeBSD.org/src/commit/?id=31a23e3eb5314a6b5929e980a0810803adfaad1f
commit 31a23e3eb5314a6b5929e980a0810803adfaad1f
Author: Guinan Sun <guinanx....@intel.com>
AuthorDate: 2020-07-09 08:00:28 +0000
Commit: Kevin Bowling <kbowl...@freebsd.org>
CommitDate: 2021-09-07 02:22:11 +0000
ixgbe: fix host interface shadow RAM read
Host interface Shadow RAM Read (0x31) command response
buffer length should be stored in two bytes, instead of one byte.
This patch fixes it.
Signed-off-by: Mateusz Kowalski <mateusz.kowal...@intel.com>
Signed-off-by: Guinan Sun <guinanx....@intel.com>
Reviewed-by: Wei Zhao <wei.zh...@intel.com>
Approved by: imp
Obtained from: DPDK (713fc4dd340e5eadd3bfa9a468446afaa5188624)
MFC after: 1 week
Differential Revision: https://reviews.freebsd.org/D31621
---
sys/dev/ixgbe/ixgbe_common.c | 3 ++-
sys/dev/ixgbe/ixgbe_type.h | 22 ++++++++++++++++++++++
2 files changed, 24 insertions(+), 1 deletion(-)
diff --git a/sys/dev/ixgbe/ixgbe_common.c b/sys/dev/ixgbe/ixgbe_common.c
index 6ee71dec4fda..2b9f8a0ca110 100644
--- a/sys/dev/ixgbe/ixgbe_common.c
+++ b/sys/dev/ixgbe/ixgbe_common.c
@@ -4636,7 +4636,8 @@ s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32
*buffer,
* Read Flash command requires reading buffer length from
* two byes instead of one byte
*/
- if (resp->cmd == 0x30) {
+ if (resp->cmd == IXGBE_HOST_INTERFACE_FLASH_READ_CMD ||
+ resp->cmd == IXGBE_HOST_INTERFACE_SHADOW_RAM_READ_CMD) {
for (; bi < dword_len + 2; bi++) {
buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
bi);
diff --git a/sys/dev/ixgbe/ixgbe_type.h b/sys/dev/ixgbe/ixgbe_type.h
index 1d00eadc890a..9619b771ea89 100644
--- a/sys/dev/ixgbe/ixgbe_type.h
+++ b/sys/dev/ixgbe/ixgbe_type.h
@@ -2426,6 +2426,16 @@ enum {
#define IXGBE_FW_LESM_PARAMETERS_PTR 0x2
#define IXGBE_FW_LESM_STATE_1 0x1
#define IXGBE_FW_LESM_STATE_ENABLED 0x8000 /* LESM Enable bit */
+#define IXGBE_FW_LESM_2_STATES_ENABLED_MASK 0x1F
+#define IXGBE_FW_LESM_2_STATES_ENABLED 0x12
+#define IXGBE_FW_LESM_STATE0_10G_ENABLED 0x6FFF
+#define IXGBE_FW_LESM_STATE1_10G_ENABLED 0x4FFF
+#define IXGBE_FW_LESM_STATE0_10G_DISABLED 0x0FFF
+#define IXGBE_FW_LESM_STATE1_10G_DISABLED 0x2FFF
+#define IXGBE_FW_LESM_PORT0_STATE0_OFFSET 0x2
+#define IXGBE_FW_LESM_PORT0_STATE1_OFFSET 0x3
+#define IXGBE_FW_LESM_PORT1_STATE0_OFFSET 0x6
+#define IXGBE_FW_LESM_PORT1_STATE1_OFFSET 0x7
#define IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR 0x4
#define IXGBE_FW_PATCH_VERSION_4 0x7
#define IXGBE_FCOE_IBA_CAPS_BLK_PTR 0x33 /* iSCSI/FCOE block */
@@ -4427,6 +4437,18 @@ struct ixgbe_bypass_eeprom {
#define IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD \
(0x1F << IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT)
+/* Code Command (Flash I/F Interface) */
+#define IXGBE_HOST_INTERFACE_FLASH_READ_CMD 0x30
+#define IXGBE_HOST_INTERFACE_SHADOW_RAM_READ_CMD 0x31
+#define IXGBE_HOST_INTERFACE_FLASH_WRITE_CMD 0x32
+#define IXGBE_HOST_INTERFACE_SHADOW_RAM_WRITE_CMD 0x33
+#define IXGBE_HOST_INTERFACE_FLASH_MODULE_UPDATE_CMD 0x34
+#define IXGBE_HOST_INTERFACE_FLASH_BLOCK_EREASE_CMD 0x35
+#define IXGBE_HOST_INTERFACE_SHADOW_RAM_DUMP_CMD 0x36
+#define IXGBE_HOST_INTERFACE_FLASH_INFO_CMD 0x37
+#define IXGBE_HOST_INTERFACE_APPLY_UPDATE_CMD 0x38
+#define IXGBE_HOST_INTERFACE_MASK_CMD 0x000000FF
+
#define IXGBE_REQUEST_TASK_MOD 0x01
#define IXGBE_REQUEST_TASK_MSF 0x02
#define IXGBE_REQUEST_TASK_MBX 0x04
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