The branch main has been updated by manu:

URL: 
https://cgit.FreeBSD.org/src/commit/?id=cb25a9455802de29a3609f34bef9e94af842b890

commit cb25a9455802de29a3609f34bef9e94af842b890
Author:     Oleksandr Tymoshenko <go...@freebsd.org>
AuthorDate: 2021-05-13 19:10:38 +0000
Commit:     Emmanuel Vadot <m...@freebsd.org>
CommitDate: 2021-06-11 19:06:08 +0000

    arm64: allwinner: Add i2s and codec support
    
    Differential Revision:  https://reviews.freebsd.org/D27830
---
 sys/arm/allwinner/a33_codec.c             | 417 +++++++++++++++
 sys/arm/allwinner/a64/sun50i_a64_acodec.c | 488 ++++++++++++++++++
 sys/arm/allwinner/aw_i2s.c                | 813 ++++++++++++++++++++++++++++++
 sys/arm64/conf/GENERIC                    |   7 +-
 sys/conf/files.arm64                      |   3 +
 5 files changed, 1726 insertions(+), 2 deletions(-)

diff --git a/sys/arm/allwinner/a33_codec.c b/sys/arm/allwinner/a33_codec.c
new file mode 100644
index 000000000000..2b3d5f6ef01c
--- /dev/null
+++ b/sys/arm/allwinner/a33_codec.c
@@ -0,0 +1,417 @@
+/*-
+ * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
+ *
+ * Copyright (c) 2020 Oleksandr Tymoshenko <go...@freebsd.org>
+ * Copyright (c) 2018 Jared McNeill <jmcne...@invisible.ca>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/lock.h>
+#include <sys/module.h>
+#include <sys/mutex.h>
+#include <sys/rman.h>
+#include <sys/resource.h>
+#include <machine/bus.h>
+#include <sys/gpio.h>
+
+#include <dev/ofw/ofw_bus.h>
+#include <dev/ofw/ofw_bus_subr.h>
+
+#include <dev/extres/clk/clk.h>
+#include <dev/extres/hwreset/hwreset.h>
+
+#include <dev/gpio/gpiobusvar.h>
+
+#include "opt_snd.h"
+#include <dev/sound/pcm/sound.h>
+#include <dev/sound/fdt/audio_dai.h>
+#include "audio_dai_if.h"
+
+#define        SYSCLK_CTL              0x00c
+#define         AIF1CLK_ENA                    (1 << 11)
+#define         AIF1CLK_SRC_MASK               (3 << 8)
+#define         AIF1CLK_SRC_PLL                (2 << 8)
+#define         SYSCLK_ENA                     (1 << 3)
+#define         SYSCLK_SRC                     (1 << 0)
+
+#define        MOD_CLK_ENA             0x010
+#define        MOD_RST_CTL             0x014
+#define        MOD_AIF1                        (1 << 15)
+#define        MOD_ADC                         (1 << 3)
+#define        MOD_DAC                         (1 << 2)
+
+#define        SYS_SR_CTRL             0x018
+#define         AIF1_FS_MASK           (0xf << 12)
+#define          AIF_FS_48KHZ          (8 << 12)
+
+#define        AIF1CLK_CTRL            0x040
+#define         AIF1_MSTR_MOD          (1 << 15)
+#define         AIF1_BCLK_INV          (1 << 14)
+#define         AIF1_LRCK_INV          (1 << 13)
+#define         AIF1_BCLK_DIV_MASK     (0xf << 9)
+#define          AIF1_BCLK_DIV_16      (6 << 9)
+#define         AIF1_LRCK_DIV_MASK     (7 << 6)
+#define          AIF1_LRCK_DIV_16      (0 << 6)
+#define          AIF1_LRCK_DIV_64      (2 << 6)
+#define         AIF1_WORD_SIZ_MASK     (3 << 4)
+#define          AIF1_WORD_SIZ_16      (1 << 4)
+#define         AIF1_DATA_FMT_MASK     (3 << 2)
+#define          AIF1_DATA_FMT_I2S     (0 << 2)
+#define          AIF1_DATA_FMT_LJ      (1 << 2)
+#define          AIF1_DATA_FMT_RJ      (2 << 2)
+#define          AIF1_DATA_FMT_DSP     (3 << 2)
+
+#define        AIF1_ADCDAT_CTRL        0x044
+#define                AIF1_ADC0L_ENA          (1 << 15)
+#define                AIF1_ADC0R_ENA          (1 << 14)
+
+#define        AIF1_DACDAT_CTRL        0x048
+#define         AIF1_DAC0L_ENA         (1 << 15)
+#define         AIF1_DAC0R_ENA         (1 << 14)
+
+#define        AIF1_MXR_SRC            0x04c
+#define                AIF1L_MXR_SRC_MASK      (0xf << 12)
+#define                AIF1L_MXR_SRC_AIF1      (0x8 << 12)
+#define                AIF1L_MXR_SRC_ADC       (0x2 << 12)
+#define                AIF1R_MXR_SRC_MASK      (0xf << 8)
+#define                AIF1R_MXR_SRC_AIF1      (0x8 << 8)
+#define                AIF1R_MXR_SRC_ADC       (0x2 << 8)
+
+#define        ADC_DIG_CTRL            0x100
+#define         ADC_DIG_CTRL_ENAD      (1 << 15)
+
+#define        HMIC_CTRL1              0x110
+#define         HMIC_CTRL1_N_MASK              (0xf << 8)
+#define         HMIC_CTRL1_N(n)                (((n) & 0xf) << 8)
+#define         HMIC_CTRL1_JACK_IN_IRQ_EN      (1 << 4)
+#define         HMIC_CTRL1_JACK_OUT_IRQ_EN     (1 << 3)
+#define         HMIC_CTRL1_MIC_DET_IRQ_EN      (1 << 0)
+
+#define        HMIC_CTRL2              0x114
+#define         HMIC_CTRL2_MDATA_THRES __BITS(12,8)
+
+#define        HMIC_STS                0x118
+#define         HMIC_STS_MIC_PRESENT   (1 << 6)
+#define         HMIC_STS_JACK_DET_OIRQ (1 << 4)
+#define         HMIC_STS_JACK_DET_IIRQ (1 << 3)
+#define         HMIC_STS_MIC_DET_ST    (1 << 0)
+
+#define        DAC_DIG_CTRL            0x120
+#define         DAC_DIG_CTRL_ENDA      (1 << 15)
+
+#define        DAC_MXR_SRC             0x130
+#define         DACL_MXR_SRC_MASK              (0xf << 12)
+#define          DACL_MXR_SRC_AIF1_DAC0L (0x8 << 12)
+#define         DACR_MXR_SRC_MASK              (0xf << 8)
+#define          DACR_MXR_SRC_AIF1_DAC0R (0x8 << 8)
+
+static struct ofw_compat_data compat_data[] = {
+       { "allwinner,sun8i-a33-codec",  1},
+       { NULL,                         0 }
+};
+
+static struct resource_spec sun8i_codec_spec[] = {
+       { SYS_RES_MEMORY,       0,      RF_ACTIVE },
+       { SYS_RES_IRQ,          0,      RF_ACTIVE | RF_SHAREABLE },
+       { -1, 0 }
+};
+
+struct sun8i_codec_softc {
+       device_t        dev;
+       struct resource *res[2];
+       struct mtx      mtx;
+       clk_t           clk_gate;
+       clk_t           clk_mod;
+       void *          intrhand;
+};
+
+#define        CODEC_LOCK(sc)                  mtx_lock(&(sc)->mtx)
+#define        CODEC_UNLOCK(sc)                mtx_unlock(&(sc)->mtx)
+#define        CODEC_READ(sc, reg)             bus_read_4((sc)->res[0], (reg))
+#define        CODEC_WRITE(sc, reg, val)       bus_write_4((sc)->res[0], 
(reg), (val))
+
+static int sun8i_codec_probe(device_t dev);
+static int sun8i_codec_attach(device_t dev);
+static int sun8i_codec_detach(device_t dev);
+
+static int
+sun8i_codec_probe(device_t dev)
+{
+       if (!ofw_bus_status_okay(dev))
+               return (ENXIO);
+
+       if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
+               return (ENXIO);
+
+       device_set_desc(dev, "Allwinner Codec");
+       return (BUS_PROBE_DEFAULT);
+}
+
+static int
+sun8i_codec_attach(device_t dev)
+{
+       struct sun8i_codec_softc *sc;
+       int error;
+       uint32_t val;
+       struct gpiobus_pin *pa_pin;
+       phandle_t node;
+
+       sc = device_get_softc(dev);
+       sc->dev = dev;
+       node = ofw_bus_get_node(dev);
+
+       mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF);
+
+       if (bus_alloc_resources(dev, sun8i_codec_spec, sc->res) != 0) {
+               device_printf(dev, "cannot allocate resources for device\n");
+               error = ENXIO;
+               goto fail;
+       }
+
+       error = clk_get_by_ofw_name(dev, 0, "mod", &sc->clk_mod);
+       if (error != 0) {
+               device_printf(dev, "cannot get \"mod\" clock\n");
+               goto fail;
+       }
+
+       error = clk_get_by_ofw_name(dev, 0, "bus", &sc->clk_gate);
+       if (error != 0) {
+               device_printf(dev, "cannot get \"bus\" clock\n");
+               goto fail;
+       }
+
+       error = clk_enable(sc->clk_gate);
+       if (error != 0) {
+               device_printf(dev, "cannot enable \"bus\" clock\n");
+               goto fail;
+       }
+
+       /* Enable clocks */
+       val = CODEC_READ(sc, SYSCLK_CTL);
+       val |= AIF1CLK_ENA;
+       val &= ~AIF1CLK_SRC_MASK;
+       val |= AIF1CLK_SRC_PLL;
+       val |= SYSCLK_ENA;
+       val &= ~SYSCLK_SRC;
+       CODEC_WRITE(sc, SYSCLK_CTL, val);
+       CODEC_WRITE(sc, MOD_CLK_ENA, MOD_AIF1 | MOD_ADC | MOD_DAC);
+       CODEC_WRITE(sc, MOD_RST_CTL, MOD_AIF1 | MOD_ADC | MOD_DAC);
+
+       /* Enable digital parts */
+       CODEC_WRITE(sc, DAC_DIG_CTRL, DAC_DIG_CTRL_ENDA);
+       CODEC_WRITE(sc, ADC_DIG_CTRL, ADC_DIG_CTRL_ENAD);
+
+       /* Set AIF1 to 48 kHz */
+       val = CODEC_READ(sc, SYS_SR_CTRL);
+       val &= ~AIF1_FS_MASK;
+       val |= AIF_FS_48KHZ;
+       CODEC_WRITE(sc, SYS_SR_CTRL, val);
+
+       /* Set AIF1 to 16-bit */
+       val = CODEC_READ(sc, AIF1CLK_CTRL);
+       val &= ~AIF1_WORD_SIZ_MASK;
+       val |= AIF1_WORD_SIZ_16;
+       CODEC_WRITE(sc, AIF1CLK_CTRL, val);
+
+       /* Enable AIF1 DAC timelot 0 */
+       val = CODEC_READ(sc, AIF1_DACDAT_CTRL);
+       val |= AIF1_DAC0L_ENA;
+       val |= AIF1_DAC0R_ENA;
+       CODEC_WRITE(sc, AIF1_DACDAT_CTRL, val);
+
+       /* Enable AIF1 ADC timelot 0 */
+       val = CODEC_READ(sc, AIF1_ADCDAT_CTRL);
+       val |= AIF1_ADC0L_ENA;
+       val |= AIF1_ADC0R_ENA;
+       CODEC_WRITE(sc, AIF1_ADCDAT_CTRL, val);
+
+       /* DAC mixer source select */
+       val = CODEC_READ(sc, DAC_MXR_SRC);
+       val &= ~DACL_MXR_SRC_MASK;
+       val |= DACL_MXR_SRC_AIF1_DAC0L;
+       val &= ~DACR_MXR_SRC_MASK;
+       val |= DACR_MXR_SRC_AIF1_DAC0R;
+       CODEC_WRITE(sc, DAC_MXR_SRC, val);
+
+       /* ADC mixer source select */
+       val = CODEC_READ(sc, AIF1_MXR_SRC);
+       val &= ~AIF1L_MXR_SRC_MASK;
+       val |= AIF1L_MXR_SRC_ADC;
+       val &= ~AIF1R_MXR_SRC_MASK;
+       val |= AIF1R_MXR_SRC_ADC;
+       CODEC_WRITE(sc, AIF1_MXR_SRC, val);
+
+       /* Enable PA power */
+       /* Unmute PA */
+       if (gpio_pin_get_by_ofw_property(dev, node, "allwinner,pa-gpios",
+           &pa_pin) == 0) {
+               error = gpio_pin_set_active(pa_pin, 1);
+               if (error != 0)
+                       device_printf(dev, "failed to unmute PA\n");
+       }
+
+       OF_device_register_xref(OF_xref_from_node(node), dev);
+
+       return (0);
+
+fail:
+       sun8i_codec_detach(dev);
+       return (error);
+}
+
+static int
+sun8i_codec_detach(device_t dev)
+{
+       struct sun8i_codec_softc *sc;
+
+       sc = device_get_softc(dev);
+
+       if (sc->clk_gate)
+               clk_release(sc->clk_gate);
+
+       if (sc->clk_mod)
+               clk_release(sc->clk_mod);
+
+       if (sc->intrhand != NULL)
+               bus_teardown_intr(sc->dev, sc->res[1], sc->intrhand);
+
+       bus_release_resources(dev, sun8i_codec_spec, sc->res);
+       mtx_destroy(&sc->mtx);
+
+       return (0);
+}
+
+static int
+sun8i_codec_dai_init(device_t dev, uint32_t format)
+{
+       struct sun8i_codec_softc *sc;
+       int fmt, pol, clk;
+       uint32_t val;
+
+       sc = device_get_softc(dev);
+
+       fmt = AUDIO_DAI_FORMAT_FORMAT(format);
+       pol = AUDIO_DAI_FORMAT_POLARITY(format);
+       clk = AUDIO_DAI_FORMAT_CLOCK(format);
+
+       val = CODEC_READ(sc, AIF1CLK_CTRL);
+
+       val &= ~AIF1_DATA_FMT_MASK;
+       switch (fmt) {
+       case AUDIO_DAI_FORMAT_I2S:
+               val |= AIF1_DATA_FMT_I2S;
+               break;
+       case AUDIO_DAI_FORMAT_RJ:
+               val |= AIF1_DATA_FMT_RJ;
+               break;
+       case AUDIO_DAI_FORMAT_LJ:
+               val |= AIF1_DATA_FMT_LJ;
+               break;
+       case AUDIO_DAI_FORMAT_DSPA:
+       case AUDIO_DAI_FORMAT_DSPB:
+               val |= AIF1_DATA_FMT_DSP;
+               break;
+       default:
+               return EINVAL;
+       }
+
+       val &= ~(AIF1_BCLK_INV|AIF1_LRCK_INV);
+       /* Codec LRCK polarity is inverted (datasheet is wrong) */
+       if (!AUDIO_DAI_POLARITY_INVERTED_FRAME(pol))
+               val |= AIF1_LRCK_INV;
+       if (AUDIO_DAI_POLARITY_INVERTED_BCLK(pol))
+               val |= AIF1_BCLK_INV;
+
+       switch (clk) {
+       case AUDIO_DAI_CLOCK_CBM_CFM:
+               val &= ~AIF1_MSTR_MOD;  /* codec is master */
+               break;
+       case AUDIO_DAI_CLOCK_CBS_CFS:
+               val |= AIF1_MSTR_MOD;   /* codec is slave */
+               break;
+       default:
+               return EINVAL;
+       }
+
+       val &= ~AIF1_LRCK_DIV_MASK;
+       val |= AIF1_LRCK_DIV_64;
+
+       val &= ~AIF1_BCLK_DIV_MASK;
+       val |= AIF1_BCLK_DIV_16;
+
+       CODEC_WRITE(sc, AIF1CLK_CTRL, val);
+
+       return (0);
+}
+
+static int
+sun8i_codec_dai_trigger(device_t dev, int go, int pcm_dir)
+{
+
+       return (0);
+}
+
+static int
+sun8i_codec_dai_setup_mixer(device_t dev, device_t pcmdev)
+{
+       struct sun8i_codec_softc *sc;
+
+       sc = device_get_softc(dev);
+       /* Do nothing for now */
+
+       return (0);
+}
+
+
+static device_method_t sun8i_codec_methods[] = {
+       /* Device interface */
+       DEVMETHOD(device_probe,         sun8i_codec_probe),
+       DEVMETHOD(device_attach,        sun8i_codec_attach),
+       DEVMETHOD(device_detach,        sun8i_codec_detach),
+
+       DEVMETHOD(audio_dai_init,       sun8i_codec_dai_init),
+       DEVMETHOD(audio_dai_setup_mixer,        sun8i_codec_dai_setup_mixer),
+       DEVMETHOD(audio_dai_trigger,    sun8i_codec_dai_trigger),
+
+       DEVMETHOD_END
+};
+
+static driver_t sun8i_codec_driver = {
+       "sun8icodec",
+       sun8i_codec_methods,
+       sizeof(struct sun8i_codec_softc),
+};
+
+static devclass_t sun8i_codec_devclass;
+
+DRIVER_MODULE(sun8i_codec, simplebus, sun8i_codec_driver, 
sun8i_codec_devclass, 0, 0);
+SIMPLEBUS_PNP_INFO(compat_data);
diff --git a/sys/arm/allwinner/a64/sun50i_a64_acodec.c 
b/sys/arm/allwinner/a64/sun50i_a64_acodec.c
new file mode 100644
index 000000000000..10febf98abd8
--- /dev/null
+++ b/sys/arm/allwinner/a64/sun50i_a64_acodec.c
@@ -0,0 +1,488 @@
+/*-
+ * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
+ *
+ * Copyright (c) 2020 Oleksandr Tymoshenko <go...@freebsd.org>
+ * Copyright (c) 2018 Jared McNeill <jmcne...@invisible.ca>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/lock.h>
+#include <sys/module.h>
+#include <sys/mutex.h>
+#include <sys/rman.h>
+#include <sys/resource.h>
+#include <machine/bus.h>
+
+#include <dev/ofw/ofw_bus.h>
+#include <dev/ofw/ofw_bus_subr.h>
+
+#include <dev/extres/clk/clk.h>
+#include <dev/extres/hwreset/hwreset.h>
+#include <dev/extres/regulator/regulator.h>
+
+#include "syscon_if.h"
+
+#include "opt_snd.h"
+#include <dev/sound/pcm/sound.h>
+#include <dev/sound/fdt/audio_dai.h>
+#include "audio_dai_if.h"
+#include "mixer_if.h"
+
+#define        A64_PR_CFG              0x00
+#define         A64_AC_PR_RST          (1 << 28)
+#define         A64_AC_PR_RW           (1 << 24)
+#define         A64_AC_PR_ADDR_MASK    (0x1f << 16)
+#define         A64_AC_PR_ADDR(n)      (((n) & 0x1f) << 16)
+#define         A64_ACDA_PR_WDAT_MASK  (0xff << 8)
+#define         A64_ACDA_PR_WDAT(n)    (((n) & 0xff) << 8)
+#define         A64_ACDA_PR_RDAT(n)    ((n) & 0xff)
+
+#define        A64_HP_CTRL             0x00
+#define         A64_HPPA_EN            (1 << 6)
+#define         A64_HPVOL_MASK         0x3f
+#define         A64_HPVOL(n)           ((n) & 0x3f)
+#define        A64_OL_MIX_CTRL         0x01
+#define         A64_LMIXMUTE_LDAC      (1 << 1)
+#define        A64_OR_MIX_CTRL         0x02
+#define         A64_RMIXMUTE_RDAC      (1 << 1)
+#define        A64_LINEOUT_CTRL0       0x05
+#define         A64_LINEOUT_LEFT_EN    (1 << 7)
+#define         A64_LINEOUT_RIGHT_EN   (1 << 6)
+#define         A64_LINEOUT_EN         
(A64_LINEOUT_LEFT_EN|A64_LINEOUT_RIGHT_EN)
+#define        A64_LINEOUT_CTRL1       0x06
+#define         A64_LINEOUT_VOL        __BITS(4,0)
+#define        A64_MIC1_CTRL           0x07
+#define         A64_MIC1G              __BITS(6,4)
+#define         A64_MIC1AMPEN          (1 << 3)
+#define         A64_MIC1BOOST          __BITS(2,0)
+#define        A64_MIC2_CTRL           0x08
+#define         A64_MIC2_SEL           (1 << 7)
+#define         A64_MIC2G_MASK         (7 << 4)
+#define         A64_MIC2G(n)           (((n) & 7) << 4)
+#define         A64_MIC2AMPEN          (1 << 3)
+#define         A64_MIC2BOOST_MASK     (7 << 0)
+#define         A64_MIC2BOOST(n)       (((n) & 7) << 0)
+#define        A64_LINEIN_CTRL         0x09
+#define         A64_LINEING            __BITS(6,4)
+#define        A64_MIX_DAC_CTRL        0x0a
+#define         A64_DACAREN            (1 << 7)
+#define         A64_DACALEN            (1 << 6)
+#define         A64_RMIXEN             (1 << 5)
+#define         A64_LMIXEN             (1 << 4)
+#define         A64_RHPPAMUTE          (1 << 3)
+#define         A64_LHPPAMUTE          (1 << 2)
+#define         A64_RHPIS              (1 << 1)
+#define         A64_LHPIS              (1 << 0)
+#define        A64_L_ADCMIX_SRC        0x0b
+#define        A64_R_ADCMIX_SRC        0x0c
+#define         A64_ADCMIX_SRC_MIC1    (1 << 6)
+#define         A64_ADCMIX_SRC_MIC2    (1 << 5)
+#define         A64_ADCMIX_SRC_LINEIN  (1 << 2)
+#define         A64_ADCMIX_SRC_OMIXER  (1 << 1)
+#define        A64_ADC_CTRL            0x0d
+#define         A64_ADCREN             (1 << 7)
+#define         A64_ADCLEN             (1 << 6)
+#define         A64_ADCG               __BITS(2,0)
+#define        A64_JACK_MIC_CTRL       0x1d
+#define         A64_JACKDETEN          (1 << 7)
+#define         A64_INNERRESEN         (1 << 6)
+#define         A64_HMICBIASEN         (1 << 5)
+#define         A64_AUTOPLEN           (1 << 1)
+
+#define        A64CODEC_MIXER_DEVS     ((1 << SOUND_MIXER_VOLUME) | \
+       (1 << SOUND_MIXER_MIC))
+
+static struct ofw_compat_data compat_data[] = {
+       { "allwinner,sun50i-a64-codec-analog",  1},
+       { NULL,                                 0 }
+};
+
+struct a64codec_softc {
+       device_t        dev;
+       struct resource *res;
+       struct mtx      mtx;
+       u_int   regaddr;        /* address for the sysctl */
+};
+
+#define        A64CODEC_LOCK(sc)               mtx_lock(&(sc)->mtx)
+#define        A64CODEC_UNLOCK(sc)             mtx_unlock(&(sc)->mtx)
+#define        A64CODEC_READ(sc, reg)          bus_read_4((sc)->res, (reg))
+#define        A64CODEC_WRITE(sc, reg, val)    bus_write_4((sc)->res, (reg), 
(val))
+
+static int a64codec_probe(device_t dev);
+static int a64codec_attach(device_t dev);
+static int a64codec_detach(device_t dev);
+
+static u_int
+a64_acodec_pr_read(struct a64codec_softc *sc, u_int addr)
+{
+       uint32_t val;
+
+       /* Read current value */
+       val = A64CODEC_READ(sc, A64_PR_CFG);
+
+       /* De-assert reset */
+       val |= A64_AC_PR_RST;
+       A64CODEC_WRITE(sc, A64_PR_CFG, val);
+
+       /* Read mode */
+       val &= ~A64_AC_PR_RW;
+       A64CODEC_WRITE(sc, A64_PR_CFG, val);
+
+       /* Set address */
+       val &= ~A64_AC_PR_ADDR_MASK;
+       val |= A64_AC_PR_ADDR(addr);
+       A64CODEC_WRITE(sc, A64_PR_CFG, val);
+
+       /* Read data */
+       val = A64CODEC_READ(sc, A64_PR_CFG);
+       return A64_ACDA_PR_RDAT(val);
+}
+
+static void
+a64_acodec_pr_write(struct a64codec_softc *sc, u_int addr, u_int data)
+{
+       uint32_t val;
+
+       /* Read current value */
+       val = A64CODEC_READ(sc, A64_PR_CFG);
+
+       /* De-assert reset */
+       val |= A64_AC_PR_RST;
+       A64CODEC_WRITE(sc, A64_PR_CFG, val);
+
+       /* Set address */
+       val &= ~A64_AC_PR_ADDR_MASK;
+       val |= A64_AC_PR_ADDR(addr);
+       A64CODEC_WRITE(sc, A64_PR_CFG, val);
+
+       /* Write data */
+       val &= ~A64_ACDA_PR_WDAT_MASK;
+       val |= A64_ACDA_PR_WDAT(data);
+       A64CODEC_WRITE(sc, A64_PR_CFG, val);
+
+       /* Write mode */
+       val |= A64_AC_PR_RW;
+       A64CODEC_WRITE(sc, A64_PR_CFG, val);
+
+       /* Clear write mode */
+       val &= ~A64_AC_PR_RW;
+       A64CODEC_WRITE(sc, A64_PR_CFG, val);
+}
+
+static void
+a64_acodec_pr_set_clear(struct a64codec_softc *sc, u_int addr, u_int set, 
u_int clr)
+{
+       u_int old, new;
+
+       old = a64_acodec_pr_read(sc, addr);
+       new = set | (old & ~clr);
+       a64_acodec_pr_write(sc, addr, new);
+}
+
+static int
+a64codec_probe(device_t dev)
+{
+       if (!ofw_bus_status_okay(dev))
+               return (ENXIO);
+
+       if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
+               return (ENXIO);
+
+       device_set_desc(dev, "Allwinner A64 Analog Codec");
+       return (BUS_PROBE_DEFAULT);
+}
+
+static int
+a64codec_attach(device_t dev)
+{
+       struct a64codec_softc *sc;
+       int error, rid;
+       phandle_t node;
+       regulator_t reg;
+
+       sc = device_get_softc(dev);
+       sc->dev = dev;
+
+       mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF);
+
+       rid = 0;
+       sc->res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
+       if (!sc->res) {
+               device_printf(dev, "cannot allocate resource for device\n");
+               error = ENXIO;
+               goto fail;
+       }
+
+       if (regulator_get_by_ofw_property(dev, 0, "cpvdd-supply", &reg) == 0) {
+               error = regulator_enable(reg);
+               if (error != 0) {
+                       device_printf(dev, "cannot enable PHY regulator\n");
+                       goto fail;
+               }
+       }
+
+       /* Right & Left Headphone PA enable */
+       a64_acodec_pr_set_clear(sc, A64_HP_CTRL,
+           A64_HPPA_EN, 0);
+
+       /* Microphone BIAS enable */
+       a64_acodec_pr_set_clear(sc, A64_JACK_MIC_CTRL,
+           A64_HMICBIASEN | A64_INNERRESEN, 0);
+
+       /* Unmute DAC to output mixer */
+       a64_acodec_pr_set_clear(sc, A64_OL_MIX_CTRL,
+           A64_LMIXMUTE_LDAC, 0);
+       a64_acodec_pr_set_clear(sc, A64_OR_MIX_CTRL,
+           A64_RMIXMUTE_RDAC, 0);
+
+       /* For now we work only with headphones */
+       a64_acodec_pr_set_clear(sc, A64_LINEOUT_CTRL0,
+           0, A64_LINEOUT_EN);
+       a64_acodec_pr_set_clear(sc, A64_HP_CTRL,
+           A64_HPPA_EN, 0);
+
+       u_int val = a64_acodec_pr_read(sc, A64_HP_CTRL);
+       val &= ~(0x3f);
+       val |= 0x25;
+       a64_acodec_pr_write(sc, A64_HP_CTRL, val);
+
+       a64_acodec_pr_set_clear(sc, A64_MIC2_CTRL,
+           A64_MIC2AMPEN | A64_MIC2_SEL | A64_MIC2G(0x3) | A64_MIC2BOOST(0x4),
+           A64_MIC2G_MASK | A64_MIC2BOOST_MASK);
+
+       a64_acodec_pr_write(sc, A64_L_ADCMIX_SRC,
+           A64_ADCMIX_SRC_MIC2);
+       a64_acodec_pr_write(sc, A64_R_ADCMIX_SRC,
+           A64_ADCMIX_SRC_MIC2);
+
+       /* Max out MIC2 gain */
+       val = a64_acodec_pr_read(sc, A64_MIC2_CTRL);
+       val &= ~(0x7);
+       val |= (0x7);
+       val &= ~(7 << 4);
+       val |= (7 << 4);
+       a64_acodec_pr_write(sc, A64_MIC2_CTRL, val);
+
+       node = ofw_bus_get_node(dev);
+       OF_device_register_xref(OF_xref_from_node(node), dev);
+
+       return (0);
+
+fail:
+       a64codec_detach(dev);
+       return (error);
+}
+
+static int
+a64codec_detach(device_t dev)
+{
+       struct a64codec_softc *sc;
+
+       sc = device_get_softc(dev);
+
+       if (sc->res)
+               bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->res);
+       mtx_destroy(&sc->mtx);
+
+       return (0);
+}
+
+static int
+a64codec_mixer_init(struct snd_mixer *m)
+{
+
+       mix_setdevs(m, A64CODEC_MIXER_DEVS);
+
+       return (0);
+}
+
+static int
+a64codec_mixer_uninit(struct snd_mixer *m)
+{
+
+       return (0);
+}
+
+static int
+a64codec_mixer_reinit(struct snd_mixer *m)
+{
+
+       return (0);
+}
+
+static int
+a64codec_mixer_set(struct snd_mixer *m, unsigned dev, unsigned left, unsigned 
right)
+{
+       struct a64codec_softc *sc;
+       struct mtx *mixer_lock;
+       uint8_t do_unlock;
+       u_int val;
+
+       sc = device_get_softc(mix_getdevinfo(m));
+       mixer_lock = mixer_get_lock(m);
+
+       if (mtx_owned(mixer_lock)) {
+               do_unlock = 0;
+       } else {
+               do_unlock = 1;
+               mtx_lock(mixer_lock);
+       }
+
+       right = left;
+
+       A64CODEC_LOCK(sc);
+       switch(dev) {
+       case SOUND_MIXER_VOLUME:
+               val = a64_acodec_pr_read(sc, A64_HP_CTRL);
+               val &= ~(A64_HPVOL_MASK);
+               val |= A64_HPVOL(left * 63 / 100);
+               a64_acodec_pr_write(sc, A64_HP_CTRL, val);
+               break;
+
+       case SOUND_MIXER_MIC:
+               val = a64_acodec_pr_read(sc, A64_MIC2_CTRL);
+               val &= ~(A64_MIC2BOOST_MASK);
+               val |= A64_MIC2BOOST(left * 7 / 100);
+               a64_acodec_pr_write(sc, A64_MIC2_CTRL, val);
+               break;
+       default:
+               break;
+       }
+       A64CODEC_UNLOCK(sc);
+
+       if (do_unlock) {
+               mtx_unlock(mixer_lock);
+       }
+
+       return (left | (right << 8));
+}
+
+static unsigned
+a64codec_mixer_setrecsrc(struct snd_mixer *m, unsigned src)
+{
+
+       return (0);
+}
+
+static kobj_method_t a64codec_mixer_methods[] = {
+       KOBJMETHOD(mixer_init,          a64codec_mixer_init),
+       KOBJMETHOD(mixer_uninit,        a64codec_mixer_uninit),
+       KOBJMETHOD(mixer_reinit,        a64codec_mixer_reinit),
+       KOBJMETHOD(mixer_set,           a64codec_mixer_set),
+       KOBJMETHOD(mixer_setrecsrc,     a64codec_mixer_setrecsrc),
+       KOBJMETHOD_END
+};
+
+MIXER_DECLARE(a64codec_mixer);
+
+static int
+a64codec_dai_init(device_t dev, uint32_t format)
+{
+
+       return (0);
+}
+
+static int
+a64codec_dai_trigger(device_t dev, int go, int pcm_dir)
+{
+       struct a64codec_softc   *sc = device_get_softc(dev);
+
+       if ((pcm_dir != PCMDIR_PLAY) && (pcm_dir != PCMDIR_REC))
+               return (EINVAL);
+
+       switch (go) {
+       case PCMTRIG_START:
+               if (pcm_dir == PCMDIR_PLAY) {
+                       /* Enable DAC analog l/r channels, HP PA, and output 
mixer */
+                       a64_acodec_pr_set_clear(sc, A64_MIX_DAC_CTRL,
+                           A64_DACAREN | A64_DACALEN | A64_RMIXEN | A64_LMIXEN 
|
+                           A64_RHPPAMUTE | A64_LHPPAMUTE, 0);
+               }
+               else if (pcm_dir == PCMDIR_REC) {
+                       /* Enable ADC analog l/r channels */
+                       a64_acodec_pr_set_clear(sc, A64_ADC_CTRL,
+                           A64_ADCREN | A64_ADCLEN, 0);
+               }
+               break;
+
+       case PCMTRIG_STOP:
+       case PCMTRIG_ABORT:
+               if (pcm_dir == PCMDIR_PLAY) {
+                       /* Disable DAC analog l/r channels, HP PA, and output 
mixer */
+                       a64_acodec_pr_set_clear(sc, A64_MIX_DAC_CTRL,
+                           0, A64_DACAREN | A64_DACALEN | A64_RMIXEN | 
A64_LMIXEN |
+                           A64_RHPPAMUTE | A64_LHPPAMUTE);
+               }
+               else if (pcm_dir == PCMDIR_REC) {
+                       /* Disable ADC analog l/r channels */
+                       a64_acodec_pr_set_clear(sc, A64_ADC_CTRL,
+                           0, A64_ADCREN | A64_ADCLEN);
+               }
+               break;
+       }
+
+       return (0);
+}
+
+static int
+a64codec_dai_setup_mixer(device_t dev, device_t pcmdev)
+{
+
+       mixer_init(pcmdev, &a64codec_mixer_class, dev);
+
+       return (0);
+}
+
+static device_method_t a64codec_methods[] = {
+       /* Device interface */
+       DEVMETHOD(device_probe,         a64codec_probe),
+       DEVMETHOD(device_attach,        a64codec_attach),
+       DEVMETHOD(device_detach,        a64codec_detach),
+
+       DEVMETHOD(audio_dai_init,       a64codec_dai_init),
+       DEVMETHOD(audio_dai_setup_mixer,        a64codec_dai_setup_mixer),
+       DEVMETHOD(audio_dai_trigger,    a64codec_dai_trigger),
+
+       DEVMETHOD_END
+};
+
+static driver_t a64codec_driver = {
+       "a64codec",
+       a64codec_methods,
+       sizeof(struct a64codec_softc),
+};
+
+static devclass_t a64codec_devclass;
+
+DRIVER_MODULE(a64codec, simplebus, a64codec_driver, a64codec_devclass, 0, 0);
+SIMPLEBUS_PNP_INFO(compat_data);
diff --git a/sys/arm/allwinner/aw_i2s.c b/sys/arm/allwinner/aw_i2s.c
new file mode 100644
index 000000000000..013e88a548a8
--- /dev/null
+++ b/sys/arm/allwinner/aw_i2s.c
@@ -0,0 +1,813 @@
+/*-
+ * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
+ *
+ * Copyright (c) 2020 Oleksandr Tymoshenko <go...@freebsd.org>
+ * Copyright (c) 2018 Jared McNeill <jmcne...@invisible.ca>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/lock.h>
+#include <sys/module.h>
+#include <sys/mutex.h>
+#include <sys/rman.h>
+#include <sys/resource.h>
+#include <machine/bus.h>
*** 805 LINES SKIPPED ***
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