---
sys/dev/mrsas/mrsas.c | 198 ++++++++++++++++---------------
sys/dev/mrsas/mrsas.h | 289 +++++++++++++++++++++++++++++++++++++++++++++-
sys/dev/mrsas/mrsas_cam.c | 54 ++++-----
sys/dev/mrsas/mrsas_fp.c | 170 ++++++++++++++-------------
4 files changed, 510 insertions(+), 201 deletions(-)
diff --git a/sys/dev/mrsas/mrsas.c b/sys/dev/mrsas/mrsas.c
index 32d85c803938..f4c34e237fc4 100644
--- a/sys/dev/mrsas/mrsas.c
+++ b/sys/dev/mrsas/mrsas.c
@@ -52,6 +52,7 @@ __FBSDID("$FreeBSD$");
#include <sys/kthread.h>
#include <sys/taskqueue.h>
#include <sys/smp.h>
+#include <sys/endian.h>
/*
* Function prototypes
@@ -619,13 +620,13 @@ mrsas_get_seq_num(struct mrsas_softc *sc,
dcmd->cmd = MFI_CMD_DCMD;
dcmd->cmd_status = 0x0;
dcmd->sge_count = 1;
- dcmd->flags = MFI_FRAME_DIR_READ;
+ dcmd->flags = htole16(MFI_FRAME_DIR_READ);
dcmd->timeout = 0;
dcmd->pad_0 = 0;
- dcmd->data_xfer_len = sizeof(struct mrsas_evt_log_info);
- dcmd->opcode = MR_DCMD_CTRL_EVENT_GET_INFO;
- dcmd->sgl.sge32[0].phys_addr = sc->el_info_phys_addr;
- dcmd->sgl.sge32[0].length = sizeof(struct mrsas_evt_log_info);
+ dcmd->data_xfer_len = htole32(sizeof(struct mrsas_evt_log_info));
+ dcmd->opcode = htole32(MR_DCMD_CTRL_EVENT_GET_INFO);
+ dcmd->sgl.sge32[0].phys_addr = htole32(sc->el_info_phys_addr &
0xFFFFFFFF);
+ dcmd->sgl.sge32[0].length = htole32(sizeof(struct mrsas_evt_log_info));
retcode = mrsas_issue_blocked_cmd(sc, cmd);
if (retcode == ETIMEDOUT)
@@ -681,7 +682,7 @@ mrsas_register_aen(struct mrsas_softc *sc, u_int32_t
seq_num,
curr_aen.word = class_locale_word;
if (sc->aen_cmd) {
- prev_aen.word = sc->aen_cmd->frame->dcmd.mbox.w[1];
+ prev_aen.word = le32toh(sc->aen_cmd->frame->dcmd.mbox.w[1]);
/*
* A class whose enum value is smaller is inclusive of all
@@ -732,16 +733,16 @@ mrsas_register_aen(struct mrsas_softc *sc, u_int32_t
seq_num,
dcmd->cmd = MFI_CMD_DCMD;
dcmd->cmd_status = 0x0;
dcmd->sge_count = 1;
- dcmd->flags = MFI_FRAME_DIR_READ;
+ dcmd->flags = htole16(MFI_FRAME_DIR_READ);
dcmd->timeout = 0;
dcmd->pad_0 = 0;
- dcmd->data_xfer_len = sizeof(struct mrsas_evt_detail);
- dcmd->opcode = MR_DCMD_CTRL_EVENT_WAIT;
- dcmd->mbox.w[0] = seq_num;
+ dcmd->data_xfer_len = htole32(sizeof(struct mrsas_evt_detail));
+ dcmd->opcode = htole32(MR_DCMD_CTRL_EVENT_WAIT);
+ dcmd->mbox.w[0] = htole32(seq_num);
sc->last_seq_num = seq_num;
- dcmd->mbox.w[1] = curr_aen.word;
- dcmd->sgl.sge32[0].phys_addr = (u_int32_t)sc->evt_detail_phys_addr;
- dcmd->sgl.sge32[0].length = sizeof(struct mrsas_evt_detail);
+ dcmd->mbox.w[1] = htole32(curr_aen.word);
+ dcmd->sgl.sge32[0].phys_addr = htole32((u_int32_t)sc->evt_detail_phys_addr
& 0xFFFFFFFF);
+ dcmd->sgl.sge32[0].length = htole32(sizeof(struct mrsas_evt_detail));
if (sc->aen_cmd != NULL) {
mrsas_release_mfi_cmd(cmd);
@@ -907,9 +908,6 @@ mrsas_attach(device_t dev)
* Set up PCI and registers
*/
cmd = pci_read_config(dev, PCIR_COMMAND, 2);
- if ((cmd & PCIM_CMD_PORTEN) == 0) {
- return (ENXIO);
- }
/* Force the busmaster enable bit on. */
cmd |= PCIM_CMD_BUSMASTEREN;
pci_write_config(dev, PCIR_COMMAND, cmd, 2);
@@ -1704,7 +1702,7 @@ mrsas_complete_cmd(struct mrsas_softc *sc, u_int32_t
MSIxIndex)
/* Find our reply descriptor for the command and process */
while ((desc_val.u.low != 0xFFFFFFFF) && (desc_val.u.high !=
0xFFFFFFFF)) {
- smid = reply_desc->SMID;
+ smid = le16toh(reply_desc->SMID);
cmd_mpt = sc->mpt_cmd_list[smid - 1];
scsi_io_req = (MRSAS_RAID_SCSI_IO_REQUEST *)
cmd_mpt->io_request;
@@ -1736,7 +1734,7 @@ mrsas_complete_cmd(struct mrsas_softc *sc, u_int32_t MSIxIndex)
case MRSAS_MPI2_FUNCTION_LD_IO_REQUEST:
if (cmd_mpt->r1_alt_dev_handle == MR_DEVHANDLE_INVALID)
{
mrsas_map_mpt_cmd_status(cmd_mpt,
cmd_mpt->ccb_ptr, status,
- extStatus, data_length, sense);
+ extStatus, le32toh(data_length), sense);
mrsas_cmd_done(sc, cmd_mpt);
mrsas_atomic_dec(&sc->fw_outstanding);
} else {
@@ -1764,7 +1762,7 @@ mrsas_complete_cmd(struct mrsas_softc *sc, u_int32_t
MSIxIndex)
mrsas_release_mpt_cmd(r1_cmd);
mrsas_atomic_dec(&sc->fw_outstanding);
mrsas_map_mpt_cmd_status(cmd_mpt,
cmd_mpt->ccb_ptr, status,
- extStatus, data_length, sense);
+ extStatus, le32toh(data_length),
sense);
mrsas_cmd_done(sc, cmd_mpt);
mrsas_atomic_dec(&sc->fw_outstanding);
}
@@ -1778,7 +1776,7 @@ mrsas_complete_cmd(struct mrsas_softc *sc, u_int32_t
MSIxIndex)
* And also make sure that the issue_polled call should
only be
* used if INTERRUPT IS DISABLED.
*/
- if (cmd_mfi->frame->hdr.flags &
MFI_FRAME_DONT_POST_IN_REPLY_QUEUE)
+ if (cmd_mfi->frame->hdr.flags &
htole16(MFI_FRAME_DONT_POST_IN_REPLY_QUEUE))
mrsas_release_mfi_cmd(cmd_mfi);
else
mrsas_complete_mptmfi_passthru(sc, cmd_mfi,
status);
@@ -2593,6 +2591,13 @@ mrsas_init_adapter(struct mrsas_softc *sc)
(MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE * (sc->max_fw_cmds + 1));
scratch_pad_2 = mrsas_read_reg_with_retries(sc, offsetof(mrsas_reg_set,
outbound_scratch_pad_2));
+
+ mrsas_dprint(sc, MRSAS_TRACE, "%s: sc->reply_q_depth 0x%x,"
+ "sc->request_alloc_sz 0x%x, sc->reply_alloc_sz 0x%x,"
+ "sc->io_frames_alloc_sz 0x%x\n", __func__,
+ sc->reply_q_depth, sc->request_alloc_sz,
+ sc->reply_alloc_sz, sc->io_frames_alloc_sz);
+
/*
* If scratch_pad_2 & MEGASAS_MAX_CHAIN_SIZE_UNITS_MASK is set,
* Firmware support extended IO chain frame which is 4 time more
@@ -2617,8 +2622,10 @@ mrsas_init_adapter(struct mrsas_softc *sc)
mrsas_dprint(sc, MRSAS_INFO,
"max sge: 0x%x, max chain frame size: 0x%x, "
- "max fw cmd: 0x%x\n", sc->max_num_sge,
- sc->max_chain_frame_sz, sc->max_fw_cmds);
+ "max fw cmd: 0x%x sc->chain_frames_alloc_sz: 0x%x\n",
+ sc->max_num_sge,
+ sc->max_chain_frame_sz, sc->max_fw_cmds,
+ sc->chain_frames_alloc_sz);
/* Used for pass thru MFI frame (DCMD) */
sc->chain_offset_mfi_pthru = offsetof(MRSAS_RAID_SCSI_IO_REQUEST, SGL)
/ 16;
@@ -2738,19 +2745,19 @@ mrsas_ioc_init(struct mrsas_softc *sc)
IOCInitMsg = (pMpi2IOCInitRequest_t)(((char *)sc->ioc_init_mem) + 1024);
IOCInitMsg->Function = MPI2_FUNCTION_IOC_INIT;
IOCInitMsg->WhoInit = MPI2_WHOINIT_HOST_DRIVER;
- IOCInitMsg->MsgVersion = MPI2_VERSION;
- IOCInitMsg->HeaderVersion = MPI2_HEADER_VERSION;
- IOCInitMsg->SystemRequestFrameSize =
MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE / 4;
- IOCInitMsg->ReplyDescriptorPostQueueDepth = sc->reply_q_depth;
- IOCInitMsg->ReplyDescriptorPostQueueAddress = sc->reply_desc_phys_addr;
- IOCInitMsg->SystemRequestFrameBaseAddress = sc->io_request_phys_addr;
+ IOCInitMsg->MsgVersion = htole16(MPI2_VERSION);
+ IOCInitMsg->HeaderVersion = htole16(MPI2_HEADER_VERSION);
+ IOCInitMsg->SystemRequestFrameSize =
htole16(MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE / 4);
+ IOCInitMsg->ReplyDescriptorPostQueueDepth = htole16(sc->reply_q_depth);
+ IOCInitMsg->ReplyDescriptorPostQueueAddress =
htole64(sc->reply_desc_phys_addr);
+ IOCInitMsg->SystemRequestFrameBaseAddress =
htole64(sc->io_request_phys_addr);
IOCInitMsg->HostMSIxVectors = (sc->msix_vectors > 0 ? sc->msix_vectors
: 0);
IOCInitMsg->HostPageSize = MR_DEFAULT_NVME_PAGE_SHIFT;
init_frame = (struct mrsas_init_frame *)sc->ioc_init_mem;
init_frame->cmd = MFI_CMD_INIT;
init_frame->cmd_status = 0xFF;
- init_frame->flags |= MFI_FRAME_DONT_POST_IN_REPLY_QUEUE;
+ init_frame->flags |= htole16(MFI_FRAME_DONT_POST_IN_REPLY_QUEUE);
/* driver support Extended MSIX */
if (sc->mrsas_gen3_ctrl || sc->is_ventura || sc->is_aero) {
@@ -2768,11 +2775,16 @@ mrsas_ioc_init(struct mrsas_softc *sc)
init_frame->driver_operations.mfi_capabilities.security_protocol_cmds_fw = 1;
if (sc->max_chain_frame_sz > MEGASAS_CHAIN_FRAME_SZ_MIN)
init_frame->driver_operations.mfi_capabilities.support_ext_io_size = 1;
+
+ init_frame->driver_operations.reg =
htole32(init_frame->driver_operations.reg);
+
phys_addr = (bus_addr_t)sc->ioc_init_phys_mem + 1024;
- init_frame->queue_info_new_phys_addr_lo = phys_addr;
- init_frame->data_xfer_len = sizeof(Mpi2IOCInitRequest_t);
+ init_frame->queue_info_new_phys_addr_lo = htole32(phys_addr);
+ init_frame->data_xfer_len = htole32(sizeof(Mpi2IOCInitRequest_t));
+
+ req_desc.addr.u.low = htole32((bus_addr_t)sc->ioc_init_phys_mem &
0xFFFFFFFF);
+ req_desc.addr.u.high = htole32((bus_addr_t)sc->ioc_init_phys_mem >> 32);
- req_desc.addr.Words = (bus_addr_t)sc->ioc_init_phys_mem;
req_desc.MFAIo.RequestFlags =
(MRSAS_REQ_DESCRIPT_FLAGS_MFA <<
MRSAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT);
@@ -2923,9 +2935,9 @@ mrsas_write_64bit_req_desc(struct mrsas_softc *sc, u_int32_t req_desc_lo,
{
mtx_lock(&sc->pci_lock);
mrsas_write_reg(sc, offsetof(mrsas_reg_set, inbound_low_queue_port),
- req_desc_lo);
+ le32toh(req_desc_lo));
mrsas_write_reg(sc, offsetof(mrsas_reg_set, inbound_high_queue_port),
- req_desc_hi);
+ le32toh(req_desc_hi));
mtx_unlock(&sc->pci_lock);
}
@@ -2944,7 +2956,7 @@ mrsas_fire_cmd(struct mrsas_softc *sc, u_int32_t req_desc_lo,
{
if (sc->atomic_desc_support)
mrsas_write_reg(sc, offsetof(mrsas_reg_set,
inbound_single_queue_port),
- req_desc_lo);
+ le32toh(req_desc_lo));
else
mrsas_write_64bit_req_desc(sc, req_desc_lo, req_desc_hi);
}
@@ -3103,7 +3115,6 @@ mrsas_ocr_thread(void *arg)
sc = (struct mrsas_softc *)arg;
mrsas_dprint(sc, MRSAS_TRACE, "%s\n", __func__);
-
sc->ocr_thread_active = 1;
mtx_lock(&sc->sim_lock);
for (;;) {
@@ -3642,10 +3653,10 @@ mrsas_get_ctrl_info(struct mrsas_softc *sc)
dcmd->flags = MFI_FRAME_DIR_READ;
dcmd->timeout = 0;
dcmd->pad_0 = 0;
- dcmd->data_xfer_len = sizeof(struct mrsas_ctrl_info);
- dcmd->opcode = MR_DCMD_CTRL_GET_INFO;
- dcmd->sgl.sge32[0].phys_addr = sc->ctlr_info_phys_addr;
- dcmd->sgl.sge32[0].length = sizeof(struct mrsas_ctrl_info);
+ dcmd->data_xfer_len = htole32(sizeof(struct mrsas_ctrl_info));
+ dcmd->opcode = htole32(MR_DCMD_CTRL_GET_INFO);
+ dcmd->sgl.sge32[0].phys_addr = htole32(sc->ctlr_info_phys_addr &
0xFFFFFFFF);
+ dcmd->sgl.sge32[0].length = htole32(sizeof(struct mrsas_ctrl_info));
if (!sc->mask_interrupts)
retcode = mrsas_issue_blocked_cmd(sc, cmd);
@@ -3654,8 +3665,13 @@ mrsas_get_ctrl_info(struct mrsas_softc *sc)
if (retcode == ETIMEDOUT)
goto dcmd_timeout;
- else
+ else {
memcpy(sc->ctrl_info, sc->ctlr_info_mem, sizeof(struct
mrsas_ctrl_info));
+ le32_to_cpus(&sc->ctrl_info->properties.OnOffProperties);
+ le32_to_cpus(&sc->ctrl_info->adapterOperations2);
+ le32_to_cpus(&sc->ctrl_info->adapterOperations3);
+ le16_to_cpus(&sc->ctrl_info->adapterOperations4);
+ }
do_ocr = 0;
mrsas_update_ext_vd_details(sc);
@@ -3813,7 +3829,7 @@ mrsas_issue_polled(struct mrsas_softc *sc, struct
mrsas_mfi_cmd *cmd)
int i, retcode = SUCCESS;
frame_hdr->cmd_status = 0xFF;
- frame_hdr->flags |= MFI_FRAME_DONT_POST_IN_REPLY_QUEUE;
+ frame_hdr->flags |= htole16(MFI_FRAME_DONT_POST_IN_REPLY_QUEUE);
/* Issue the frame using inbound queue port */
if (mrsas_issue_dcmd(sc, cmd)) {
@@ -3892,7 +3908,7 @@ mrsas_build_mpt_cmd(struct mrsas_softc *sc, struct
mrsas_mfi_cmd *cmd)
req_desc->addr.Words = 0;
req_desc->SCSIIO.RequestFlags = (MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO <<
MRSAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT);
- req_desc->SCSIIO.SMID = index;
+ req_desc->SCSIIO.SMID = htole16(index);
return (req_desc);
}
@@ -3927,7 +3943,7 @@ mrsas_build_mptmfi_passthru(struct mrsas_softc *sc,
struct mrsas_mfi_cmd *mfi_cm
* mrsas_complete_cmd.
*/
- if (frame_hdr->flags & MFI_FRAME_DONT_POST_IN_REPLY_QUEUE)
+ if (frame_hdr->flags & htole16(MFI_FRAME_DONT_POST_IN_REPLY_QUEUE))
mpt_cmd->flags = MFI_FRAME_DONT_POST_IN_REPLY_QUEUE;
io_req = mpt_cmd->io_request;
@@ -3944,12 +3960,12 @@ mrsas_build_mptmfi_passthru(struct mrsas_softc *sc,
struct mrsas_mfi_cmd *mfi_cm
io_req->SGLOffset0 = offsetof(MRSAS_RAID_SCSI_IO_REQUEST, SGL) / 4;
io_req->ChainOffset = sc->chain_offset_mfi_pthru;
- mpi25_ieee_chain->Address = mfi_cmd->frame_phys_addr;
+ mpi25_ieee_chain->Address = htole64(mfi_cmd->frame_phys_addr);
mpi25_ieee_chain->Flags = IEEE_SGE_FLAGS_CHAIN_ELEMENT |
MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR;
- mpi25_ieee_chain->Length = sc->max_chain_frame_sz;
+ mpi25_ieee_chain->Length = htole32(sc->max_chain_frame_sz);
return (0);
}
@@ -4100,7 +4116,7 @@ mrsas_complete_mptmfi_passthru(struct mrsas_softc *sc,
struct mrsas_mfi_cmd *cmd
break;
}
/* See if got an event notification */
- if (cmd->frame->dcmd.opcode == MR_DCMD_CTRL_EVENT_WAIT)
+ if (le32toh(cmd->frame->dcmd.opcode) == MR_DCMD_CTRL_EVENT_WAIT)
mrsas_complete_aen(sc, cmd);
else
mrsas_wakeup(sc, cmd);
@@ -4264,14 +4280,14 @@ megasas_sync_pd_seq_num(struct mrsas_softc *sc,
boolean_t pend)
dcmd->sge_count = 1;
dcmd->timeout = 0;
dcmd->pad_0 = 0;
- dcmd->data_xfer_len = (pd_seq_map_sz);
- dcmd->opcode = (MR_DCMD_SYSTEM_PD_MAP_GET_INFO);
- dcmd->sgl.sge32[0].phys_addr = (pd_seq_h);
- dcmd->sgl.sge32[0].length = (pd_seq_map_sz);
+ dcmd->data_xfer_len = htole32(pd_seq_map_sz);
+ dcmd->opcode = htole32(MR_DCMD_SYSTEM_PD_MAP_GET_INFO);
+ dcmd->sgl.sge32[0].phys_addr = htole32(pd_seq_h & 0xFFFFFFFF);
+ dcmd->sgl.sge32[0].length = htole32(pd_seq_map_sz);
if (pend) {
dcmd->mbox.b[0] = MRSAS_DCMD_MBOX_PEND_FLAG;
- dcmd->flags = (MFI_FRAME_DIR_WRITE);
+ dcmd->flags = htole16(MFI_FRAME_DIR_WRITE);
sc->jbod_seq_cmd = cmd;
if (mrsas_issue_dcmd(sc, cmd)) {
device_printf(sc->mrsas_dev,
@@ -4280,13 +4296,13 @@ megasas_sync_pd_seq_num(struct mrsas_softc *sc,
boolean_t pend)
} else
return 0;
} else
- dcmd->flags = MFI_FRAME_DIR_READ;
+ dcmd->flags = htole16(MFI_FRAME_DIR_READ);
retcode = mrsas_issue_polled(sc, cmd);
if (retcode == ETIMEDOUT)
goto dcmd_timeout;
- if (pd_sync->count > MAX_PHYSICAL_DEVICES) {
+ if (le32toh(pd_sync->count) > MAX_PHYSICAL_DEVICES) {
device_printf(sc->mrsas_dev,
"driver supports max %d JBOD, but FW reports %d\n",
MAX_PHYSICAL_DEVICES, pd_sync->count);
@@ -4364,13 +4380,13 @@ mrsas_get_ld_map_info(struct mrsas_softc *sc)
dcmd->cmd = MFI_CMD_DCMD;
dcmd->cmd_status = 0xFF;
dcmd->sge_count = 1;
- dcmd->flags = MFI_FRAME_DIR_READ;
+ dcmd->flags = htole16(MFI_FRAME_DIR_READ);
dcmd->timeout = 0;
dcmd->pad_0 = 0;
- dcmd->data_xfer_len = sc->current_map_sz;
- dcmd->opcode = MR_DCMD_LD_MAP_GET_INFO;
- dcmd->sgl.sge32[0].phys_addr = map_phys_addr;
- dcmd->sgl.sge32[0].length = sc->current_map_sz;
+ dcmd->data_xfer_len = htole32(sc->current_map_sz);
+ dcmd->opcode = htole32(MR_DCMD_LD_MAP_GET_INFO);
+ dcmd->sgl.sge32[0].phys_addr = htole32(map_phys_addr & 0xFFFFFFFF);
+ dcmd->sgl.sge32[0].length = htole32(sc->current_map_sz);
retcode = mrsas_issue_polled(sc, cmd);
if (retcode == ETIMEDOUT)
@@ -4427,15 +4443,15 @@ mrsas_sync_map_info(struct mrsas_softc *sc)
dcmd->cmd = MFI_CMD_DCMD;
dcmd->cmd_status = 0xFF;
dcmd->sge_count = 1;
- dcmd->flags = MFI_FRAME_DIR_WRITE;
+ dcmd->flags = htole16(MFI_FRAME_DIR_WRITE);
dcmd->timeout = 0;
dcmd->pad_0 = 0;
- dcmd->data_xfer_len = sc->current_map_sz;
+ dcmd->data_xfer_len = htole32(sc->current_map_sz);
dcmd->mbox.b[0] = num_lds;
dcmd->mbox.b[1] = MRSAS_DCMD_MBOX_PEND_FLAG;
- dcmd->opcode = MR_DCMD_LD_MAP_GET_INFO;
- dcmd->sgl.sge32[0].phys_addr = map_phys_addr;
- dcmd->sgl.sge32[0].length = sc->current_map_sz;
+ dcmd->opcode = htole32(MR_DCMD_LD_MAP_GET_INFO);
+ dcmd->sgl.sge32[0].phys_addr = htole32(map_phys_addr & 0xFFFFFFFF);
+ dcmd->sgl.sge32[0].length = htole32(sc->current_map_sz);
sc->map_update_cmd = cmd;
if (mrsas_issue_dcmd(sc, cmd)) {
@@ -4472,17 +4488,17 @@ mrsas_get_pd_info(struct mrsas_softc *sc, u_int16_t
device_id)
memset(sc->pd_info_mem, 0, sizeof(struct mrsas_pd_info));
memset(dcmd->mbox.b, 0, MFI_MBOX_SIZE);
- dcmd->mbox.s[0] = device_id;
+ dcmd->mbox.s[0] = htole16(device_id);
dcmd->cmd = MFI_CMD_DCMD;
dcmd->cmd_status = 0xFF;
dcmd->sge_count = 1;
dcmd->flags = MFI_FRAME_DIR_READ;
dcmd->timeout = 0;
dcmd->pad_0 = 0;
- dcmd->data_xfer_len = sizeof(struct mrsas_pd_info);
- dcmd->opcode = MR_DCMD_PD_GET_INFO;
- dcmd->sgl.sge32[0].phys_addr = (u_int32_t)sc->pd_info_phys_addr;
- dcmd->sgl.sge32[0].length = sizeof(struct mrsas_pd_info);
+ dcmd->data_xfer_len = htole32(sizeof(struct mrsas_pd_info));
+ dcmd->opcode = htole32(MR_DCMD_PD_GET_INFO);
+ dcmd->sgl.sge32[0].phys_addr = htole32((u_int32_t)sc->pd_info_phys_addr
& 0xFFFFFFFF);
+ dcmd->sgl.sge32[0].length = htole32(sizeof(struct mrsas_pd_info));
if (!sc->mask_interrupts)
retcode = mrsas_issue_blocked_cmd(sc, cmd);
@@ -4493,7 +4509,7 @@ mrsas_get_pd_info(struct mrsas_softc *sc, u_int16_t
device_id)
goto dcmd_timeout;
sc->target_list[device_id].interface_type =
- sc->pd_info_mem->state.ddf.pdType.intf;
+ le16toh(sc->pd_info_mem->state.ddf.pdType.intf);
do_ocr = 0;
@@ -4572,6 +4588,7 @@ mrsas_get_pd_list(struct mrsas_softc *sc)
struct MR_PD_ADDRESS *pd_addr;
bus_addr_t pd_list_phys_addr = 0;
struct mrsas_tmp_dcmd *tcmd;
+ u_int16_t dev_id;
cmd = mrsas_get_mfi_cmd(sc);
if (!cmd) {
@@ -4601,13 +4618,13 @@ mrsas_get_pd_list(struct mrsas_softc *sc)
dcmd->cmd = MFI_CMD_DCMD;
dcmd->cmd_status = 0xFF;
dcmd->sge_count = 1;
- dcmd->flags = MFI_FRAME_DIR_READ;
+ dcmd->flags = htole16(MFI_FRAME_DIR_READ);
dcmd->timeout = 0;
dcmd->pad_0 = 0;
- dcmd->data_xfer_len = MRSAS_MAX_PD * sizeof(struct MR_PD_LIST);
- dcmd->opcode = MR_DCMD_PD_LIST_QUERY;
- dcmd->sgl.sge32[0].phys_addr = pd_list_phys_addr;
- dcmd->sgl.sge32[0].length = MRSAS_MAX_PD * sizeof(struct MR_PD_LIST);
+ dcmd->data_xfer_len = htole32(MRSAS_MAX_PD * sizeof(struct MR_PD_LIST));
+ dcmd->opcode = htole32(MR_DCMD_PD_LIST_QUERY);
+ dcmd->sgl.sge32[0].phys_addr = htole32(pd_list_phys_addr & 0xFFFFFFFF);
+ dcmd->sgl.sge32[0].length = htole32(MRSAS_MAX_PD * sizeof(struct
MR_PD_LIST));
if (!sc->mask_interrupts)
retcode = mrsas_issue_blocked_cmd(sc, cmd);
@@ -4620,17 +4637,18 @@ mrsas_get_pd_list(struct mrsas_softc *sc)
/* Get the instance PD list */
pd_count = MRSAS_MAX_PD;
pd_addr = pd_list_mem->addr;
- if (pd_list_mem->count < pd_count) {
+ if (le32toh(pd_list_mem->count) < pd_count) {
memset(sc->local_pd_list, 0,
MRSAS_MAX_PD * sizeof(struct mrsas_pd_list));
- for (pd_index = 0; pd_index < pd_list_mem->count; pd_index++) {
- sc->local_pd_list[pd_addr->deviceId].tid =
pd_addr->deviceId;
- sc->local_pd_list[pd_addr->deviceId].driveType =
- pd_addr->scsiDevType;
- sc->local_pd_list[pd_addr->deviceId].driveState =
+ for (pd_index = 0; pd_index < le32toh(pd_list_mem->count);
pd_index++) {
+ dev_id = le16toh(pd_addr->deviceId);
+ sc->local_pd_list[dev_id].tid = dev_id;
+ sc->local_pd_list[dev_id].driveType =
+ le16toh(pd_addr->scsiDevType);
+ sc->local_pd_list[dev_id].driveState =
MR_PD_STATE_SYSTEM;
- if (sc->target_list[pd_addr->deviceId].target_id ==
0xffff)
- mrsas_add_target(sc, pd_addr->deviceId);
+ if (sc->target_list[dev_id].target_id == 0xffff)
+ mrsas_add_target(sc, dev_id);
pd_addr++;
}
for (pd_index = 0; pd_index < MRSAS_MAX_PD; pd_index++) {
@@ -4711,10 +4729,10 @@ mrsas_get_ld_list(struct mrsas_softc *sc)
dcmd->sge_count = 1;
dcmd->flags = MFI_FRAME_DIR_READ;
dcmd->timeout = 0;
- dcmd->data_xfer_len = sizeof(struct MR_LD_LIST);
- dcmd->opcode = MR_DCMD_LD_GET_LIST;
- dcmd->sgl.sge32[0].phys_addr = ld_list_phys_addr;
- dcmd->sgl.sge32[0].length = sizeof(struct MR_LD_LIST);
+ dcmd->data_xfer_len = htole32(sizeof(struct MR_LD_LIST));
+ dcmd->opcode = htole32(MR_DCMD_LD_GET_LIST);
+ dcmd->sgl.sge32[0].phys_addr = htole32(ld_list_phys_addr);
+ dcmd->sgl.sge32[0].length = htole32(sizeof(struct MR_LD_LIST));
dcmd->pad_0 = 0;
if (!sc->mask_interrupts)
@@ -4730,10 +4748,10 @@ mrsas_get_ld_list(struct mrsas_softc *sc)
#endif
/* Get the instance LD list */
- if (ld_list_mem->ldCount <= sc->fw_supported_vd_count) {
- sc->CurLdCount = ld_list_mem->ldCount;
+ if (le32toh(ld_list_mem->ldCount) <= sc->fw_supported_vd_count) {
+ sc->CurLdCount = le32toh(ld_list_mem->ldCount);
memset(sc->ld_ids, 0xff, MAX_LOGICAL_DRIVES_EXT);
- for (ld_index = 0; ld_index < ld_list_mem->ldCount; ld_index++)
{
+ for (ld_index = 0; ld_index < le32toh(ld_list_mem->ldCount);
ld_index++) {
ids =
ld_list_mem->ldList[ld_index].ref.ld_context.targetId;
drv_tgt_id = ids + MRSAS_MAX_PD;
if (ld_list_mem->ldList[ld_index].state != 0) {
diff --git a/sys/dev/mrsas/mrsas.h b/sys/dev/mrsas/mrsas.h
index fbb08215b7b1..069db02fadff 100644
--- a/sys/dev/mrsas/mrsas.h
+++ b/sys/dev/mrsas/mrsas.h
@@ -165,14 +165,22 @@ do { \
device_printf(sc->mrsas_dev, msg, ##args); \
} while (0)
+#define le32_to_cpus(x) do { *((u_int32_t *)(x)) = le32toh((*(u_int32_t *)x)); } while (0)
+#define le16_to_cpus(x) do { *((u_int16_t *)(x)) = le16toh((*(u_int16_t *)x));
} while (0)
+
/****************************************************************************
* Raid Context structure which describes MegaRAID specific IO Paramenters
* This resides at offset 0x60 where the SGL normally starts in MPT IO Frames
****************************************************************************/
typedef struct _RAID_CONTEXT {
+#if _BYTE_ORDER == _LITTLE_ENDIAN
u_int8_t Type:4;
u_int8_t nseg:4;
+#else
+ u_int8_t nseg:4;
+ u_int8_t Type:4;
+#endif
u_int8_t resvd0;
u_int16_t timeoutValue;
u_int8_t regLockFlags;
@@ -197,12 +205,19 @@ typedef struct _RAID_CONTEXT {
* This resides at offset 0x60 where the SGL normally starts in MPT IO Frames
*/
typedef struct _RAID_CONTEXT_G35 {
+#if _BYTE_ORDER == _LITTLE_ENDIAN
u_int16_t Type:4;
u_int16_t nseg:4;
u_int16_t resvd0:8;
+#else
+ u_int16_t resvd0:8;
+ u_int16_t nseg:4;
+ u_int16_t Type:4;
+#endif
u_int16_t timeoutValue;
union {
struct {
+#if _BYTE_ORDER == _LITTLE_ENDIAN
u_int16_t reserved:1;
u_int16_t sld:1;
u_int16_t c2f:1;
@@ -213,6 +228,18 @@ typedef struct _RAID_CONTEXT_G35 {
u_int16_t log:1;
u_int16_t cpuSel:4;
u_int16_t setDivert:4;
+#else
+ u_int16_t setDivert:4;
+ u_int16_t cpuSel:4;
+ u_int16_t log:1;
+ u_int16_t rw:1;
+ u_int16_t sbs:1;
+ u_int16_t sqn:1;
+ u_int16_t fwn:1;
+ u_int16_t c2f:1;
+ u_int16_t sld:1;
+ u_int16_t reserved:1;
+#endif
} bits;
u_int16_t s;
} routingFlags;
@@ -228,9 +255,15 @@ typedef struct _RAID_CONTEXT_G35 {
u_int8_t RAIDFlags;
u_int8_t spanArm;
u_int16_t configSeqNum;
+#if _BYTE_ORDER == _LITTLE_ENDIAN
u_int16_t numSGE:12;
u_int16_t reserved:3;
u_int16_t streamDetected:1;
+#else
+ u_int16_t streamDetected:1;
+ u_int16_t reserved:3;
+ u_int16_t numSGE:12;
+#endif
u_int8_t resvd2[2];
} RAID_CONTEXT_G35;
@@ -433,9 +466,15 @@ typedef struct _MR_TASK_MANAGE_REQUEST {
MR_TM_REQUEST TmRequest;
union {
struct {
+#if _BYTE_ORDER == _LITTLE_ENDIAN
u_int32_t isTMForLD:1;
u_int32_t isTMForPD:1;
u_int32_t reserved1:30;
+#else
+ u_int32_t reserved1:30;
+ u_int32_t isTMForPD:1;
+ u_int32_t isTMForLD:1;
+#endif
u_int32_t reserved2;
} tmReqFlags;
MR_TM_REPLY TMReply;
@@ -808,6 +847,7 @@ typedef struct _MR_SPAN_BLOCK_INFO {
typedef struct _MR_LD_RAID {
struct {
+#if _BYTE_ORDER == _LITTLE_ENDIAN
u_int32_t fpCapable:1;
u_int32_t raCapable:1;
u_int32_t reserved5:2;
@@ -822,6 +862,22 @@ typedef struct _MR_LD_RAID {
u_int32_t tmCapable:1;
u_int32_t fpCacheBypassCapable:1;
u_int32_t reserved4:5;
+#else
+ u_int32_t reserved4:5;
+ u_int32_t fpCacheBypassCapable:1;
+ u_int32_t tmCapable:1;
+ u_int32_t fpNonRWCapable:1;
+ u_int32_t fpReadAcrossStripe:1;
+ u_int32_t fpWriteAcrossStripe:1;
+ u_int32_t fpReadCapable:1;
+ u_int32_t fpWriteCapable:1;
+ u_int32_t encryptionType:8;
+ u_int32_t pdPiMode:4;
+ u_int32_t ldPiMode:4;
+ u_int32_t reserved5:2;
+ u_int32_t raCapable:1;
+ u_int32_t fpCapable:1;
+#endif
} capability;
u_int32_t reserved6;
u_int64_t size;
@@ -844,9 +900,15 @@ typedef struct _MR_LD_RAID {
u_int16_t seqNum;
struct {
+#if _BYTE_ORDER == _LITTLE_ENDIAN
+ u_int32_t reserved:30;
+ u_int32_t regTypeReqOnReadLsValid:1;
+ u_int32_t ldSyncRequired:1;
+#else
u_int32_t ldSyncRequired:1;
u_int32_t regTypeReqOnReadLsValid:1;
u_int32_t reserved:30;
+#endif
} flags;
u_int8_t LUN[8];
@@ -854,9 +916,15 @@ typedef struct _MR_LD_RAID {
u_int8_t reserved2[3];
u_int32_t logicalBlockLength;
struct {
+#if _BYTE_ORDER == _LITTLE_ENDIAN
+ u_int32_t reserved1:24;
+ u_int32_t LdLogicalBlockExp:4;
+ u_int32_t LdPiExp:4;
+#else
u_int32_t LdPiExp:4;
u_int32_t LdLogicalBlockExp:4;
u_int32_t reserved1:24;
+#endif
} exponent;
u_int8_t reserved3[0x80 - 0x38];
} MR_LD_RAID;
@@ -1039,8 +1107,13 @@ struct MR_PD_CFG_SEQ {
u_int16_t seqNum;
u_int16_t devHandle;
struct {
+#if _BYTE_ORDER == _LITTLE_ENDIAN
u_int8_t tmCapable:1;
u_int8_t reserved:7;
+#else
+ u_int8_t reserved:7;
+ u_int8_t tmCapable:1;
+#endif
} capability;
u_int8_t reserved;
u_int16_t pdTargetId;
@@ -1868,6 +1941,7 @@ struct mrsas_ctrl_prop {
* structure.
*/
struct {
+#if _BYTE_ORDER == _LITTLE_ENDIAN
u_int32_t copyBackDisabled:1;
u_int32_t SMARTerEnabled:1;
u_int32_t prCorrectUnconfiguredAreas:1;
@@ -1899,6 +1973,39 @@ struct mrsas_ctrl_prop {
u_int32_t enableSwZone:1;
u_int32_t limitMaxRateSATA3G:1;
u_int32_t reserved:2;
+#else
+ u_int32_t reserved:2;
+ u_int32_t limitMaxRateSATA3G:1;
+ u_int32_t enableSwZone:1;
+ u_int32_t ignore64ldRestriction:1;
+ u_int32_t disableT10RebuildAssist:1;
+ u_int32_t disableImmediateIO:1;
+ u_int32_t enableAutoLockRecovery:1;
+ u_int32_t enableVirtualCache:1;
+ u_int32_t enableConfigAutoBalance:1;
+ u_int32_t forceSGPIOForQuadOnly:1;
+ u_int32_t useEmergencySparesforSMARTer:1;
+ u_int32_t useUnconfGoodForEmergency:1;
+ u_int32_t useGlobalSparesForEmergency:1;
+ u_int32_t preventPIImport:1;
+ u_int32_t enablePI:1;
+ u_int32_t useDiskActivityForLocate:1;
+ u_int32_t disableCacheBypass:1;
+ u_int32_t enableJBOD:1;
+ u_int32_t disableSpinDownHS:1;
+ u_int32_t allowBootWithPinnedCache:1;
+ u_int32_t disableOnlineCtrlReset:1;
+ u_int32_t enableSecretKeyControl:1;
+ u_int32_t autoEnhancedImport:1;
+ u_int32_t enableSpinDownUnconfigured:1;
+ u_int32_t SSDPatrolReadEnabled:1;
+ u_int32_t SSDSMARTerEnabled:1;
+ u_int32_t disableNCQ:1;
+ u_int32_t useFdeOnly:1;
+ u_int32_t prCorrectUnconfiguredAreas:1;
+ u_int32_t SMARTerEnabled:1;
+ u_int32_t copyBackDisabled:1;
+#endif
} OnOffProperties;
u_int8_t autoSnapVDSpace;
u_int8_t viewSpace;
@@ -2170,6 +2277,7 @@ struct mrsas_ctrl_info {
u_int16_t cacheMemorySize; /* 0x7A2 */
struct { /* 0x7A4 */
+#if _BYTE_ORDER == _LITTLE_ENDIAN
u_int32_t supportPIcontroller:1;
u_int32_t supportLdPIType1:1;
u_int32_t supportLdPIType2:1;
@@ -2194,6 +2302,30 @@ struct mrsas_ctrl_info {
u_int32_t supportUnevenSpans:1;
u_int32_t reserved:11;
+#else
+ u_int32_t reserved:11;
+ u_int32_t supportUnevenSpans:1;
+ u_int32_t dedicatedHotSparesLimited:1;
+ u_int32_t headlessMode:1;
+ u_int32_t supportEmulatedDrives:1;
+ u_int32_t supportResetNow:1;
+ u_int32_t realTimeScheduler:1;
+ u_int32_t supportSSDPatrolRead:1;
+ u_int32_t supportPerfTuning:1;
+ u_int32_t disableOnlinePFKChange:1;
+ u_int32_t supportJBOD:1;
+ u_int32_t supportBootTimePFKChange:1;
+ u_int32_t supportSetLinkSpeed:1;
+ u_int32_t supportEmergencySpares:1;
+ u_int32_t supportSuspendResumeBGops:1;
+ u_int32_t blockSSDWriteCacheChange:1;
+ u_int32_t supportShieldState:1;
+ u_int32_t supportLdBBMInfo:1;
+ u_int32_t supportLdPIType3:1;
+ u_int32_t supportLdPIType2:1;
+ u_int32_t supportLdPIType1:1;
+ u_int32_t supportPIcontroller:1;
+#endif
} adapterOperations2;
u_int8_t driverVersion[32]; /* 0x7A8 */
@@ -2206,6 +2338,7 @@ struct mrsas_ctrl_info {
u_int8_t reserved5[2]; /* 0x7CD reserved */
struct {
+#if _BYTE_ORDER == _LITTLE_ENDIAN
u_int32_t peerIsPresent:1;
u_int32_t peerIsIncompatible:1;
@@ -2214,6 +2347,15 @@ struct mrsas_ctrl_info {
u_int32_t ctrlPropIncompatible:1;
u_int32_t premiumFeatureMismatch:1;
u_int32_t reserved:26;
+#else
+ u_int32_t reserved:26;
+ u_int32_t premiumFeatureMismatch:1;
+ u_int32_t ctrlPropIncompatible:1;
+ u_int32_t fwVersionMismatch:1;
+ u_int32_t hwIncompatible:1;
+ u_int32_t peerIsIncompatible:1;
+ u_int32_t peerIsPresent:1;
+#endif
} cluster;
char clusterId[16]; /* 0x7D4 */
@@ -2221,6 +2363,7 @@ struct mrsas_ctrl_info {
char reserved6[4]; /* 0x7E4 RESERVED FOR IOV */
struct { /* 0x7E8 */
+#if _BYTE_ORDER == _LITTLE_ENDIAN
u_int32_t supportPersonalityChange:2;
u_int32_t supportThermalPollInterval:1;
u_int32_t supportDisableImmediateIO:1;
@@ -2246,11 +2389,39 @@ struct mrsas_ctrl_info {
u_int32_t supportExtendedSSCSize:1;
u_int32_t useSeqNumJbodFP:1;
u_int32_t reserved:7;
+#else
+ u_int32_t reserved:7;
+ u_int32_t useSeqNumJbodFP:1;
+ u_int32_t supportExtendedSSCSize:1;
+ u_int32_t supportDiskCacheSettingForSysPDs:1;
+ u_int32_t supportCPLDUpdate:1;
+ u_int32_t supportTTYLogCompression:1;
+ u_int32_t discardCacheDuringLDDelete:1;
+ u_int32_t supportSecurityonJBOD:1;
+ u_int32_t supportCacheBypassModes:1;
+ u_int32_t supportDisableSESMonitoring:1;
+ u_int32_t supportForceFlash:1;
+ u_int32_t supportNVDRAM:1;
+ u_int32_t supportDrvActivityLEDSetting:1;
+ u_int32_t supportAllowedOpsforDrvRemoval:1;
+ u_int32_t supportHOQRebuild:1;
+ u_int32_t supportForceTo512e:1;
+ u_int32_t supportNVCacheErase:1;
+ u_int32_t supportDebugQueue:1;
+ u_int32_t supportSwZone:1;
+ u_int32_t supportCrashDump:1;
+ u_int32_t supportMaxExtLDs:1;
+ u_int32_t supportT10RebuildAssist:1;
+ u_int32_t supportDisableImmediateIO:1;
+ u_int32_t supportThermalPollInterval:1;
+ u_int32_t supportPersonalityChange:2;
+#endif
} adapterOperations3;
u_int8_t pad_cpld[16];
struct {
+#if _BYTE_ORDER == _LITTLE_ENDIAN
u_int16_t ctrlInfoExtSupported:1;
u_int16_t supportIbuttonLess:1;
u_int16_t supportedEncAlgo:1;
@@ -2260,6 +2431,17 @@ struct mrsas_ctrl_info {
u_int16_t supportPdMapTargetId:1;
u_int16_t FWSwapsBBUVPDInfo:1;
u_int16_t reserved:8;
+#else
+ u_int16_t reserved:8;
+ u_int16_t FWSwapsBBUVPDInfo:1;
+ u_int16_t supportPdMapTargetId:1;
+ u_int16_t supportSESCtrlInMultipathCfg:1;
+ u_int16_t imageUploadSupported:1;
+ u_int16_t supportEncryptedMfc:1;
+ u_int16_t supportedEncAlgo:1;
+ u_int16_t supportIbuttonLess:1;
+ u_int16_t ctrlInfoExtSupported:1;
+#endif
} adapterOperations4;
u_int8_t pad[0x800 - 0x7FE]; /* 0x7FE */
@@ -2332,6 +2514,7 @@ struct mrsas_ctrl_info {
typedef union _MFI_CAPABILITIES {
struct {
+#if _BYTE_ORDER == _LITTLE_ENDIAN
u_int32_t support_fp_remote_lun:1;
u_int32_t support_additional_msix:1;
u_int32_t support_fastpath_wb:1;
@@ -2342,6 +2525,18 @@ typedef union _MFI_CAPABILITIES {
u_int32_t support_ext_queue_depth:1;
u_int32_t support_ext_io_size:1;
u_int32_t reserved:23;
+#else
+ u_int32_t reserved:23;
+ u_int32_t support_ext_io_size:1;
+ u_int32_t support_ext_queue_depth:1;
+ u_int32_t security_protocol_cmds_fw:1;
+ u_int32_t support_core_affinity:1;
+ u_int32_t support_ndrive_r1_lb:1;
+ u_int32_t support_max_255lds:1;
+ u_int32_t support_fastpath_wb:1;
+ u_int32_t support_additional_msix:1;
+ u_int32_t support_fp_remote_lun:1;
+#endif
} mfi_capabilities;
u_int32_t reg;
} MFI_CAPABILITIES;
@@ -2602,9 +2797,15 @@ union mrsas_frame {
#pragma pack(1)
union mrsas_evt_class_locale {
struct {
+#if _BYTE_ORDER == _LITTLE_ENDIAN
u_int16_t locale;
u_int8_t reserved;
int8_t class;
+#else
+ int8_t class;
+ u_int8_t reserved;
+ u_int16_t locale;
+#endif
} __packed members;
u_int32_t word;
@@ -2890,6 +3091,7 @@ typedef struct _MRSAS_DRV_PCI_COMMON_HEADER {
typedef struct _MRSAS_DRV_PCI_LINK_CAPABILITY {
union {
struct {
+#if _BYTE_ORDER == _LITTLE_ENDIAN
u_int32_t linkSpeed:4;
u_int32_t linkWidth:6;
u_int32_t aspmSupport:2;
@@ -2897,6 +3099,15 @@ typedef struct _MRSAS_DRV_PCI_LINK_CAPABILITY {
u_int32_t l1ExitLatency:3;
u_int32_t rsvdp:6;
u_int32_t portNumber:8;
+#else
+ u_int32_t portNumber:8;
+ u_int32_t rsvdp:6;
+ u_int32_t l1ExitLatency:3;
+ u_int32_t losExitLatency:3;
+ u_int32_t aspmSupport:2;
+ u_int32_t linkWidth:6;
+ u_int32_t linkSpeed:4;
+#endif
} bits;
u_int32_t asUlong;
@@ -2908,12 +3119,21 @@ typedef struct _MRSAS_DRV_PCI_LINK_CAPABILITY {
typedef struct _MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY {
union {
struct {
+#if _BYTE_ORDER == _LITTLE_ENDIAN
u_int16_t linkSpeed:4;
u_int16_t negotiatedLinkWidth:6;
u_int16_t linkTrainingError:1;
u_int16_t linkTraning:1;
u_int16_t slotClockConfig:1;
u_int16_t rsvdZ:3;
+#else
+ u_int16_t rsvdZ:3;
+ u_int16_t slotClockConfig:1;
+ u_int16_t linkTraning:1;
+ u_int16_t linkTrainingError:1;
+ u_int16_t negotiatedLinkWidth:6;
+ u_int16_t linkSpeed:4;
+#endif
} bits;
u_int16_t asUshort;
@@ -2967,6 +3187,7 @@ union MR_PD_DDF_TYPE {
struct {
union {
struct {
+#if _BYTE_ORDER == _LITTLE_ENDIAN
u_int16_t forcedPDGUID:1;
u_int16_t inVD:1;
u_int16_t isGlobalSpare:1;
@@ -2974,6 +3195,15 @@ union MR_PD_DDF_TYPE {
u_int16_t isForeign:1;
u_int16_t reserved:7;
u_int16_t intf:4;
+#else
+ u_int16_t intf:4;
+ u_int16_t reserved:7;
+ u_int16_t isForeign:1;
+ u_int16_t isSpare:1;
+ u_int16_t isGlobalSpare:1;
+ u_int16_t inVD:1;
+ u_int16_t forcedPDGUID:1;
+#endif
} pdType;
u_int16_t type;
};
@@ -3004,6 +3234,7 @@ union MR_PROGRESS {
*/
struct MR_PD_PROGRESS {
struct {
+#if _BYTE_ORDER == _LITTLE_ENDIAN
u_int32_t rbld:1;
u_int32_t patrol:1;
u_int32_t clear:1;
@@ -3011,6 +3242,15 @@ struct MR_PD_PROGRESS {
u_int32_t erase:1;
u_int32_t locate:1;
u_int32_t reserved:26;
*** 783 LINES SKIPPED ***
