The branch main has been updated by alc:
URL:
https://cgit.FreeBSD.org/src/commit/?id=1c1acaf6858be301384fd20b402cf2df831507a7
commit 1c1acaf6858be301384fd20b402cf2df831507a7
Author: Alan Cox <a...@freebsd.org>
AuthorDate: 2025-06-28 19:49:26 +0000
Commit: Alan Cox <a...@freebsd.org>
CommitDate: 2025-07-03 21:30:02 +0000
amd64: enable EFER.TCE
Setting this option tells AMD processors that targeted TLB invalidation
instructions, such as invlpg, only have to invalidate cached entries
from the upper levels of the page table that lie along the path to the
targeted virtual address. Otherwise, by default, all cached entries
from the upper levels of the page table are invalidated.
After unmapping a page table page we always perform a TLB invalidation
that will invalidate any cached references to that page table page, so
this option is safe to enable.
Reviewed by: kib, markj
Tested by: dougm
Differential Revision: https://reviews.freebsd.org/D51093
---
sys/amd64/amd64/initcpu.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/sys/amd64/amd64/initcpu.c b/sys/amd64/amd64/initcpu.c
index 05e482f7783b..7f317674907e 100644
--- a/sys/amd64/amd64/initcpu.c
+++ b/sys/amd64/amd64/initcpu.c
@@ -325,6 +325,10 @@ initializecpu(void)
wrmsr(MSR_EFER, msr);
pg_nx = PG_NX;
}
+ if ((amd_feature2 & AMDID2_TCE) != 0) {
+ msr = rdmsr(MSR_EFER) | EFER_TCE;
+ wrmsr(MSR_EFER, msr);
+ }
hw_ibrs_recalculate(false);
hw_ssb_recalculate(false);
amd64_syscall_ret_flush_l1d_recalc();
