The branch stable/14 has been updated by markj:
URL:
https://cgit.FreeBSD.org/src/commit/?id=8de50b4e29ef7496e99597ebbd64bfb6e16dc364
commit 8de50b4e29ef7496e99597ebbd64bfb6e16dc364
Author: Hareshx Sankar Raj <hareshx.sankar....@intel.com>
AuthorDate: 2025-04-30 19:48:44 +0000
Commit: Mark Johnston <ma...@freebsd.org>
CommitDate: 2025-06-20 12:47:27 +0000
qat: update 4xxx capabilities handling
Some capabilities were not properly fused out based on
the hardware slices. Hence updated the function accordingly.
Both PF and VF are changed.
This change also streamlines capability handling for SYM service:
- Lack of UCS slice does not mean that CIPHER capabilities are not
available.
- SYM capabilities should be considered disabled only if both
AUTH and CIPHER capabilities are not present.
- AUTH capability shouldn't disable CIPHER.
SMX slice mask for qat_4xxx is also corrected to check for
both SM3 and SM4 support.
Reviewed by: markj, ziaee
MFC after: 2 weeks
Sponsored by: Intel Corporation
Differential Revision: https://reviews.freebsd.org/D50379
(cherry picked from commit 4da5c15e5c84738903fd306b54b18a0aaf166d5f)
---
sys/dev/qat/qat_hw/qat_4xxx/adf_4xxx_hw_data.c | 98 +++++++++++++---------
sys/dev/qat/qat_hw/qat_4xxx/adf_4xxx_hw_data.h | 4 +-
sys/dev/qat/qat_hw/qat_4xxxvf/adf_4xxxvf_hw_data.c | 89 +++++++++++++-------
sys/dev/qat/qat_hw/qat_4xxxvf/adf_4xxxvf_hw_data.h | 14 +++-
4 files changed, 133 insertions(+), 72 deletions(-)
diff --git a/sys/dev/qat/qat_hw/qat_4xxx/adf_4xxx_hw_data.c
b/sys/dev/qat/qat_hw/qat_4xxx/adf_4xxx_hw_data.c
index 43e530c3a6f1..9a84ad652282 100644
--- a/sys/dev/qat/qat_hw/qat_4xxx/adf_4xxx_hw_data.c
+++ b/sys/dev/qat/qat_hw/qat_4xxx/adf_4xxx_hw_data.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
#include <linux/iopoll.h>
#include <adf_accel_devices.h>
#include <adf_cfg.h>
@@ -212,57 +212,77 @@ adf_4xxx_get_hw_cap(struct adf_accel_dev *accel_dev)
{
device_t pdev = accel_dev->accel_pci_dev.pci_dev;
u32 fusectl1;
- u32 capabilities;
+ u32 capabilities_sym, capabilities_sym_cipher, capabilities_sym_auth,
+ capabilities_asym, capabilities_dc, capabilities_other;
+
+ capabilities_other = ICP_ACCEL_CAPABILITIES_RL;
/* Read accelerator capabilities mask */
fusectl1 = pci_read_config(pdev, ADF_4XXX_FUSECTL1_OFFSET, 4);
- capabilities = ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC |
- ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC |
- ICP_ACCEL_CAPABILITIES_CIPHER |
- ICP_ACCEL_CAPABILITIES_AUTHENTICATION |
- ICP_ACCEL_CAPABILITIES_COMPRESSION |
- ICP_ACCEL_CAPABILITIES_LZ4_COMPRESSION |
- ICP_ACCEL_CAPABILITIES_LZ4S_COMPRESSION |
- ICP_ACCEL_CAPABILITIES_SHA3 | ICP_ACCEL_CAPABILITIES_HKDF |
- ICP_ACCEL_CAPABILITIES_SHA3_EXT | ICP_ACCEL_CAPABILITIES_SM3 |
+
+ capabilities_sym_cipher = ICP_ACCEL_CAPABILITIES_HKDF |
ICP_ACCEL_CAPABILITIES_SM4 | ICP_ACCEL_CAPABILITIES_CHACHA_POLY |
- ICP_ACCEL_CAPABILITIES_AESGCM_SPC | ICP_ACCEL_CAPABILITIES_AES_V2 |
- ICP_ACCEL_CAPABILITIES_RL | ICP_ACCEL_CAPABILITIES_ECEDMONT |
- ICP_ACCEL_CAPABILITIES_CNV_INTEGRITY64;
+ ICP_ACCEL_CAPABILITIES_AESGCM_SPC | ICP_ACCEL_CAPABILITIES_AES_V2;
+ capabilities_sym_auth = ICP_ACCEL_CAPABILITIES_SM3 |
+ ICP_ACCEL_CAPABILITIES_SHA3 | ICP_ACCEL_CAPABILITIES_SHA3_EXT;
+ /* A set bit in fusectl1 means the feature is OFF in this SKU */
if (fusectl1 & ICP_ACCEL_4XXX_MASK_CIPHER_SLICE) {
- capabilities &= ~ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC;
- capabilities &= ~ICP_ACCEL_CAPABILITIES_HKDF;
- capabilities &= ~ICP_ACCEL_CAPABILITIES_CIPHER;
- }
- if (fusectl1 & ICP_ACCEL_4XXX_MASK_AUTH_SLICE) {
- capabilities &= ~ICP_ACCEL_CAPABILITIES_AUTHENTICATION;
- capabilities &= ~ICP_ACCEL_CAPABILITIES_SHA3;
- capabilities &= ~ICP_ACCEL_CAPABILITIES_SHA3_EXT;
- capabilities &= ~ICP_ACCEL_CAPABILITIES_CIPHER;
+ capabilities_sym_cipher &= ~ICP_ACCEL_CAPABILITIES_HKDF;
+ capabilities_sym_cipher &= ~ICP_ACCEL_CAPABILITIES_SM4;
}
- if (fusectl1 & ICP_ACCEL_MASK_PKE_SLICE) {
- capabilities &= ~ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC;
- capabilities &= ~ICP_ACCEL_CAPABILITIES_ECEDMONT;
+
+ if (fusectl1 & ICP_ACCEL_4XXX_MASK_UCS_SLICE) {
+ capabilities_sym_cipher &= ~ICP_ACCEL_CAPABILITIES_CHACHA_POLY;
+ capabilities_sym_cipher &= ~ICP_ACCEL_CAPABILITIES_AESGCM_SPC;
+ capabilities_sym_cipher &= ~ICP_ACCEL_CAPABILITIES_AES_V2;
}
- if (fusectl1 & ICP_ACCEL_4XXX_MASK_COMPRESS_SLICE) {
- capabilities &= ~ICP_ACCEL_CAPABILITIES_COMPRESSION;
- capabilities &= ~ICP_ACCEL_CAPABILITIES_LZ4_COMPRESSION;
- capabilities &= ~ICP_ACCEL_CAPABILITIES_LZ4S_COMPRESSION;
- capabilities &= ~ICP_ACCEL_CAPABILITIES_CNV_INTEGRITY64;
+
+ if (fusectl1 & ICP_ACCEL_4XXX_MASK_AUTH_SLICE) {
+ capabilities_sym_auth &= ~ICP_ACCEL_CAPABILITIES_SM3;
+ capabilities_sym_auth &= ~ICP_ACCEL_CAPABILITIES_SHA3;
+ capabilities_sym_auth &= ~ICP_ACCEL_CAPABILITIES_SHA3_EXT;
}
+
if (fusectl1 & ICP_ACCEL_4XXX_MASK_SMX_SLICE) {
- capabilities &= ~ICP_ACCEL_CAPABILITIES_SM3;
- capabilities &= ~ICP_ACCEL_CAPABILITIES_SM4;
+ capabilities_sym_cipher &= ~ICP_ACCEL_CAPABILITIES_SM4;
+ capabilities_sym_auth &= ~ICP_ACCEL_CAPABILITIES_SM3;
}
- if (fusectl1 & ICP_ACCEL_4XXX_MASK_UCS_SLICE) {
- capabilities &= ~ICP_ACCEL_CAPABILITIES_CHACHA_POLY;
- capabilities &= ~ICP_ACCEL_CAPABILITIES_AESGCM_SPC;
- capabilities &= ~ICP_ACCEL_CAPABILITIES_AES_V2;
- capabilities &= ~ICP_ACCEL_CAPABILITIES_CIPHER;
+
+ if (capabilities_sym_cipher)
+ capabilities_sym_cipher |= ICP_ACCEL_CAPABILITIES_CIPHER;
+
+ if (capabilities_sym_auth)
+ capabilities_sym_auth |= ICP_ACCEL_CAPABILITIES_AUTHENTICATION;
+
+ capabilities_sym = capabilities_sym_cipher | capabilities_sym_auth;
+
+ if (capabilities_sym)
+ capabilities_sym |= ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC;
+
+ capabilities_asym = ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC |
+ ICP_ACCEL_CAPABILITIES_SM2 | ICP_ACCEL_CAPABILITIES_ECEDMONT;
+
+ if (fusectl1 & ICP_ACCEL_4XXX_MASK_PKE_SLICE) {
+ capabilities_asym &= ~ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC;
+ capabilities_asym &= ~ICP_ACCEL_CAPABILITIES_SM2;
+ capabilities_asym &= ~ICP_ACCEL_CAPABILITIES_ECEDMONT;
+ }
+
+ capabilities_dc = ICP_ACCEL_CAPABILITIES_COMPRESSION |
+ ICP_ACCEL_CAPABILITIES_LZ4_COMPRESSION |
+ ICP_ACCEL_CAPABILITIES_LZ4S_COMPRESSION |
+ ICP_ACCEL_CAPABILITIES_CNV_INTEGRITY64;
+
+ if (fusectl1 & ICP_ACCEL_4XXX_MASK_COMPRESS_SLICE) {
+ capabilities_dc &= ~ICP_ACCEL_CAPABILITIES_COMPRESSION;
+ capabilities_dc &= ~ICP_ACCEL_CAPABILITIES_LZ4_COMPRESSION;
+ capabilities_dc &= ~ICP_ACCEL_CAPABILITIES_LZ4S_COMPRESSION;
+ capabilities_dc &= ~ICP_ACCEL_CAPABILITIES_CNV_INTEGRITY64;
}
- return capabilities;
+ return capabilities_sym | capabilities_dc | capabilities_asym |
+ capabilities_other;
}
static u32
diff --git a/sys/dev/qat/qat_hw/qat_4xxx/adf_4xxx_hw_data.h
b/sys/dev/qat/qat_hw/qat_4xxx/adf_4xxx_hw_data.h
index b6a5da92fdb5..c35ebbcadcd7 100644
--- a/sys/dev/qat/qat_hw/qat_4xxx/adf_4xxx_hw_data.h
+++ b/sys/dev/qat/qat_hw/qat_4xxx/adf_4xxx_hw_data.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007 - 2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
#ifndef ADF_4XXX_HW_DATA_H_
#define ADF_4XXX_HW_DATA_H_
@@ -105,7 +105,7 @@ enum icp_qat_4xxx_slice_mask {
ICP_ACCEL_4XXX_MASK_COMPRESS_SLICE = BIT(3),
ICP_ACCEL_4XXX_MASK_UCS_SLICE = BIT(4),
ICP_ACCEL_4XXX_MASK_EIA3_SLICE = BIT(5),
- ICP_ACCEL_4XXX_MASK_SMX_SLICE = BIT(6),
+ ICP_ACCEL_4XXX_MASK_SMX_SLICE = BIT(7),
};
void adf_init_hw_data_4xxx(struct adf_hw_device_data *hw_data, u32 id);
diff --git a/sys/dev/qat/qat_hw/qat_4xxxvf/adf_4xxxvf_hw_data.c
b/sys/dev/qat/qat_hw/qat_4xxxvf/adf_4xxxvf_hw_data.c
index 27e5ef8162ab..f3d4ae3c7b38 100644
--- a/sys/dev/qat/qat_hw/qat_4xxxvf/adf_4xxxvf_hw_data.c
+++ b/sys/dev/qat/qat_hw/qat_4xxxvf/adf_4xxxvf_hw_data.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
#include <adf_accel_devices.h>
#include <adf_cfg.h>
#include <adf_common_drv.h>
@@ -133,45 +133,74 @@ adf_4xxxvf_get_hw_cap(struct adf_accel_dev *accel_dev)
{
device_t pdev = accel_dev->accel_pci_dev.pci_dev;
u32 vffusectl1;
- u32 capabilities;
-
- capabilities = ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC +
- ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC +
- ICP_ACCEL_CAPABILITIES_CIPHER +
- ICP_ACCEL_CAPABILITIES_AUTHENTICATION +
- ICP_ACCEL_CAPABILITIES_COMPRESSION +
- ICP_ACCEL_CAPABILITIES_SHA3_EXT + ICP_ACCEL_CAPABILITIES_SM2 +
- ICP_ACCEL_CAPABILITIES_SM3 + ICP_ACCEL_CAPABILITIES_SM4 +
- ICP_ACCEL_CAPABILITIES_CHACHA_POLY +
- ICP_ACCEL_CAPABILITIES_AESGCM_SPC +
- ICP_ACCEL_CAPABILITIES_CNV_INTEGRITY64 +
- ICP_ACCEL_CAPABILITIES_LZ4_COMPRESSION +
- ICP_ACCEL_CAPABILITIES_LZ4S_COMPRESSION;
+ u32 capabilities_sym, capabilities_sym_cipher, capabilities_sym_auth,
+ capabilities_asym, capabilities_dc;
/* Get fused capabilities */
vffusectl1 = pci_read_config(pdev, ADF_4XXXIOV_VFFUSECTL1_OFFSET, 4);
- if (vffusectl1 & BIT(7)) {
- capabilities &=
- ~(ICP_ACCEL_CAPABILITIES_SM3 + ICP_ACCEL_CAPABILITIES_SM4);
+ capabilities_sym_cipher = ICP_ACCEL_CAPABILITIES_HKDF |
+ ICP_ACCEL_CAPABILITIES_SM4 | ICP_ACCEL_CAPABILITIES_CHACHA_POLY |
+ ICP_ACCEL_CAPABILITIES_AESGCM_SPC | ICP_ACCEL_CAPABILITIES_AES_V2;
+ capabilities_sym_auth = ICP_ACCEL_CAPABILITIES_SM3 |
+ ICP_ACCEL_CAPABILITIES_SHA3 | ICP_ACCEL_CAPABILITIES_SHA3_EXT;
+
+ /* A set bit in vffusectl1 means the feature is OFF in this SKU */
+ if (vffusectl1 & ICP_ACCEL_4XXXVF_MASK_CIPHER_SLICE) {
+ capabilities_sym_cipher &= ~ICP_ACCEL_CAPABILITIES_HKDF;
+ capabilities_sym_cipher &= ~ICP_ACCEL_CAPABILITIES_SM4;
}
- if (vffusectl1 & BIT(6)) {
- capabilities &= ~ICP_ACCEL_CAPABILITIES_SM3;
+
+ if (vffusectl1 & ICP_ACCEL_4XXXVF_MASK_UCS_SLICE) {
+ capabilities_sym_cipher &= ~ICP_ACCEL_CAPABILITIES_CHACHA_POLY;
+ capabilities_sym_cipher &= ~ICP_ACCEL_CAPABILITIES_AESGCM_SPC;
+ capabilities_sym_cipher &= ~ICP_ACCEL_CAPABILITIES_AES_V2;
}
- if (vffusectl1 & BIT(3)) {
- capabilities &= ~(ICP_ACCEL_CAPABILITIES_COMPRESSION +
- ICP_ACCEL_CAPABILITIES_CNV_INTEGRITY64);
+
+ if (vffusectl1 & ICP_ACCEL_4XXXVF_MASK_AUTH_SLICE) {
+ capabilities_sym_auth &= ~ICP_ACCEL_CAPABILITIES_SM3;
+ capabilities_sym_auth &= ~ICP_ACCEL_CAPABILITIES_SHA3;
+ capabilities_sym_auth &= ~ICP_ACCEL_CAPABILITIES_SHA3_EXT;
}
- if (vffusectl1 & BIT(2)) {
- capabilities &= ~ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC;
+
+ if (vffusectl1 & ICP_ACCEL_4XXXVF_MASK_SMX_SLICE) {
+ capabilities_sym_cipher &= ~ICP_ACCEL_CAPABILITIES_SM4;
+ capabilities_sym_auth &= ~ICP_ACCEL_CAPABILITIES_SM3;
}
- if (vffusectl1 & BIT(1)) {
- capabilities &= ~ICP_ACCEL_CAPABILITIES_AUTHENTICATION;
+
+ if (capabilities_sym_cipher)
+ capabilities_sym_cipher |= ICP_ACCEL_CAPABILITIES_CIPHER;
+
+ if (capabilities_sym_auth)
+ capabilities_sym_auth |= ICP_ACCEL_CAPABILITIES_AUTHENTICATION;
+
+ capabilities_sym = capabilities_sym_cipher | capabilities_sym_auth;
+
+ if (capabilities_sym)
+ capabilities_sym |= ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC;
+
+ capabilities_asym = ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC |
+ ICP_ACCEL_CAPABILITIES_SM2 | ICP_ACCEL_CAPABILITIES_ECEDMONT;
+
+ if (vffusectl1 & ICP_ACCEL_4XXXVF_MASK_PKE_SLICE) {
+ capabilities_asym &= ~ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC;
+ capabilities_asym &= ~ICP_ACCEL_CAPABILITIES_SM2;
+ capabilities_asym &= ~ICP_ACCEL_CAPABILITIES_ECEDMONT;
}
- if (vffusectl1 & BIT(0)) {
- capabilities &= ~ICP_ACCEL_CAPABILITIES_CIPHER;
+
+ capabilities_dc = ICP_ACCEL_CAPABILITIES_COMPRESSION |
+ ICP_ACCEL_CAPABILITIES_LZ4_COMPRESSION |
+ ICP_ACCEL_CAPABILITIES_LZ4S_COMPRESSION |
+ ICP_ACCEL_CAPABILITIES_CNV_INTEGRITY64;
+
+ if (vffusectl1 & ICP_ACCEL_4XXXVF_MASK_COMPRESS_SLICE) {
+ capabilities_dc &= ~ICP_ACCEL_CAPABILITIES_COMPRESSION;
+ capabilities_dc &= ~ICP_ACCEL_CAPABILITIES_LZ4_COMPRESSION;
+ capabilities_dc &= ~ICP_ACCEL_CAPABILITIES_LZ4S_COMPRESSION;
+ capabilities_dc &= ~ICP_ACCEL_CAPABILITIES_CNV_INTEGRITY64;
}
- return capabilities;
+
+ return capabilities_sym | capabilities_dc | capabilities_asym;
}
static void
diff --git a/sys/dev/qat/qat_hw/qat_4xxxvf/adf_4xxxvf_hw_data.h
b/sys/dev/qat/qat_hw/qat_4xxxvf/adf_4xxxvf_hw_data.h
index 83c034f543c9..a702fc69dde7 100644
--- a/sys/dev/qat/qat_hw/qat_4xxxvf/adf_4xxxvf_hw_data.h
+++ b/sys/dev/qat/qat_hw/qat_4xxxvf/adf_4xxxvf_hw_data.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright(c) 2007-2022 Intel Corporation */
+/* Copyright(c) 2007-2025 Intel Corporation */
#ifndef ADF_4XXXVF_HW_DATA_H_
#define ADF_4XXXVF_HW_DATA_H_
@@ -27,6 +27,18 @@
#define ADF_4XXXIOV_VFFUSECTL4_OFFSET (0x1C4)
#define ADF_4XXXIOV_VFFUSECTL5_OFFSET (0x1C8)
+/*qat_4xxxvf fuse bits are same as qat_4xxx*/
+enum icp_qat_4xxxvf_slice_mask {
+ ICP_ACCEL_4XXXVF_MASK_CIPHER_SLICE = 0x01,
+ ICP_ACCEL_4XXXVF_MASK_AUTH_SLICE = 0x02,
+ ICP_ACCEL_4XXXVF_MASK_PKE_SLICE = 0x04,
+ ICP_ACCEL_4XXXVF_MASK_COMPRESS_SLICE = 0x08,
+ ICP_ACCEL_4XXXVF_MASK_UCS_SLICE = 0x10,
+ ICP_ACCEL_4XXXVF_MASK_EIA3_SLICE = 0x20,
+ /*SM3&SM4 are indicated by same bit*/
+ ICP_ACCEL_4XXXVF_MASK_SMX_SLICE = 0x80,
+};
+
void adf_init_hw_data_4xxxiov(struct adf_hw_device_data *hw_data);
void adf_clean_hw_data_4xxxiov(struct adf_hw_device_data *hw_data);
u32 adf_4xxxvf_get_hw_cap(struct adf_accel_dev *accel_dev);
