The branch stable/13 has been updated by kib:
URL:
https://cgit.FreeBSD.org/src/commit/?id=6b771774c5c6da6286354ebf9b8e2e7432a32dde
commit 6b771774c5c6da6286354ebf9b8e2e7432a32dde
Author: Konstantin Belousov <k...@freebsd.org>
AuthorDate: 2024-04-07 01:25:46 +0000
Commit: Konstantin Belousov <k...@freebsd.org>
CommitDate: 2024-04-17 08:13:18 +0000
pcireg.h: Add AMD IOMMU Base Cap definitions
(cherry picked from commit 33adb388c78ee48efbdc9b497fe2224397fdee84)
---
sys/dev/pci/pcireg.h | 52 ++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 52 insertions(+)
diff --git a/sys/dev/pci/pcireg.h b/sys/dev/pci/pcireg.h
index c94decd8ef2a..623deb8b4505 100644
--- a/sys/dev/pci/pcireg.h
+++ b/sys/dev/pci/pcireg.h
@@ -1125,4 +1125,56 @@
#define PCIM_ACS_UNCLAIMED_REQ_REDIRECT_CTL 0x1000
#define PCIR_ACS_EGRESS_CONTROL_VECTOR 0x8
+/*
+ * AMD IOMMU Base Capability
+ * From AMD I/O Virtualization Technology (IOMMU) Specification
+ * Publication # 48882 Revision: 3.09-PUB Date: October 2023
+ */
+#define PCIR_AMDIOMMU_CAP_HEADER 0x0000
+#define PCIR_AMDIOMMU_BASE_LOW 0x0004
+#define PCIR_AMDIOMMU_BASE_HIGH 0x0008
+#define PCIR_AMDIOMMU_RANGE 0x000c
+#define PCIR_AMDIOMMU_MISC0 0x0010
+#define PCIR_AMDIOMMU_MISC1 0x0014
+
+#define PCIM_AMDIOMMU_CAP_CAPEXT (1 << 28)
+#define PCIM_AMDIOMMU_CAP_EFR (1 << 27)
+#define PCIM_AMDIOMMU_CAP_NPCACHE (1 << 26)
+#define PCIM_AMDIOMMU_CAP_HTTUN (1 << 25)
+#define PCIM_AMDIOMMU_CAP_IOTLB (1 << 24)
+#define PCIM_AMDIOMMU_CAP_REV_MASK (0x1f << 19)
+#define PCIM_AMDIOMMU_CAP_REV_VAL (0x1 << 19)
+#define PCIM_AMDIOMMU_CAP_TYPE_MASK (7 << 16)
+#define PCIM_AMDIOMMU_CAP_TYPE_VAL (0x3 << 16)
+
+#define PCIM_AMDIOMMU_BASE_LOW_EN 0x00000001
+#define PCIM_AMDIOMMU_BASE_LOW_ADDRM 0xffffc000
+
+#define PCIM_AMDIOMMU_RANGE_UNITID_MASK 0x1f
+#define PCIM_AMDIOMMU_RANGE_RNGVALID (1 << 7)
+#define PCIM_AMDIOMMU_RANGE_BUSNUM_MASK (0xffffu << 8)
+#define PCIM_AMDIOMMU_RANGE_FIRSTDEV_MASK (0xffffu << 16)
+#define PCIM_AMDIOMMU_RANGE_LASTDEV_MASK (0xffffu << 24)
+
+#define PCIM_AMDIOMMU_MISC0_MSINUMPPR_MASK (0x1f << 27)
+#define PCIM_AMDIOMMU_MISC0_HTATSRESV (1 << 22)
+#define PCIM_AMDIOMMU_MISC0_VASIZE_MASK (0x7f << 15)
+#define PCIM_AMDIOMMU_MISC0_PASIZE_MASK (0x7f << 8)
+#define PCIM_AMDIOMMU_MISC0_GVASIZE_MASK (0x3 << 5)
+#define PCIM_AMDIOMMU_MISC0_MSINUM_MASK 0x1f
+
+#define PCIM_AMDIOMMU_MISC0_VASIZE_32 (0x20 << 15)
+#define PCIM_AMDIOMMU_MISC0_VASIZE_40 (0x28 << 15)
+#define PCIM_AMDIOMMU_MISC0_VASIZE_48 (0x30 << 15)
+#define PCIM_AMDIOMMU_MISC0_VASIZE_64 (0x40 << 15)
+
+#define PCIM_AMDIOMMU_MISC0_PASIZE_40 (0x28 << 8)
+#define PCIM_AMDIOMMU_MISC0_PASIZE_48 (0x30 << 8)
+#define PCIM_AMDIOMMU_MISC0_PASIZE_52 (0x34 << 8)
+
+#define PCIM_AMDIOMMU_MISC0_GVASIZE_48 (0x2 << 5)
+#define PCIM_AMDIOMMU_MISC0_GVASIZE_57 (0x3 << 5)
+
+#define PCIM_AMDIOMMU_MISC1_MSINUMGA_MASK 0x1f
+
#endif /* __PCI_PCIREG_H */
