The branch main has been updated by andrew: URL: https://cgit.FreeBSD.org/src/commit/?id=f12952eaeeba706725d888a46ff24baa2ac420d7
commit f12952eaeeba706725d888a46ff24baa2ac420d7 Author: Andrew Turner <[email protected]> AuthorDate: 2023-08-03 18:02:25 +0000 Commit: Andrew Turner <[email protected]> CommitDate: 2023-08-03 18:13:17 +0000 arm64: Comment out some ID registers Older toolchains don't support reading these registers. Until a fix is added comment them out. Reported by: jhb Sponsored by: Arm Ltd --- sys/arm64/arm64/identcpu.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/sys/arm64/arm64/identcpu.c b/sys/arm64/arm64/identcpu.c index 2347d27c69e1..4beb34b04381 100644 --- a/sys/arm64/arm64/identcpu.c +++ b/sys/arm64/arm64/identcpu.c @@ -139,11 +139,15 @@ struct cpu_desc { uint64_t id_aa64mmfr0; uint64_t id_aa64mmfr1; uint64_t id_aa64mmfr2; +#ifdef NOTYET uint64_t id_aa64mmfr3; uint64_t id_aa64mmfr4; +#endif uint64_t id_aa64pfr0; uint64_t id_aa64pfr1; +#ifdef NOTYET uint64_t id_aa64pfr2; +#endif uint64_t id_aa64zfr0; uint64_t ctr; #ifdef COMPAT_FREEBSD32 @@ -1268,6 +1272,7 @@ static const struct mrs_field id_aa64mmfr2_fields[] = { }; +#ifdef NOTYET /* ID_AA64MMFR2_EL1 */ static const struct mrs_field_value id_aa64mmfr3_spec_fpacc[] = { MRS_FIELD_VALUE_NONE_IMPL(ID_AA64MMFR3, Spec_FPACC, NONE, IMPL), @@ -1303,6 +1308,7 @@ static const struct mrs_field id_aa64mmfr3_fields[] = { static const struct mrs_field id_aa64mmfr4_fields[] = { MRS_FIELD_END, }; +#endif /* ID_AA64PFR0_EL1 */ @@ -1543,10 +1549,12 @@ static const struct mrs_field id_aa64pfr1_fields[] = { }; +#ifdef NOTYET /* ID_AA64PFR2_EL1 */ static const struct mrs_field id_aa64pfr2_fields[] = { MRS_FIELD_END, }; +#endif /* ID_AA64ZFR0_EL1 */ @@ -1846,12 +1854,16 @@ static const struct mrs_user_reg user_regs[] = { USER_REG(ID_AA64MMFR0_EL1, id_aa64mmfr0), USER_REG(ID_AA64MMFR1_EL1, id_aa64mmfr1), USER_REG(ID_AA64MMFR2_EL1, id_aa64mmfr2), +#ifdef NOTYET USER_REG(ID_AA64MMFR3_EL1, id_aa64mmfr3), USER_REG(ID_AA64MMFR4_EL1, id_aa64mmfr4), +#endif USER_REG(ID_AA64PFR0_EL1, id_aa64pfr0), USER_REG(ID_AA64PFR1_EL1, id_aa64pfr1), +#ifdef NOTYET USER_REG(ID_AA64PFR2_EL1, id_aa64pfr2), +#endif USER_REG(ID_AA64ZFR0_EL1, id_aa64zfr0), @@ -2560,10 +2572,12 @@ print_cpu_features(u_int cpu, struct cpu_desc *desc, print_id_register(sb, "Processor Features 1", desc->id_aa64pfr1, id_aa64pfr1_fields); +#ifdef NOTYET /* AArch64 Processor Feature Register 2 */ if (SHOULD_PRINT_REG(id_aa64pfr2)) print_id_register(sb, "Processor Features 2", desc->id_aa64pfr2, id_aa64pfr2_fields); +#endif /* AArch64 Memory Model Feature Register 0 */ if (SHOULD_PRINT_REG(id_aa64mmfr0)) @@ -2580,6 +2594,7 @@ print_cpu_features(u_int cpu, struct cpu_desc *desc, print_id_register(sb, "Memory Model Features 2", desc->id_aa64mmfr2, id_aa64mmfr2_fields); +#ifdef NOTYET /* AArch64 Memory Model Feature Register 3 */ if (SHOULD_PRINT_REG(id_aa64mmfr3)) print_id_register(sb, "Memory Model Features 3", @@ -2589,6 +2604,7 @@ print_cpu_features(u_int cpu, struct cpu_desc *desc, if (SHOULD_PRINT_REG(id_aa64mmfr4)) print_id_register(sb, "Memory Model Features 4", desc->id_aa64mmfr4, id_aa64mmfr4_fields); +#endif /* AArch64 Debug Feature Register 0 */ if (SHOULD_PRINT_REG(id_aa64dfr0)) @@ -2704,11 +2720,15 @@ identify_cpu(u_int cpu) desc->id_aa64mmfr0 = READ_SPECIALREG(id_aa64mmfr0_el1); desc->id_aa64mmfr1 = READ_SPECIALREG(id_aa64mmfr1_el1); desc->id_aa64mmfr2 = READ_SPECIALREG(id_aa64mmfr2_el1); +#ifdef NOTYET desc->id_aa64mmfr3 = READ_SPECIALREG(id_aa64mmfr3_el1); desc->id_aa64mmfr4 = READ_SPECIALREG(id_aa64mmfr4_el1); +#endif desc->id_aa64pfr0 = READ_SPECIALREG(id_aa64pfr0_el1); desc->id_aa64pfr1 = READ_SPECIALREG(id_aa64pfr1_el1); +#ifdef NOTYET desc->id_aa64pfr2 = READ_SPECIALREG(id_aa64pfr2_el1); +#endif /* * ID_AA64ZFR0_EL1 is only valid when at least one of:
