The branch stable/13 has been updated by markj:
URL:
https://cgit.FreeBSD.org/src/commit/?id=5000c6519a87c9d46ce62c8d406919b582978fc3
commit 5000c6519a87c9d46ce62c8d406919b582978fc3
Author: Mark Johnston <ma...@freebsd.org>
AuthorDate: 2023-03-21 13:36:58 +0000
Commit: Mark Johnston <ma...@freebsd.org>
CommitDate: 2023-05-09 14:01:15 +0000
dtrace: Sync dis_tables.c with illumos
This brings in the following commits:
commit 584b574a3b16c6772c8204ec1d1c957c56f22a87
12174 i86pc: variable may be used uninitialized
Author: Toomas Soome <tso...@me.com>
Reviewed by: John Levon <john.le...@joyent.com>
Reviewed by: Andrew Stormont <astorm...@racktopsystems.com>
Approved by: Dan McDonald <dan...@joyent.com>
commit a25e615d76804404e5fc63897a9196d4f92c3f5e
12371 dis x86 EVEX prefix mishandled
12372 dis EVEX encoding SIB mishandled
12373 dis support for EVEX vaes instructions
12374 dis support for EVEX vpclmulqdq instructions
12375 dis support for gfni instructions
Author: Robert Mustacchi <r...@fingolfin.org>
Reviewed by: Jerry Jelinek <jerry.jeli...@joyent.com>
Approved by: Joshua M. Clulow <j...@sysmgr.org>
commit c1e9bf00765d7ac9cf1986575e4489dd8710d9b1
12369 dis WBNOINVD support
Author: Robert Mustacchi <r...@joyent.com>
Reviewed by: Hans Rosenfeld <hans.rosenf...@joyent.com>
Reviewed by: Jerry Jelinek <jerry.jeli...@joyent.com>
Reviewed by: Andy Fiddaman <a...@omniosce.org>
Reviewed by: Toomas Soome <tso...@me.com>
Approved by: Dan McDonald <dan...@joyent.com>
commit e4f6ce7088a7dd335b9edf4774325f888692e5fb
10893 Need support for new Cascade Lake Instructions
Author: Robert Mustacchi <r...@joyent.com>
Reviewed by: Hans Rosenfeld <hans.rosenf...@joyent.com>
Reviewed by: Dan McDonald <dan...@joyent.com>
Reviewed by: Richard Lowe <richl...@richlowe.net>
Approved by: Gordon Ross <g...@nexenta.com>
commit cff040f3ef42d16ae655969398f5a5e6e700b85e
10226 Need support for new EPYC ISA extensions
Author: Robert Mustacchi <r...@joyent.com>
Reviewed by: Hans Rosenfeld <hans.rosenf...@joyent.com>
Reviewed by: Jason King <jason.k...@joyent.com>
Reviewed by: Richard Lowe <richl...@richlowe.net>
Approved by: Dan McDonald <dan...@joyent.com>
commit d242cdf5288b86d9070d88791c8ee696612becdc
8492 AVX512 dis - legacy logical instructions
Author: Jerry Jelinek <jerry.jeli...@joyent.com>
Reviewed by: Robert Mustacchi <r...@joyent.com>
Reviewed by: Gordon Ross <gordon.w.r...@gmail.com>
Approved by: Richard Lowe <richl...@richlowe.net>
commit 81b505b772ab015c588c56bb116239ee549b6eee
8384 AVX512 dis - EVEX prefix support
8385 32-bit avx dis test mishandles EVEX prefix
8386 32-bit bound dis is incorrect
Author: Jerry Jelinek <jerry.jeli...@joyent.com>
Reviewed by: Robert Mustacchi <r...@joyent.com>
Reviewed by: Gordon Ross <gordon.w.r...@gmail.com>
Approved by: Richard Lowe <richl...@richlowe.net>
commit 92381362ae635a3bea638d87b7119f1623b6212e
8319 dis support for new xsave instructions
Author: Jerry Jelinek <jerry.jeli...@joyent.com>
Reviewed by: Robert Mustacchi <r...@joyent.com>
Reviewed by: Gordon Ross <gordon.w.r...@gmail.com>
Approved by: Richard Lowe <richl...@richlowe.net>
commit a4e73d5d60e566669c550027fae2b1d87b4be2b4
8240 AVX512 dis - opmask instruction support
Author: Jerry Jelinek <jerry.jeli...@joyent.com>
Reviewed by: Robert Mustacchi <r...@joyent.com>
Reviewed by: Toomas Soome <tso...@me.com>
Approved by: Gordon Ross <gordon.w.r...@gmail.com>
959b2dfd39979fe8a9a315a52741d009eb168822
7825 want avx dis tests
7826 PCLMULQDQ psuedo-ops aren't properly described in dis
7827 dis tests for f16c, movbe, cpuid, msr, tsc, fence instrs
7828 sysenter and sysexit dis should be allowed in 64-bit x86
Author: Robert Mustacchi <r...@joyent.com>
Reviewed by: Jerry Jelinek <jerry.jeli...@joyent.com>
Approved by: Richard Lowe <richl...@richlowe.net>
MFC after: 2 weeks
(cherry picked from commit 722b2e2f9aa64e6ff4dec346951bd4b56cd27a8d)
---
sys/cddl/dev/dtrace/x86/dis_tables.c | 1604 +++++++++++++++++++++++++++++-----
1 file changed, 1370 insertions(+), 234 deletions(-)
diff --git a/sys/cddl/dev/dtrace/x86/dis_tables.c
b/sys/cddl/dev/dtrace/x86/dis_tables.c
index d130b3ac335e..ad3b453f8845 100644
--- a/sys/cddl/dev/dtrace/x86/dis_tables.c
+++ b/sys/cddl/dev/dtrace/x86/dis_tables.c
@@ -21,7 +21,8 @@
*/
/*
* Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved.
- * Copyright 2016 Joyent, Inc.
+ * Copyright 2019 Joyent, Inc.
+ * Copyright 2020 Robert Mustacchi
*/
/*
@@ -30,7 +31,7 @@
*/
/* Copyright (c) 1988 AT&T */
-/* All Rights Reserved */
+/* All Rights Reserved */
/*
* $FreeBSD$
@@ -48,8 +49,8 @@
*
* The behavior of this file can be controlled by one of the following flags:
*
- * DIS_TEXT Include text for disassembly
- * DIS_MEM Include memory-size calculations
+ * DIS_TEXT Include text for disassembly
+ * DIS_MEM Include memory-size calculations
*
* Either or both of these can be defined.
*
@@ -69,7 +70,7 @@ extern size_t strlcat(char *, const char *, size_t);
#endif
-#define TERM 0 /* used to indicate that the 'indirect'
*/
+#define TERM 0 /* used to indicate that the 'indirect'
*/
/* field terminates - no pointer. */
/* Used to decode instructions. */
@@ -88,7 +89,8 @@ typedef struct instable {
uint_t it_invalid32:1; /* invalid in IA32 */
uint_t it_stackop:1; /* push/pop stack operation */
uint_t it_vexwoxmm:1; /* VEX instructions that don't
use XMM/YMM */
- uint_t it_avxsuf:1; /* AVX suffix required */
+ uint_t it_avxsuf:2; /* AVX2/AVX512 suffix rqd. */
+ uint_t it_vexopmask:1; /* VEX inst. that use opmask */
} instable_t;
/*
@@ -118,7 +120,7 @@ enum {
SEG,
MR,
RM,
- RM_66r, /* RM, but with a required 0x66 prefix */
+ RM_66r, /* RM, but with a required 0x66 prefix */
IA,
MA,
SD,
@@ -137,7 +139,7 @@ enum {
NORM, /* instructions w/o ModR/M byte, no memory access */
IMPLMEM, /* instructions w/o ModR/M byte, implicit mem access */
O, /* for call */
- JTAB, /* jump table */
+ JTAB, /* jump table */
IMUL, /* for 186 iimul instr */
CBW, /* so data16 can be evaluated for cbw and variants */
MvI, /* for 186 logicals */
@@ -172,7 +174,7 @@ enum {
MMO, /* Prefixable MMX/SIMD-Int mm/mem -> mm */
MMOIMPL, /* Prefixable MMX/SIMD-Int mm -> mm (mem) */
MMO3P, /* Prefixable MMX/SIMD-Int mm -> r32,imm8 */
- MMOM3, /* Prefixable MMX/SIMD-Int mm -> r32 */
+ MMOM3, /* Prefixable MMX/SIMD-Int mm -> r32 */
MMOS, /* Prefixable MMX/SIMD-Int mm -> mm/mem */
MMOMS, /* Prefixable MMX/SIMD-Int mm -> mem */
MMOPM, /* MMX/SIMD-Int mm/mem -> mm,imm8 */
@@ -190,33 +192,34 @@ enum {
XMMOXMM, /* Prefixable SIMD xmm/mem -> mm */
XMMOM, /* Prefixable SIMD xmm -> mem */
XMMOMS, /* Prefixable SIMD mem -> xmm */
- XMM, /* SIMD xmm/mem -> xmm */
+ XMM, /* SIMD xmm/mem -> xmm */
XMM_66r, /* SIMD 0x66 prefix required xmm/mem -> xmm */
- XMM_66o, /* SIMD 0x66 prefix optional xmm/mem -> xmm */
+ XMM_66o, /* SIMD 0x66 prefix optional xmm/mem -> xmm */
XMMXIMPL, /* SIMD xmm -> xmm (mem) */
XMM3P, /* SIMD xmm -> r32,imm8 */
XMM3PM_66r, /* SIMD 0x66 prefix required xmm -> r32/mem,imm8
*/
- XMMP, /* SIMD xmm/mem w/to xmm,imm8 */
+ XMMP, /* SIMD xmm/mem w/to xmm,imm8 */
XMMP_66o, /* SIMD 0x66 prefix optional xmm/mem w/to xmm,imm8 */
XMMP_66r, /* SIMD 0x66 prefix required xmm/mem w/to xmm,imm8 */
- XMMPRM, /* SIMD r32/mem -> xmm,imm8 */
+ XMMPRM, /* SIMD r32/mem -> xmm,imm8 */
XMMPRM_66r, /* SIMD 0x66 prefix required r32/mem -> xmm,imm8 */
XMMS, /* SIMD xmm -> xmm/mem */
- XMMM, /* SIMD mem -> xmm */
+ XMMM, /* SIMD mem -> xmm */
XMMM_66r, /* SIMD 0x66 prefix required mem -> xmm */
XMMMS, /* SIMD xmm -> mem */
- XMM3MX, /* SIMD r32/mem -> xmm */
- XMM3MXS, /* SIMD xmm -> r32/mem */
- XMMSH, /* SIMD xmm,imm8 */
- XMMXM3, /* SIMD xmm/mem -> r32 */
- XMMX3, /* SIMD xmm -> r32 */
- XMMXMM, /* SIMD xmm/mem -> mm */
- XMMMX, /* SIMD mm -> xmm */
- XMMXM, /* SIMD xmm -> mm */
- XMMX2I, /* SIMD xmm -> xmm,
imm, imm */
- XMM2I, /* SIMD xmm, imm, imm */
+ XMM3MX, /* SIMD r32/mem -> xmm */
+ XMM3MXS, /* SIMD xmm -> r32/mem */
+ XMMSH, /* SIMD xmm,imm8 */
+ XMMXM3, /* SIMD xmm/mem -> r32 */
+ XMMX3, /* SIMD xmm -> r32 */
+ XMMXMM, /* SIMD xmm/mem -> mm */
+ XMMMX, /* SIMD mm -> xmm */
+ XMMXM, /* SIMD xmm -> mm */
+ XMMX2I, /* SIMD xmm -> xmm, imm, imm */
+ XMM2I, /* SIMD xmm, imm, imm */
XMMFENCE, /* SIMD lfence or mfence */
XMMSFNC, /* SIMD sfence (none or mem) */
+ FSGS, /* FSGSBASE if reg */
XGETBV_XSETBV,
VEX_NONE, /* VEX no operand */
VEX_MO, /* VEX mod_rm -> implicit reg
*/
@@ -224,25 +227,32 @@ enum {
VEX_VRMrX, /* VEX mod_rm, VEX.vvvv -> mod_rm */
VEX_RRX, /* VEX VEX.vvvv, mod_reg -> mod_rm */
VEX_RMRX, /* VEX VEX.vvvv, mod_rm, imm8[7:4] -> mod_reg */
- VEX_MX, /* VEX mod_rm -> mod_reg */
- VEX_MXI, /* VEX mod_rm, imm8 -> mod_reg */
- VEX_XXI, /* VEX mod_rm, imm8 -> VEX.vvvv */
- VEX_MR, /* VEX mod_rm -> mod_reg */
- VEX_RRI, /* VEX mod_reg, mod_rm ->
implicit(eflags/r32) */
- VEX_RX, /* VEX mod_reg -> mod_rm */
- VEX_RR, /* VEX mod_rm -> mod_reg */
- VEX_RRi, /* VEX mod_rm, imm8 -> mod_reg */
- VEX_RM, /* VEX mod_reg -> mod_rm */
+ VEX_MX, /* VEX mod_rm -> mod_reg */
+ VEX_MXI, /* VEX mod_rm, imm8 -> mod_reg */
+ VEX_XXI, /* VEX mod_rm, imm8 -> VEX.vvvv */
+ VEX_MR, /* VEX mod_rm -> mod_reg */
+ VEX_RRI, /* VEX mod_reg, mod_rm ->
implicit(eflags/r32) */
+ VEX_RX, /* VEX mod_reg -> mod_rm */
+ VEX_KRR, /* VEX mod_rm -> mod_reg */
+ VEX_KMR, /* VEX mod_reg -> mod_rm */
+ VEX_KRM, /* VEX mod_rm -> mod_reg */
+ VEX_RR, /* VEX mod_rm -> mod_reg */
+ VEX_RRi, /* VEX mod_rm, imm8 -> mod_reg */
+ VEX_RM, /* VEX mod_reg -> mod_rm */
VEX_RIM, /* VEX mod_reg, imm8 -> mod_rm */
- VEX_RRM, /* VEX VEX.vvvv, mod_reg -> mod_rm */
- VEX_RMX, /* VEX VEX.vvvv, mod_rm -> mod_reg */
+ VEX_RRM, /* VEX VEX.vvvv, mod_reg -> mod_rm */
+ VEX_RMX, /* VEX VEX.vvvv, mod_rm -> mod_reg */
VEX_SbVM, /* VEX SIB, VEX.vvvv -> mod_rm */
VMx, /* vmcall/vmlaunch/vmresume/vmxoff */
VMxo, /* VMx instruction with optional prefix */
SVM, /* AMD SVM instructions */
BLS, /* BLSR, BLSMSK, BLSI */
FMA, /* FMA instructions, all VEX_RMrX */
- ADX /* ADX instructions, support REX.w, mod_rm->mod_reg */
+ ADX, /* ADX instructions, support REX.w, mod_rm->mod_reg */
+ EVEX_RX, /* EVEX mod_reg -> mod_rm */
+ EVEX_MX, /* EVEX mod_rm -> mod_reg */
+ EVEX_RMrX, /* EVEX EVEX.vvvv, mod_rm -> mod_reg */
+ EVEX_RMRX /* EVEX EVEX.vvvv, mod_rm, imm8 -> mod_reg */
};
/*
@@ -280,7 +290,9 @@ enum {
* IND - indirect to another to another table
* "T" - means to Terminate indirections (this is the final opcode)
* "S" - means "operand length suffix required"
- * "Sa" - means AVX2 suffix (d/q) required
+ * "Sa" - means AVX2 suffix (q/d) required
+ * "Sq" - means AVX512 suffix (q/d) required
+ * "Sd" - means AVX512 suffix (d/s) required
* "NS" - means "no suffix" which is the operand length suffix of the opcode
* "Z" - means instruction size arg required
* "u" - means the opcode is invalid in IA32 but valid in amd64
@@ -288,8 +300,13 @@ enum {
* "y" - means the operand size is always 64 bits in 64 bit mode
* "p" - means push/pop stack operation
* "vr" - means VEX instruction that operates on normal registers, not fpu
+ * "vo" - means VEX instruction that operates on opmask registers, not fpu
*/
+#define AVS2 (uint_t)1 /* it_avxsuf: AVX2 q/d suffix handling
*/
+#define AVS5Q (uint_t)2 /* it_avxsuf: AVX512 q/d suffix
handling */
+#define AVS5D (uint_t)3 /* it_avxsuf: AVX512 d/s suffix
handling */
+
#if defined(DIS_TEXT) && defined(DIS_MEM)
#define IND(table) {(instable_t *)table, 0, "", 0, 0, 0,
0, 0, 0}
#define INDx(table) {(instable_t *)table, 0, "", 0, 0, 1,
0, 0, 0}
@@ -301,12 +318,15 @@ enum {
#define TNSZ(name, amode, sz) {TERM, amode, name, 0, sz, 0, 0, 0, 0}
#define TNSZy(name, amode, sz) {TERM, amode, name, 0, sz, 0, 1, 0, 0}
#define TNSZvr(name, amode, sz) {TERM, amode, name, 0, sz, 0, 0, 0, 0,
1}
+#define TSvo(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 0,
0, 0, 1}
#define TS(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 0}
#define TSx(name, amode) {TERM, amode, name, 1, 0, 1, 0, 0, 0}
#define TSy(name, amode) {TERM, amode, name, 1, 0, 0, 1, 0, 0}
#define TSp(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 1}
#define TSZ(name, amode, sz) {TERM, amode, name, 1, sz, 0, 0, 0, 0}
-#define TSaZ(name, amode, sz) {TERM, amode, name, 1, sz, 0, 0, 0, 0,
0, 1}
+#define TSaZ(name, amode, sz) {TERM, amode, name, 1, sz, 0, 0, 0, 0,
0, AVS2}
+#define TSq(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0, 0,
0, AVS5Q}
+#define TSd(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0, 0,
0, AVS5D}
#define TSZx(name, amode, sz) {TERM, amode, name, 1, sz, 1, 0, 0, 0}
#define TSZy(name, amode, sz) {TERM, amode, name, 1, sz, 0, 1, 0, 0}
#define INVALID {TERM, UNKNOWN, "", 0, 0, 0, 0, 0}
@@ -321,12 +341,14 @@ enum {
#define TNSZ(name, amode, sz) {TERM, amode, name, 0, 0, 0, 0, 0}
#define TNSZy(name, amode, sz) {TERM, amode, name, 0, 0, 1, 0, 0}
#define TNSZvr(name, amode, sz) {TERM, amode, name, 0, 0, 0, 0, 0, 1}
+#define TSvo(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 0,
0, 1}
#define TS(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0}
#define TSx(name, amode) {TERM, amode, name, 1, 1, 0, 0, 0}
#define TSy(name, amode) {TERM, amode, name, 1, 0, 1, 0, 0}
#define TSp(name, amode) {TERM, amode, name, 1, 0, 0, 0, 1}
#define TSZ(name, amode, sz) {TERM, amode, name, 1, 0, 0, 0, 0}
-#define TSaZ(name, amode, sz) {TERM, amode, name, 1, 0, 0, 0, 0, 0, 1}
+#define TSaZ(name, amode, sz) {TERM, amode, name, 1, 0, 0, 0, 0, 0,
AVS2}
+#define TSq(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0, 0,
AVS5Q}
#define TSZx(name, amode, sz) {TERM, amode, name, 1, 1, 0, 0, 0}
#define TSZy(name, amode, sz) {TERM, amode, name, 1, 0, 1, 0, 0}
#define INVALID {TERM, UNKNOWN, "", 0, 0, 0, 0, 0}
@@ -341,12 +363,14 @@ enum {
#define TNSZ(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0}
#define TNSZy(name, amode, sz) {TERM, amode, sz, 0, 1, 0, 0}
#define TNSZvr(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0, 1}
+#define TSvo(name, amode) {TERM, amode, 0, 0, 0, 0, 0, 0, 0, 1}
#define TS(name, amode) {TERM, amode, 0, 0, 0, 0, 0}
#define TSx(name, amode) {TERM, amode, 0, 1, 0, 0, 0}
#define TSy(name, amode) {TERM, amode, 0, 0, 1, 0, 0}
#define TSp(name, amode) {TERM, amode, 0, 0, 0, 0, 1}
#define TSZ(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0}
-#define TSaZ(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0, 0, 1}
+#define TSaZ(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0, 0, AVS2}
+#define TSq(name, amode) {TERM, amode, 0, 0, 0, 0, 0, 0, AVS5Q}
#define TSZx(name, amode, sz) {TERM, amode, sz, 1, 0, 0, 0}
#define TSZy(name, amode, sz) {TERM, amode, sz, 0, 1, 0, 0}
#define INVALID {TERM, UNKNOWN, 0, 0, 0, 0, 0}
@@ -361,12 +385,15 @@ enum {
#define TNSZ(name, amode, sz) {TERM, amode, 0, 0, 0, 0}
#define TNSZy(name, amode, sz) {TERM, amode, 0, 1, 0, 0}
#define TNSZvr(name, amode, sz) {TERM, amode, 0, 0, 0, 0, 1}
+#define TSvo(name, amode) {TERM, amode, 0, 0, 0, 0, 0, 0, 1}
#define TS(name, amode) {TERM, amode, 0, 0, 0, 0}
#define TSx(name, amode) {TERM, amode, 1, 0, 0, 0}
#define TSy(name, amode) {TERM, amode, 0, 1, 0, 0}
#define TSp(name, amode) {TERM, amode, 0, 0, 0, 1}
#define TSZ(name, amode, sz) {TERM, amode, 0, 0, 0, 0}
-#define TSaZ(name, amode, sz) {TERM, amode, 0, 0, 0, 0, 0, 1}
+#define TSaZ(name, amode, sz) {TERM, amode, 0, 0, 0, 0, 0, AVS2}
+#define TSq(name, amode) {TERM, amode, 0, 0, 0, 0, 0, AVS5Q}
+#define TSd(name, amode) {TERM, amode, 0, 0, 0, 0, 0, AVS5D}
#define TSZx(name, amode, sz) {TERM, amode, 1, 0, 0, 0}
#define TSZy(name, amode, sz) {TERM, amode, 0, 1, 0, 0}
#define INVALID {TERM, UNKNOWN, 0, 0, 0, 0}
@@ -470,14 +497,41 @@ const char *const dis_MMREG[16] = {
"%mm0", "%mm1", "%mm2", "%mm3", "%mm4", "%mm5", "%mm6", "%mm7"
};
-const char *const dis_XMMREG[16] = {
- "%xmm0", "%xmm1", "%xmm2", "%xmm3", "%xmm4", "%xmm5", "%xmm6", "%xmm7",
- "%xmm8", "%xmm9", "%xmm10", "%xmm11", "%xmm12", "%xmm13", "%xmm14",
"%xmm15"
+const char *const dis_XMMREG[32] = {
+ "%xmm0", "%xmm1", "%xmm2", "%xmm3",
+ "%xmm4", "%xmm5", "%xmm6", "%xmm7",
+ "%xmm8", "%xmm9", "%xmm10", "%xmm11",
+ "%xmm12", "%xmm13", "%xmm14", "%xmm15",
+ "%xmm16", "%xmm17", "%xmm18", "%xmm19",
+ "%xmm20", "%xmm21", "%xmm22", "%xmm23",
+ "%xmm24", "%xmm25", "%xmm26", "%xmm27",
+ "%xmm28", "%xmm29", "%xmm30", "%xmm31",
+};
+
+const char *const dis_YMMREG[32] = {
+ "%ymm0", "%ymm1", "%ymm2", "%ymm3",
+ "%ymm4", "%ymm5", "%ymm6", "%ymm7",
+ "%ymm8", "%ymm9", "%ymm10", "%ymm11",
+ "%ymm12", "%ymm13", "%ymm14", "%ymm15",
+ "%ymm16", "%ymm17", "%ymm18", "%ymm19",
+ "%ymm20", "%ymm21", "%ymm22", "%ymm23",
+ "%ymm24", "%ymm25", "%ymm26", "%ymm27",
+ "%ymm28", "%ymm29", "%ymm30", "%ymm31",
+};
+
+const char *const dis_ZMMREG[32] = {
+ "%zmm0", "%zmm1", "%zmm2", "%zmm3",
+ "%zmm4", "%zmm5", "%zmm6", "%zmm7",
+ "%zmm8", "%zmm9", "%zmm10", "%zmm11",
+ "%zmm12", "%zmm13", "%zmm14", "%zmm15",
+ "%zmm16", "%zmm17", "%zmm18", "%zmm19",
+ "%zmm20", "%zmm21", "%zmm22", "%zmm23",
+ "%zmm24", "%zmm25", "%zmm26", "%zmm27",
+ "%zmm28", "%zmm29", "%zmm30", "%zmm31",
};
-const char *const dis_YMMREG[16] = {
- "%ymm0", "%ymm1", "%ymm2", "%ymm3", "%ymm4", "%ymm5", "%ymm6", "%ymm7",
- "%ymm8", "%ymm9", "%ymm10", "%ymm11", "%ymm12", "%ymm13", "%ymm14",
"%ymm15"
+const char *const dis_KOPMASKREG[8] = {
+ "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
};
const char *const dis_SEGREG[16] = {
@@ -511,12 +565,17 @@ const instable_t dis_opMOVSLD = TNS("movslq",MOVSXZ);
*/
const instable_t dis_opPause = TNS("pause", NORM);
+/*
+ * "decode table" for wbnoinvd instruction
+ */
+const instable_t dis_opWbnoinvd = TNS("wbnoinvd", NORM);
+
/*
* Decode table for 0x0F00 opcodes
*/
const instable_t dis_op0F00[8] = {
-/* [0] */ TNS("sldt",M), TNS("str",M), TNSy("lldt",M),
TNSy("ltr",M),
+/* [0] */ TNS("sldt",M), TNS("str",M), TNSy("lldt",M),
TNSy("ltr",M),
/* [4] */ TNSZ("verr",M,2), TNSZ("verw",M,2), INVALID,
INVALID,
};
@@ -527,7 +586,7 @@ const instable_t dis_op0F00[8] = {
const instable_t dis_op0F01[8] = {
/* [0] */ TNSZ("sgdt",VMx,6), TNSZ("sidt",MONITOR_MWAIT,6),
TNSZ("lgdt",XGETBV_XSETBV,6), TNSZ("lidt",SVM,6),
-/* [4] */ TNSZ("smsw",M,2), INVALID,
TNSZ("lmsw",M,2), TNS("invlpg",SWAPGS_RDTSCP),
+/* [4] */ TNSZ("smsw",M,2), INVALID,
TNSZ("lmsw",M,2), TNS("invlpg",SWAPGS_RDTSCP),
};
/*
@@ -540,13 +599,21 @@ const instable_t dis_op0F18[8] = {
};
/*
- * Decode table for 0x0FAE opcodes -- SIMD state save/restore
+ * Decode table for 0x0FAE opcodes -- SIMD state save/restore
*/
const instable_t dis_op0FAE[8] = {
-/* [0] */ TNSZ("fxsave",M,512), TNSZ("fxrstor",M,512),
TNS("ldmxcsr",M), TNS("stmxcsr",M),
+/* [0] */
TNSZ("fxsave",FSGS,512),TNSZ("fxrstor",FSGS,512),TNS("ldmxcsr",FSGS),
TNS("stmxcsr",FSGS),
/* [4] */ TNSZ("xsave",M,512), TNS("lfence",XMMFENCE),
TNS("mfence",XMMFENCE), TNS("sfence",XMMSFNC),
};
+/*
+ * Decode table for 0xF30FAE opcodes -- FSGSBASE
+ */
+const instable_t dis_opF30FAE[8] = {
+/* [0] */ TNSx("rdfsbase",FSGS), TNSx("rdgsbase",FSGS),
TNSx("wrfsbase",FSGS), TNSx("wrgsbase",FSGS),
+/* [4] */ INVALID, INVALID, INVALID,
INVALID,
+};
+
/*
* Decode table for 0x0FBA opcodes
*/
@@ -558,17 +625,17 @@ const instable_t dis_op0FBA[8] = {
};
/*
- * Decode table for 0x0FC7 opcode (group 9)
+ * Decode table for 0x0FC7 opcode (group 9)
*/
const instable_t dis_op0FC7[8] = {
-/* [0] */ INVALID, TNS("cmpxchg8b",M), INVALID,
INVALID,
-/* [4] */ INVALID, INVALID,
TNS("vmptrld",MG9), TNS("vmptrst",MG9),
+/* [0] */ INVALID, TNS("cmpxchg8b",M), INVALID,
TNS("xrstors",MG9),
+/* [4] */ TNS("xsavec",MG9), TNS("xsaves",MG9),
TNS("vmptrld",MG9), TNS("vmptrst",MG9),
};
/*
- * Decode table for 0x0FC7 opcode (group 9) mode 3
+ * Decode table for 0x0FC7 opcode (group 9) mode 3
*/
const instable_t dis_op0FC7m3[8] = {
@@ -578,7 +645,7 @@ const instable_t dis_op0FC7m3[8] = {
};
/*
- * Decode table for 0x0FC7 opcode with 0x66 prefix
+ * Decode table for 0x0FC7 opcode with 0x66 prefix
*/
const instable_t dis_op660FC7[8] = {
@@ -588,7 +655,7 @@ const instable_t dis_op660FC7[8] = {
};
/*
- * Decode table for 0x0FC7 opcode with 0xF3 prefix
+ * Decode table for 0x0FC7 opcode with 0xF3 prefix
*/
const instable_t dis_opF30FC7[8] = {
@@ -621,7 +688,7 @@ const instable_t dis_op0F7123[4][8] = {
/* .4 */ TNS("psrad",MMOSH), INVALID,
TNS("pslld",MMOSH), INVALID,
}, {
/* [73].0 */ INVALID, INVALID,
TNS("psrlq",MMOSH), TNS("INVALID",MMOSH),
-/* .4 */ INVALID, INVALID,
TNS("psllq",MMOSH), TNS("INVALID",MMOSH),
+/* .4 */ INVALID, INVALID,
TNS("psllq",MMOSH), TNS("INVALID",MMOSH),
} };
/*
@@ -757,9 +824,9 @@ const instable_t dis_opAVX660F[256] = {
/* [38] */ INVALID, INVALID, INVALID,
INVALID,
/* [3C] */ INVALID, INVALID, INVALID,
INVALID,
-/* [40] */ INVALID, INVALID, INVALID,
INVALID,
-/* [44] */ INVALID, INVALID, INVALID,
INVALID,
-/* [48] */ INVALID, INVALID, INVALID,
INVALID,
+/* [40] */ INVALID, TSvo("kand",VEX_RMX),
TSvo("kandn",VEX_RMX), INVALID,
+/* [44] */ TSvo("knot",VEX_MX), TSvo("kor",VEX_RMX),
TSvo("kxnor",VEX_RMX), TSvo("kxor",VEX_RMX),
+/* [48] */ INVALID, INVALID,
TSvo("kadd",VEX_RMX), TSvo("kunpck",VEX_RMX),
/* [4C] */ INVALID, INVALID, INVALID,
INVALID,
/* [50] */ TNS("vmovmskpd",VEX_MR), TNSZ("vsqrtpd",VEX_MX,16),
INVALID, INVALID,
@@ -782,9 +849,9 @@ const instable_t dis_opAVX660F[256] = {
/* [88] */ INVALID, INVALID, INVALID,
INVALID,
/* [8C] */ INVALID, INVALID, INVALID,
INVALID,
-/* [90] */ INVALID, INVALID, INVALID,
INVALID,
+/* [90] */ TSvo("kmov",VEX_KRM), TSvo("kmov",VEX_KMR),
TSvo("kmov",VEX_KRR), TSvo("kmov",VEX_MR),
/* [94] */ INVALID, INVALID, INVALID,
INVALID,
-/* [98] */ INVALID, INVALID, INVALID,
INVALID,
+/* [98] */ TSvo("kortest",VEX_MX), TSvo("ktest",VEX_MX), INVALID,
INVALID,
/* [9C] */ INVALID, INVALID, INVALID,
INVALID,
/* [A0] */ INVALID, INVALID, INVALID,
INVALID,
@@ -812,30 +879,524 @@ const instable_t dis_opAVX660F[256] = {
/* [E8] */ TNSZ("vpsubsb",VEX_RMrX,16), TNSZ("vpsubsw",VEX_RMrX,16),
TNSZ("vpminsw",VEX_RMrX,16), TNSZ("vpor",VEX_RMrX,16),
/* [EC] */ TNSZ("vpaddsb",VEX_RMrX,16), TNSZ("vpaddsw",VEX_RMrX,16),
TNSZ("vpmaxsw",VEX_RMrX,16), TNSZ("vpxor",VEX_RMrX,16),
-/* [F0] */ INVALID, TNSZ("vpsllw",VEX_RMrX,16),
TNSZ("vpslld",VEX_RMrX,16), TNSZ("vpsllq",VEX_RMrX,16),
-/* [F4] */ TNSZ("vpmuludq",VEX_RMrX,16), TNSZ("vpmaddwd",VEX_RMrX,16),
TNSZ("vpsadbw",VEX_RMrX,16), TNS("vmaskmovdqu",VEX_MX),
-/* [F8] */ TNSZ("vpsubb",VEX_RMrX,16), TNSZ("vpsubw",VEX_RMrX,16),
TNSZ("vpsubd",VEX_RMrX,16), TNSZ("vpsubq",VEX_RMrX,16),
-/* [FC] */ TNSZ("vpaddb",VEX_RMrX,16), TNSZ("vpaddw",VEX_RMrX,16),
TNSZ("vpaddd",VEX_RMrX,16), INVALID,
+/* [F0] */ INVALID, TNSZ("vpsllw",VEX_RMrX,16),
TNSZ("vpslld",VEX_RMrX,16), TNSZ("vpsllq",VEX_RMrX,16),
+/* [F4] */ TNSZ("vpmuludq",VEX_RMrX,16), TNSZ("vpmaddwd",VEX_RMrX,16),
TNSZ("vpsadbw",VEX_RMrX,16), TNS("vmaskmovdqu",VEX_MX),
+/* [F8] */ TNSZ("vpsubb",VEX_RMrX,16), TNSZ("vpsubw",VEX_RMrX,16),
TNSZ("vpsubd",VEX_RMrX,16), TNSZ("vpsubq",VEX_RMrX,16),
+/* [FC] */ TNSZ("vpaddb",VEX_RMrX,16), TNSZ("vpaddw",VEX_RMrX,16),
TNSZ("vpaddd",VEX_RMrX,16), INVALID,
+};
+
+/*
+ * Decode table for SIMD instructions with the repnz (0xf2) prefix.
+ */
+const instable_t dis_opSIMDrepnz[256] = {
+/* [00] */ INVALID, INVALID, INVALID,
INVALID,
+/* [04] */ INVALID, INVALID, INVALID,
INVALID,
+/* [08] */ INVALID, INVALID, INVALID,
INVALID,
+/* [0C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [10] */ TNSZ("movsd",XMM,8), TNSZ("movsd",XMMS,8),
TNSZ("movddup",XMM,8), INVALID,
+/* [14] */ INVALID, INVALID, INVALID,
INVALID,
+/* [18] */ INVALID, INVALID, INVALID,
INVALID,
+/* [1C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [20] */ INVALID, INVALID, INVALID,
INVALID,
+/* [24] */ INVALID, INVALID, INVALID,
INVALID,
+/* [28] */ INVALID, INVALID,
TNSZ("cvtsi2sd",XMM3MX,4),TNSZ("movntsd",XMMMS,8),
+/* [2C] */ TNSZ("cvttsd2si",XMMXM3,8),TNSZ("cvtsd2si",XMMXM3,8),INVALID,
INVALID,
+
+/* [30] */ INVALID, INVALID, INVALID,
INVALID,
+/* [34] */ INVALID, INVALID, INVALID,
INVALID,
+/* [38] */ INVALID, INVALID, INVALID,
INVALID,
+/* [3C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [40] */ INVALID, INVALID, INVALID,
INVALID,
+/* [44] */ INVALID, INVALID, INVALID,
INVALID,
+/* [48] */ INVALID, INVALID, INVALID,
INVALID,
+/* [4C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [50] */ INVALID, TNSZ("sqrtsd",XMM,8), INVALID,
INVALID,
+/* [54] */ INVALID, INVALID, INVALID,
INVALID,
+/* [58] */ TNSZ("addsd",XMM,8), TNSZ("mulsd",XMM,8),
TNSZ("cvtsd2ss",XMM,8), INVALID,
+/* [5C] */ TNSZ("subsd",XMM,8), TNSZ("minsd",XMM,8),
TNSZ("divsd",XMM,8), TNSZ("maxsd",XMM,8),
+
+/* [60] */ INVALID, INVALID, INVALID,
INVALID,
+/* [64] */ INVALID, INVALID, INVALID,
INVALID,
+/* [68] */ INVALID, INVALID, INVALID,
INVALID,
+/* [6C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [70] */ TNSZ("pshuflw",XMMP,16),INVALID, INVALID,
INVALID,
+/* [74] */ INVALID, INVALID, INVALID,
INVALID,
+/* [78] */ TNSZ("insertq",XMMX2I,16),TNSZ("insertq",XMM,8),INVALID,
INVALID,
+/* [7C] */ TNSZ("haddps",XMM,16), TNSZ("hsubps",XMM,16), INVALID,
INVALID,
+
+/* [80] */ INVALID, INVALID, INVALID,
INVALID,
+/* [84] */ INVALID, INVALID, INVALID,
INVALID,
+/* [88] */ INVALID, INVALID, INVALID,
INVALID,
+/* [0C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [90] */ INVALID, INVALID, INVALID,
INVALID,
+/* [94] */ INVALID, INVALID, INVALID,
INVALID,
+/* [98] */ INVALID, INVALID, INVALID,
INVALID,
+/* [9C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [A0] */ INVALID, INVALID, INVALID,
INVALID,
+/* [A4] */ INVALID, INVALID, INVALID,
INVALID,
+/* [A8] */ INVALID, INVALID, INVALID,
INVALID,
+/* [AC] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [B0] */ INVALID, INVALID, INVALID,
INVALID,
+/* [B4] */ INVALID, INVALID, INVALID,
INVALID,
+/* [B8] */ INVALID, INVALID, INVALID,
INVALID,
+/* [BC] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [C0] */ INVALID, INVALID,
TNSZ("cmpsd",XMMP,8), INVALID,
+/* [C4] */ INVALID, INVALID, INVALID,
INVALID,
+/* [C8] */ INVALID, INVALID, INVALID,
INVALID,
+/* [CC] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [D0] */ TNSZ("addsubps",XMM,16),INVALID, INVALID,
INVALID,
+/* [D4] */ INVALID, INVALID,
TNS("movdq2q",XMMXM), INVALID,
+/* [D8] */ INVALID, INVALID, INVALID,
INVALID,
+/* [DC] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [E0] */ INVALID, INVALID, INVALID,
INVALID,
+/* [E4] */ INVALID, INVALID,
TNSZ("cvtpd2dq",XMM,16),INVALID,
+/* [E8] */ INVALID, INVALID, INVALID,
INVALID,
+/* [EC] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [F0] */ TNS("lddqu",XMMM), INVALID, INVALID,
INVALID,
+/* [F4] */ INVALID, INVALID, INVALID,
INVALID,
+/* [F8] */ INVALID, INVALID, INVALID,
INVALID,
+/* [FC] */ INVALID, INVALID, INVALID,
INVALID,
+};
+
+const instable_t dis_opAVXF20F[256] = {
+/* [00] */ INVALID, INVALID, INVALID,
INVALID,
+/* [04] */ INVALID, INVALID, INVALID,
INVALID,
+/* [08] */ INVALID, INVALID, INVALID,
INVALID,
+/* [0C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [10] */ TNSZ("vmovsd",VEX_RMrX,8), TNSZ("vmovsd",VEX_RRX,8),
TNSZ("vmovddup",VEX_MX,8), INVALID,
+/* [14] */ INVALID, INVALID, INVALID,
INVALID,
+/* [18] */ INVALID, INVALID, INVALID,
INVALID,
+/* [1C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [20] */ INVALID, INVALID, INVALID,
INVALID,
+/* [24] */ INVALID, INVALID, INVALID,
INVALID,
+/* [28] */ INVALID, INVALID,
TNSZ("vcvtsi2sd",VEX_RMrX,4),INVALID,
+/* [2C] */ TNSZ("vcvttsd2si",VEX_MR,8),TNSZ("vcvtsd2si",VEX_MR,8),INVALID,
INVALID,
+
+/* [30] */ INVALID, INVALID, INVALID,
INVALID,
+/* [34] */ INVALID, INVALID, INVALID,
INVALID,
+/* [38] */ INVALID, INVALID, INVALID,
INVALID,
+/* [3C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [40] */ INVALID, INVALID, INVALID,
INVALID,
+/* [44] */ INVALID, INVALID, INVALID,
INVALID,
+/* [48] */ INVALID, INVALID, INVALID,
INVALID,
+/* [4C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [50] */ INVALID, TNSZ("vsqrtsd",VEX_RMrX,8),
INVALID, INVALID,
+/* [54] */ INVALID, INVALID, INVALID,
INVALID,
+/* [58] */ TNSZ("vaddsd",VEX_RMrX,8), TNSZ("vmulsd",VEX_RMrX,8),
TNSZ("vcvtsd2ss",VEX_RMrX,8), INVALID,
+/* [5C] */ TNSZ("vsubsd",VEX_RMrX,8), TNSZ("vminsd",VEX_RMrX,8),
TNSZ("vdivsd",VEX_RMrX,8), TNSZ("vmaxsd",VEX_RMrX,8),
+
+/* [60] */ INVALID, INVALID, INVALID,
INVALID,
+/* [64] */ INVALID, INVALID, INVALID,
INVALID,
+/* [68] */ INVALID, INVALID, INVALID,
INVALID,
+/* [6C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [70] */ TNSZ("vpshuflw",VEX_MXI,16),INVALID, INVALID,
INVALID,
+/* [74] */ INVALID, INVALID, INVALID,
INVALID,
+/* [78] */ INVALID, INVALID, INVALID,
INVALID,
+/* [7C] */ TNSZ("vhaddps",VEX_RMrX,8), TNSZ("vhsubps",VEX_RMrX,8),
INVALID, INVALID,
+
+/* [80] */ INVALID, INVALID, INVALID,
INVALID,
+/* [84] */ INVALID, INVALID, INVALID,
INVALID,
+/* [88] */ INVALID, INVALID, INVALID,
INVALID,
+/* [0C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [90] */ INVALID, INVALID,
TSvo("kmov",VEX_KRR), TSvo("kmov",VEX_MR),
+/* [94] */ INVALID, INVALID, INVALID,
INVALID,
+/* [98] */ INVALID, INVALID, INVALID,
INVALID,
+/* [9C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [A0] */ INVALID, INVALID, INVALID,
INVALID,
+/* [A4] */ INVALID, INVALID, INVALID,
INVALID,
+/* [A8] */ INVALID, INVALID, INVALID,
INVALID,
+/* [AC] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [B0] */ INVALID, INVALID, INVALID,
INVALID,
+/* [B4] */ INVALID, INVALID, INVALID,
INVALID,
+/* [B8] */ INVALID, INVALID, INVALID,
INVALID,
+/* [BC] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [C0] */ INVALID, INVALID,
TNSZ("vcmpsd",VEX_RMRX,8), INVALID,
+/* [C4] */ INVALID, INVALID, INVALID,
INVALID,
+/* [C8] */ INVALID, INVALID, INVALID,
INVALID,
+/* [CC] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [D0] */ TNSZ("vaddsubps",VEX_RMrX,8), INVALID,
INVALID, INVALID,
+/* [D4] */ INVALID, INVALID, INVALID,
INVALID,
+/* [D8] */ INVALID, INVALID, INVALID,
INVALID,
+/* [DC] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [E0] */ INVALID, INVALID, INVALID,
INVALID,
+/* [E4] */ INVALID, INVALID,
TNSZ("vcvtpd2dq",VEX_MX,16),INVALID,
+/* [E8] */ INVALID, INVALID, INVALID,
INVALID,
+/* [EC] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [F0] */ TNSZ("vlddqu",VEX_MX,16), INVALID,
INVALID, INVALID,
+/* [F4] */ INVALID, INVALID, INVALID,
INVALID,
+/* [F8] */ INVALID, INVALID, INVALID,
INVALID,
+/* [FC] */ INVALID, INVALID, INVALID,
INVALID,
+};
+
+const instable_t dis_opAVXF20F3A[256] = {
+/* [00] */ INVALID, INVALID, INVALID,
INVALID,
+/* [04] */ INVALID, INVALID, INVALID,
INVALID,
+/* [08] */ INVALID, INVALID, INVALID,
INVALID,
+/* [0C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [10] */ INVALID, INVALID, INVALID,
INVALID,
+/* [14] */ INVALID, INVALID, INVALID,
INVALID,
+/* [18] */ INVALID, INVALID, INVALID,
INVALID,
+/* [1C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [20] */ INVALID, INVALID, INVALID,
INVALID,
+/* [24] */ INVALID, INVALID, INVALID,
INVALID,
+/* [28] */ INVALID, INVALID, INVALID,
INVALID,
+/* [2C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [30] */ INVALID, INVALID, INVALID,
INVALID,
+/* [34] */ INVALID, INVALID, INVALID,
INVALID,
+/* [38] */ INVALID, INVALID, INVALID,
INVALID,
+/* [3C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [40] */ INVALID, INVALID, INVALID,
INVALID,
+/* [44] */ INVALID, INVALID, INVALID,
INVALID,
+/* [48] */ INVALID, INVALID, INVALID,
INVALID,
+/* [4C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [50] */ INVALID, INVALID, INVALID,
INVALID,
+/* [54] */ INVALID, INVALID, INVALID,
INVALID,
+/* [58] */ INVALID, INVALID, INVALID,
INVALID,
+/* [5C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [60] */ INVALID, INVALID, INVALID,
INVALID,
+/* [64] */ INVALID, INVALID, INVALID,
INVALID,
+/* [68] */ INVALID, INVALID, INVALID,
INVALID,
+/* [6C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [70] */ INVALID, INVALID, INVALID,
INVALID,
+/* [74] */ INVALID, INVALID, INVALID,
INVALID,
+/* [78] */ INVALID, INVALID, INVALID,
INVALID,
+/* [7C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [80] */ INVALID, INVALID, INVALID,
INVALID,
+/* [84] */ INVALID, INVALID, INVALID,
INVALID,
+/* [88] */ INVALID, INVALID, INVALID,
INVALID,
+/* [0C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [90] */ INVALID, INVALID, INVALID,
INVALID,
+/* [94] */ INVALID, INVALID, INVALID,
INVALID,
+/* [98] */ INVALID, INVALID, INVALID,
INVALID,
+/* [9C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [A0] */ INVALID, INVALID, INVALID,
INVALID,
+/* [A4] */ INVALID, INVALID, INVALID,
INVALID,
+/* [A8] */ INVALID, INVALID, INVALID,
INVALID,
+/* [AC] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [B0] */ INVALID, INVALID, INVALID,
INVALID,
+/* [B4] */ INVALID, INVALID, INVALID,
INVALID,
+/* [B8] */ INVALID, INVALID, INVALID,
INVALID,
+/* [BC] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [C0] */ INVALID, INVALID, INVALID,
INVALID,
+/* [C4] */ INVALID, INVALID, INVALID,
INVALID,
+/* [C8] */ INVALID, INVALID, INVALID,
INVALID,
+/* [CC] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [D0] */ INVALID, INVALID, INVALID,
INVALID,
+/* [D4] */ INVALID, INVALID, INVALID,
INVALID,
+/* [D8] */ INVALID, INVALID, INVALID,
INVALID,
+/* [DC] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [E0] */ INVALID, INVALID, INVALID,
INVALID,
+/* [E4] */ INVALID, INVALID, INVALID,
INVALID,
+/* [E8] */ INVALID, INVALID, INVALID,
INVALID,
+/* [EC] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [F0] */ TNSZvr("rorx",VEX_MXI,6),INVALID, INVALID,
INVALID,
+/* [F4] */ INVALID, INVALID, INVALID,
INVALID,
+/* [F8] */ INVALID, INVALID, INVALID,
INVALID,
+/* [FC] */ INVALID, INVALID, INVALID,
INVALID,
+};
+
+const instable_t dis_opAVXF20F38[256] = {
+/* [00] */ INVALID, INVALID, INVALID,
INVALID,
+/* [04] */ INVALID, INVALID, INVALID,
INVALID,
+/* [08] */ INVALID, INVALID, INVALID,
INVALID,
+/* [0C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [10] */ INVALID, INVALID, INVALID,
INVALID,
+/* [14] */ INVALID, INVALID, INVALID,
INVALID,
+/* [18] */ INVALID, INVALID, INVALID,
INVALID,
+/* [1C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [20] */ INVALID, INVALID, INVALID,
INVALID,
+/* [24] */ INVALID, INVALID, INVALID,
INVALID,
+/* [28] */ INVALID, INVALID, INVALID,
INVALID,
+/* [2C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [30] */ INVALID, INVALID, INVALID,
INVALID,
+/* [34] */ INVALID, INVALID, INVALID,
INVALID,
+/* [38] */ INVALID, INVALID, INVALID,
INVALID,
+/* [3C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [40] */ INVALID, INVALID, INVALID,
INVALID,
+/* [44] */ INVALID, INVALID, INVALID,
INVALID,
+/* [48] */ INVALID, INVALID, INVALID,
INVALID,
+/* [4C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [50] */ INVALID, INVALID, INVALID,
INVALID,
+/* [54] */ INVALID, INVALID, INVALID,
INVALID,
+/* [58] */ INVALID, INVALID, INVALID,
INVALID,
+/* [5C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [60] */ INVALID, INVALID, INVALID,
INVALID,
+/* [64] */ INVALID, INVALID, INVALID,
INVALID,
+/* [68] */ INVALID, INVALID, INVALID,
INVALID,
+/* [6C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [70] */ INVALID, INVALID, INVALID,
INVALID,
+/* [74] */ INVALID, INVALID, INVALID,
INVALID,
+/* [78] */ INVALID, INVALID, INVALID,
INVALID,
+/* [7C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [80] */ INVALID, INVALID, INVALID,
INVALID,
+/* [84] */ INVALID, INVALID, INVALID,
INVALID,
+/* [88] */ INVALID, INVALID, INVALID,
INVALID,
+/* [0C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [90] */ INVALID, INVALID, INVALID,
INVALID,
+/* [94] */ INVALID, INVALID, INVALID,
INVALID,
+/* [98] */ INVALID, INVALID, INVALID,
INVALID,
+/* [9C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [A0] */ INVALID, INVALID, INVALID,
INVALID,
+/* [A4] */ INVALID, INVALID, INVALID,
INVALID,
+/* [A8] */ INVALID, INVALID, INVALID,
INVALID,
+/* [AC] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [B0] */ INVALID, INVALID, INVALID,
INVALID,
+/* [B4] */ INVALID, INVALID, INVALID,
INVALID,
+/* [B8] */ INVALID, INVALID, INVALID,
INVALID,
+/* [BC] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [C0] */ INVALID, INVALID, INVALID,
INVALID,
+/* [C4] */ INVALID, INVALID, INVALID,
INVALID,
+/* [C8] */ INVALID, INVALID, INVALID,
INVALID,
+/* [CC] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [D0] */ INVALID, INVALID, INVALID,
INVALID,
+/* [D4] */ INVALID, INVALID, INVALID,
INVALID,
+/* [D8] */ INVALID, INVALID, INVALID,
INVALID,
+/* [DC] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [E0] */ INVALID, INVALID, INVALID,
INVALID,
+/* [E4] */ INVALID, INVALID, INVALID,
INVALID,
+/* [E8] */ INVALID, INVALID, INVALID,
INVALID,
+/* [EC] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [F0] */ INVALID, INVALID, INVALID,
INVALID,
+/* [F4] */ INVALID,
TNSZvr("pdep",VEX_RMrX,5),TNSZvr("mulx",VEX_RMrX,5),TNSZvr("shrx",VEX_VRMrX,5),
+/* [F8] */ INVALID, INVALID, INVALID,
INVALID,
+/* [FC] */ INVALID, INVALID, INVALID,
INVALID,
+};
+
+const instable_t dis_opAVXF30F38[256] = {
+/* [00] */ INVALID, INVALID, INVALID,
INVALID,
+/* [04] */ INVALID, INVALID, INVALID,
INVALID,
+/* [08] */ INVALID, INVALID, INVALID,
INVALID,
+/* [0C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [10] */ INVALID, INVALID, INVALID,
INVALID,
+/* [14] */ INVALID, INVALID, INVALID,
INVALID,
+/* [18] */ INVALID, INVALID, INVALID,
INVALID,
+/* [1C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [20] */ INVALID, INVALID, INVALID,
INVALID,
+/* [24] */ INVALID, INVALID, INVALID,
INVALID,
+/* [28] */ INVALID, INVALID, INVALID,
INVALID,
+/* [2C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [30] */ INVALID, INVALID, INVALID,
INVALID,
+/* [34] */ INVALID, INVALID, INVALID,
INVALID,
+/* [38] */ INVALID, INVALID, INVALID,
INVALID,
+/* [3C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [40] */ INVALID, INVALID, INVALID,
INVALID,
+/* [44] */ INVALID, INVALID, INVALID,
INVALID,
+/* [48] */ INVALID, INVALID, INVALID,
INVALID,
+/* [4C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [50] */ INVALID, INVALID, INVALID,
INVALID,
+/* [54] */ INVALID, INVALID, INVALID,
INVALID,
+/* [58] */ INVALID, INVALID, INVALID,
INVALID,
+/* [5C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [60] */ INVALID, INVALID, INVALID,
INVALID,
+/* [64] */ INVALID, INVALID, INVALID,
INVALID,
+/* [68] */ INVALID, INVALID, INVALID,
INVALID,
+/* [6C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [70] */ INVALID, INVALID, INVALID,
INVALID,
+/* [74] */ INVALID, INVALID, INVALID,
INVALID,
+/* [78] */ INVALID, INVALID, INVALID,
INVALID,
+/* [7C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [80] */ INVALID, INVALID, INVALID,
INVALID,
+/* [84] */ INVALID, INVALID, INVALID,
INVALID,
+/* [88] */ INVALID, INVALID, INVALID,
INVALID,
+/* [0C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [90] */ INVALID, INVALID, INVALID,
INVALID,
+/* [94] */ INVALID, INVALID, INVALID,
INVALID,
+/* [98] */ INVALID, INVALID, INVALID,
INVALID,
+/* [9C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [A0] */ INVALID, INVALID, INVALID,
INVALID,
+/* [A4] */ INVALID, INVALID, INVALID,
INVALID,
+/* [A8] */ INVALID, INVALID, INVALID,
INVALID,
+/* [AC] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [B0] */ INVALID, INVALID, INVALID,
INVALID,
+/* [B4] */ INVALID, INVALID, INVALID,
INVALID,
+/* [B8] */ INVALID, INVALID, INVALID,
INVALID,
+/* [BC] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [C0] */ INVALID, INVALID, INVALID,
INVALID,
+/* [C4] */ INVALID, INVALID, INVALID,
INVALID,
+/* [C8] */ INVALID, INVALID, INVALID,
INVALID,
+/* [CC] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [D0] */ INVALID, INVALID, INVALID,
INVALID,
+/* [D4] */ INVALID, INVALID, INVALID,
INVALID,
+/* [D8] */ INVALID, INVALID, INVALID,
INVALID,
+/* [DC] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [E0] */ INVALID, INVALID, INVALID,
INVALID,
+/* [E4] */ INVALID, INVALID, INVALID,
INVALID,
+/* [E8] */ INVALID, INVALID, INVALID,
INVALID,
+/* [EC] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [F0] */ INVALID, INVALID, INVALID,
INVALID,
+/* [F4] */ INVALID, TNSZvr("pext",VEX_RMrX,5),INVALID,
TNSZvr("sarx",VEX_VRMrX,5),
+/* [F8] */ INVALID, INVALID, INVALID,
INVALID,
+/* [FC] */ INVALID, INVALID, INVALID,
INVALID,
+};
+/*
+ * Decode table for SIMD instructions with the repz (0xf3) prefix.
+ */
+const instable_t dis_opSIMDrepz[256] = {
+/* [00] */ INVALID, INVALID, INVALID,
INVALID,
+/* [04] */ INVALID, INVALID, INVALID,
INVALID,
+/* [08] */ INVALID, INVALID, INVALID,
INVALID,
+/* [0C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [10] */ TNSZ("movss",XMM,4), TNSZ("movss",XMMS,4),
TNSZ("movsldup",XMM,16),INVALID,
+/* [14] */ INVALID, INVALID,
TNSZ("movshdup",XMM,16),INVALID,
+/* [18] */ INVALID, INVALID, INVALID,
INVALID,
+/* [1C] */ INVALID, INVALID, INVALID,
INVALID,
+
+/* [20] */ INVALID, INVALID, INVALID,
INVALID,
+/* [24] */ INVALID, INVALID, INVALID,
INVALID,
+/* [28] */ INVALID, INVALID,
TNSZ("cvtsi2ss",XMM3MX,4),TNSZ("movntss",XMMMS,4),
+/* [2C] */ TNSZ("cvttss2si",XMMXM3,4),TNSZ("cvtss2si",XMMXM3,4),INVALID,
INVALID,
+
*** 1650 LINES SKIPPED ***
