The branch releng/13.2 has been updated by erj:
URL:
https://cgit.FreeBSD.org/src/commit/?id=576955dd669e381c59c06168fda6b73f930b191f
commit 576955dd669e381c59c06168fda6b73f930b191f
Author: Piotr Kubaj <pku...@freebsd.org>
AuthorDate: 2023-02-14 01:29:44 +0000
Commit: Eric Joyner <e...@freebsd.org>
CommitDate: 2023-02-21 23:55:41 +0000
ice(4): Update to 1.37.7-k
Notable changes include:
- DSCP QoS Support (leveraging support added in
rG9c950139051298831ce19d01ea5fb33ec6ea7f89)
- Improved PFC handling and TC queue assignments (now all remaining
queues are assigned to TC 0 when more than one TC is enabled and the
number of available queues does not evenly divide between them)
- Support for dumping the internal FW state for additional debugging by
Intel support
- Support for allowing "No FEC" to be a valid state for the LESM to
negotiate when using non-standard compliant modules
Also includes various bug fixes and smaller enhancements, too.
Signed-off-by: Eric Joyner <e...@freebsd.org>
Reviewed by: erj@
Tested by: Jeff Pieper <jeffrey.pie...@intel.com>
Approved by: re (cperciva)
Relnotes: yes
Sponsored by: Intel Corporation
Differential Revision: https://reviews.freebsd.org/D38109
(cherry picked from commit 8923de59054358980102ea5acda6c6dd58273957)
(cherry picked from commit ebc914f942f6655ff4c27f8717630f81c74624cb)
---
sys/conf/files.amd64 | 2 +
sys/conf/files.arm64 | 2 +
sys/conf/files.powerpc | 44 +-
sys/dev/ice/ice_adminq_cmd.h | 142 +-
sys/dev/ice/ice_alloc.h | 2 +-
sys/dev/ice/ice_bitops.h | 14 +-
sys/dev/ice/ice_common.c | 453 ++++--
sys/dev/ice/ice_common.h | 7 +-
sys/dev/ice/ice_common_sysctls.h | 17 +-
sys/dev/ice/ice_common_txrx.h | 2 +-
sys/dev/ice/ice_controlq.c | 31 +-
sys/dev/ice/ice_controlq.h | 2 +-
sys/dev/ice/ice_dcb.c | 52 +-
sys/dev/ice/ice_dcb.h | 4 +-
sys/dev/ice/ice_ddp_common.c | 2532 +++++++++++++++++++++++++++++++++
sys/dev/ice/ice_ddp_common.h | 478 +++++++
sys/dev/ice/ice_defs.h | 71 +
sys/dev/ice/ice_devids.h | 9 +-
sys/dev/ice/ice_drv_info.h | 15 +-
sys/dev/ice/ice_features.h | 4 +-
sys/dev/ice/ice_flex_pipe.c | 2474 +++++---------------------------
sys/dev/ice/ice_flex_pipe.h | 44 +-
sys/dev/ice/ice_flex_type.h | 291 +---
sys/dev/ice/ice_flow.c | 18 +-
sys/dev/ice/ice_flow.h | 2 +-
sys/dev/ice/ice_fw_logging.c | 2 +-
sys/dev/ice/ice_fwlog.c | 2 +-
sys/dev/ice/ice_fwlog.h | 4 +-
sys/dev/ice/ice_hw_autogen.h | 2 +-
sys/dev/ice/ice_iflib.h | 12 +-
sys/dev/ice/ice_iflib_recovery_txrx.c | 2 +-
sys/dev/ice/ice_iflib_sysctls.h | 2 +-
sys/dev/ice/ice_iflib_txrx.c | 27 +-
sys/dev/ice/ice_lan_tx_rx.h | 10 +-
sys/dev/ice/ice_lib.c | 1489 ++++++++++++++++---
sys/dev/ice/ice_lib.h | 43 +-
sys/dev/ice/ice_nvm.c | 37 +-
sys/dev/ice/ice_nvm.h | 5 +-
sys/dev/ice/ice_opts.h | 2 +-
sys/dev/ice/ice_osdep.c | 2 +-
sys/dev/ice/ice_osdep.h | 2 +-
sys/dev/ice/ice_protocol_type.h | 25 +-
sys/dev/ice/ice_rdma.c | 15 +-
sys/dev/ice/ice_rdma.h | 2 +-
sys/dev/ice/ice_resmgr.c | 2 +-
sys/dev/ice/ice_resmgr.h | 2 +-
sys/dev/ice/ice_rss.h | 2 +-
sys/dev/ice/ice_sbq_cmd.h | 2 +-
sys/dev/ice/ice_sched.c | 94 +-
sys/dev/ice/ice_sched.h | 13 +-
sys/dev/ice/ice_status.h | 2 +-
sys/dev/ice/ice_strings.c | 8 +-
sys/dev/ice/ice_switch.c | 257 ++--
sys/dev/ice/ice_switch.h | 54 +-
sys/dev/ice/ice_type.h | 112 +-
sys/dev/ice/ice_vlan_mode.c | 3 +-
sys/dev/ice/ice_vlan_mode.h | 2 +-
sys/dev/ice/if_ice_iflib.c | 66 +-
sys/dev/ice/irdma_di_if.m | 2 +-
sys/dev/ice/irdma_if.m | 2 +-
sys/dev/ice/virtchnl.h | 186 ++-
sys/dev/ice/virtchnl_inline_ipsec.h | 11 +-
sys/dev/ice/virtchnl_lan_desc.h | 550 -------
sys/modules/ice/Makefile | 2 +-
64 files changed, 5963 insertions(+), 3806 deletions(-)
diff --git a/sys/conf/files.amd64 b/sys/conf/files.amd64
index 464c7af84bfa..b973827d6632 100644
--- a/sys/conf/files.amd64
+++ b/sys/conf/files.amd64
@@ -205,6 +205,8 @@ dev/ice/irdma_if.m optional ice pci \
compile-with "${NORMAL_M} -I$S/dev/ice"
dev/ice/irdma_di_if.m optional ice pci \
compile-with "${NORMAL_M} -I$S/dev/ice"
+dev/ice/ice_ddp_common.c optional ice pci \
+ compile-with "${NORMAL_C} -I$S/dev/ice"
ice_ddp.c optional ice_ddp \
compile-with "${AWK} -f $S/tools/fw_stub.awk
ice_ddp.fw:ice_ddp:0x01031e00 -mice_ddp -c${.TARGET}" \
no-ctfconvert no-implicit-rule before-depend local \
diff --git a/sys/conf/files.arm64 b/sys/conf/files.arm64
index 88cb483f178f..6b96de28128d 100644
--- a/sys/conf/files.arm64
+++ b/sys/conf/files.arm64
@@ -235,6 +235,8 @@ dev/ice/irdma_if.m optional ice
pci \
compile-with "${NORMAL_M} -I$S/dev/ice"
dev/ice/irdma_di_if.m optional ice pci \
compile-with "${NORMAL_M} -I$S/dev/ice"
+dev/ice/ice_ddp_common.c optional ice pci \
+ compile-with "${NORMAL_C} -I$S/dev/ice"
ice_ddp.c optional ice_ddp \
compile-with "${AWK} -f $S/tools/fw_stub.awk
ice_ddp.fw:ice_ddp:0x01031e00 -mice_ddp -c${.TARGET}" \
no-ctfconvert no-implicit-rule before-depend local \
diff --git a/sys/conf/files.powerpc b/sys/conf/files.powerpc
index c01e0e81ab1a..05f331e2c3e0 100644
--- a/sys/conf/files.powerpc
+++ b/sys/conf/files.powerpc
@@ -38,48 +38,50 @@ dev/iicbus/max6690.c optional max6690
powermac
dev/iicbus/ofw_iicbus.c optional iicbus aim
dev/ipmi/ipmi.c optional ipmi
dev/ipmi/ipmi_opal.c optional powernv ipmi
-dev/ice/if_ice_iflib.c optional ice pci powerpc64 \
+dev/ice/if_ice_iflib.c optional ice pci powerpc64 | ice pci
powerpc64le \
compile-with "${NORMAL_C} -I$S/dev/ice"
-dev/ice/ice_lib.c optional ice pci powerpc64 \
+dev/ice/ice_lib.c optional ice pci powerpc64 | ice pci
powerpc64le \
compile-with "${NORMAL_C} -I$S/dev/ice"
-dev/ice/ice_osdep.c optional ice pci powerpc64 \
+dev/ice/ice_osdep.c optional ice pci powerpc64 | ice pci
powerpc64le \
compile-with "${NORMAL_C} -I$S/dev/ice"
-dev/ice/ice_resmgr.c optional ice pci powerpc64 \
+dev/ice/ice_resmgr.c optional ice pci powerpc64 | ice pci
powerpc64le \
compile-with "${NORMAL_C} -I$S/dev/ice"
-dev/ice/ice_strings.c optional ice pci powerpc64 \
+dev/ice/ice_strings.c optional ice pci powerpc64 | ice pci
powerpc64le \
compile-with "${NORMAL_C} -I$S/dev/ice"
-dev/ice/ice_iflib_recovery_txrx.c optional ice pci powerpc64 \
+dev/ice/ice_iflib_recovery_txrx.c optional ice pci powerpc64 | ice
pci powerpc64le \
compile-with "${NORMAL_C} -I$S/dev/ice"
-dev/ice/ice_iflib_txrx.c optional ice pci powerpc64 \
+dev/ice/ice_iflib_txrx.c optional ice pci powerpc64 | ice pci
powerpc64le \
compile-with "${NORMAL_C} -I$S/dev/ice"
-dev/ice/ice_common.c optional ice pci powerpc64 \
+dev/ice/ice_common.c optional ice pci powerpc64 | ice pci
powerpc64le \
compile-with "${NORMAL_C} -I$S/dev/ice"
-dev/ice/ice_controlq.c optional ice pci powerpc64 \
+dev/ice/ice_controlq.c optional ice pci powerpc64 | ice pci
powerpc64le \
compile-with "${NORMAL_C} -I$S/dev/ice"
-dev/ice/ice_dcb.c optional ice pci powerpc64 \
+dev/ice/ice_dcb.c optional ice pci powerpc64 | ice pci
powerpc64le \
compile-with "${NORMAL_C} -I$S/dev/ice"
-dev/ice/ice_flex_pipe.c optional ice pci powerpc64 \
+dev/ice/ice_flex_pipe.c optional ice pci powerpc64 | ice
pci powerpc64le \
compile-with "${NORMAL_C} -I$S/dev/ice"
-dev/ice/ice_flow.c optional ice pci powerpc64 \
+dev/ice/ice_flow.c optional ice pci powerpc64 | ice pci
powerpc64le \
compile-with "${NORMAL_C} -I$S/dev/ice"
-dev/ice/ice_nvm.c optional ice pci powerpc64 \
+dev/ice/ice_nvm.c optional ice pci powerpc64 | ice pci
powerpc64le \
compile-with "${NORMAL_C} -I$S/dev/ice"
-dev/ice/ice_sched.c optional ice pci powerpc64 \
+dev/ice/ice_sched.c optional ice pci powerpc64 | ice pci
powerpc64le \
compile-with "${NORMAL_C} -I$S/dev/ice"
-dev/ice/ice_switch.c optional ice pci powerpc64 \
+dev/ice/ice_switch.c optional ice pci powerpc64 | ice pci
powerpc64le \
compile-with "${NORMAL_C} -I$S/dev/ice"
-dev/ice/ice_vlan_mode.c optional ice pci powerpc64 \
+dev/ice/ice_vlan_mode.c optional ice pci powerpc64 | ice
pci powerpc64le \
compile-with "${NORMAL_C} -I$S/dev/ice"
-dev/ice/ice_fw_logging.c optional ice pci powerpc64 \
+dev/ice/ice_fw_logging.c optional ice pci powerpc64 | ice pci
powerpc64le \
compile-with "${NORMAL_C} -I$S/dev/ice"
-dev/ice/ice_fwlog.c optional ice pci powerpc64 \
+dev/ice/ice_fwlog.c optional ice pci powerpc64 | ice pci
powerpc64le \
compile-with "${NORMAL_C} -I$S/dev/ice"
-dev/ice/ice_rdma.c optional ice pci powerpc64 \
+dev/ice/ice_rdma.c optional ice pci powerpc64 | ice pci
powerpc64le \
compile-with "${NORMAL_C} -I$S/dev/ice"
-dev/ice/irdma_if.m optional ice pci powerpc64 \
+dev/ice/irdma_if.m optional ice pci powerpc64 | ice pci
powerpc64le \
compile-with "${NORMAL_M} -I$S/dev/ice"
-dev/ice/irdma_di_if.m optional ice pci powerpc64 \
+dev/ice/irdma_di_if.m optional ice pci powerpc64 | ice pci
powerpc64le \
compile-with "${NORMAL_M} -I$S/dev/ice"
+dev/ice/ice_ddp_common.c optional ice pci powerpc64 | ice pci
powerpc64le \
+ compile-with "${NORMAL_C} -I$S/dev/ice"
ice_ddp.c optional ice_ddp powerpc64 | ice pci
powerpc64le \
compile-with "${AWK} -f $S/tools/fw_stub.awk
ice_ddp.fw:ice_ddp:0x01031e00 -mice_ddp -c${.TARGET}" \
no-ctfconvert no-implicit-rule before-depend local \
diff --git a/sys/dev/ice/ice_adminq_cmd.h b/sys/dev/ice/ice_adminq_cmd.h
index a07ca6780a3c..92ad8055b666 100644
--- a/sys/dev/ice/ice_adminq_cmd.h
+++ b/sys/dev/ice/ice_adminq_cmd.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright (c) 2021, Intel Corporation
+/* Copyright (c) 2022, Intel Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -37,10 +37,19 @@
* descriptor format. It is shared between Firmware and Software.
*/
+#include "ice_osdep.h"
+#include "ice_defs.h"
+#include "ice_bitops.h"
+
#define ICE_MAX_VSI 768
#define ICE_AQC_TOPO_MAX_LEVEL_NUM 0x9
#define ICE_AQ_SET_MAC_FRAME_SIZE_MAX 9728
+enum ice_aq_res_access_type {
+ ICE_RES_READ = 1,
+ ICE_RES_WRITE
+};
+
struct ice_aqc_generic {
__le32 param0;
__le32 param1;
@@ -155,9 +164,6 @@ struct ice_aqc_list_caps_elem {
#define ICE_AQC_CAPS_TXQS 0x0042
#define ICE_AQC_CAPS_MSIX 0x0043
#define ICE_AQC_CAPS_MAX_MTU 0x0047
-#define ICE_AQC_CAPS_NVM_VER 0x0048
-#define ICE_AQC_CAPS_OROM_VER 0x004A
-#define ICE_AQC_CAPS_NET_VER 0x004C
#define ICE_AQC_CAPS_CEM 0x00F2
#define ICE_AQC_CAPS_IWARP 0x0051
#define ICE_AQC_CAPS_LED 0x0061
@@ -173,6 +179,10 @@ struct ice_aqc_list_caps_elem {
#define ICE_AQC_CAPS_EXT_TOPO_DEV_IMG1 0x0082
#define ICE_AQC_CAPS_EXT_TOPO_DEV_IMG2 0x0083
#define ICE_AQC_CAPS_EXT_TOPO_DEV_IMG3 0x0084
+#define ICE_AQC_CAPS_TX_SCHED_TOPO_COMP_MODE 0x0085
+#define ICE_AQC_CAPS_NAC_TOPOLOGY 0x0087
+#define ICE_AQC_CAPS_DYN_FLATTENING 0x0090
+#define ICE_AQC_CAPS_ROCEV2_LAG 0x0092
u8 major_ver;
u8 minor_ver;
@@ -526,6 +536,7 @@ struct ice_aqc_vsi_props {
#define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0
#define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M (0xF <<
ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S)
#define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0)
+#define ICE_AQ_VSI_SW_FLAG_RX_PASS_PRUNE_ENA BIT(3)
#define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4)
u8 veb_stat_id;
#define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0
@@ -836,6 +847,8 @@ struct ice_sw_rule_lkup_rx_tx {
#define ICE_SINGLE_ACT_PTR 0x2
#define ICE_SINGLE_ACT_PTR_VAL_S 4
#define ICE_SINGLE_ACT_PTR_VAL_M (0x1FFF << ICE_SINGLE_ACT_PTR_VAL_S)
+ /* Bit 17 should be set if pointed action includes a FWD cmd */
+#define ICE_SINGLE_ACT_PTR_HAS_FWD BIT(17)
/* Bit 18 should be set to 1 */
#define ICE_SINGLE_ACT_PTR_BIT BIT(18)
@@ -1017,6 +1030,24 @@ struct ice_aqc_get_topo {
__le32 addr_low;
};
+/* Get/Set Tx Topology (indirect 0x0418/0x0417) */
+struct ice_aqc_get_set_tx_topo {
+ u8 set_flags;
+#define ICE_AQC_TX_TOPO_FLAGS_CORRER BIT(0)
+#define ICE_AQC_TX_TOPO_FLAGS_SRC_RAM BIT(1)
+#define ICE_AQC_TX_TOPO_FLAGS_SET_PSM BIT(2)
+#define ICE_AQC_TX_TOPO_FLAGS_LOAD_NEW BIT(4)
+#define ICE_AQC_TX_TOPO_FLAGS_ISSUED BIT(5)
+ u8 get_flags;
+#define ICE_AQC_TX_TOPO_GET_NO_UPDATE 0
+#define ICE_AQC_TX_TOPO_GET_PSM 1
+#define ICE_AQC_TX_TOPO_GET_RAM 2
+ __le16 reserved1;
+ __le32 reserved2;
+ __le32 addr_high;
+ __le32 addr_low;
+};
+
/* Update TSE (indirect 0x0403)
* Get TSE (indirect 0x0404)
* Add TSE (indirect 0x0401)
@@ -1170,6 +1201,22 @@ struct ice_aqc_rl_profile_elem {
__le16 rl_encode;
};
+/* Config Node Attributes (indirect 0x0419)
+ * Query Node Attributes (indirect 0x041A)
+ */
+struct ice_aqc_node_attr {
+ __le16 num_entries; /* Number of attributes structures in the buffer */
+ u8 reserved[6];
+ __le32 addr_high;
+ __le32 addr_low;
+};
+
+struct ice_aqc_node_attr_elem {
+ __le32 node_teid;
+ __le16 max_children;
+ __le16 children_level;
+};
+
/* Configure L2 Node CGD (indirect 0x0414)
* This indirect command allows configuring a congestion domain for given L2
* node TEIDs in the scheduler topology.
@@ -1335,7 +1382,7 @@ struct ice_aqc_get_phy_caps {
#define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2)
#define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3)
#define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4)
-#define ICE_PHY_TYPE_HIGH_MAX_INDEX 5
+#define ICE_PHY_TYPE_HIGH_MAX_INDEX 4
struct ice_aqc_get_phy_caps_data {
__le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
@@ -1376,6 +1423,7 @@ struct ice_aqc_get_phy_caps_data {
#define ICE_AQC_PHY_FEC_25G_RS_528_REQ BIT(2)
#define ICE_AQC_PHY_FEC_25G_KR_REQ BIT(3)
#define ICE_AQC_PHY_FEC_25G_RS_544_REQ BIT(4)
+#define ICE_AQC_PHY_FEC_DIS BIT(5)
#define ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN BIT(6)
#define ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN BIT(7)
#define ICE_AQC_PHY_FEC_MASK MAKEMASK(0xdf, 0)
@@ -1484,6 +1532,12 @@ struct ice_aqc_get_link_status {
__le32 addr_low;
};
+enum ice_get_link_status_data_version {
+ ICE_GET_LINK_STATUS_DATA_V1 = 1,
+};
+
+#define ICE_GET_LINK_STATUS_DATALEN_V1 32
+
/* Get link status response data structure, also used for Link Status Event */
struct ice_aqc_get_link_status_data {
u8 topo_media_conflict;
@@ -2078,6 +2132,12 @@ struct ice_aqc_nvm {
#define ICE_AQC_NVM_PERST_FLAG 1
#define ICE_AQC_NVM_EMPR_FLAG 2
#define ICE_AQC_NVM_EMPR_ENA BIT(0) /* Write Activate reply only */
+ /* For Write Activate, several flags are sent as part of a separate
+ * flags2 field using a separate byte. For simplicity of the software
+ * interface, we pass the flags as a 16 bit value so these flags are
+ * all offset by 8 bits
+ */
+#define ICE_AQC_NVM_ACTIV_REQ_EMPR BIT(8) /* NVM Write Activate only */
__le16 module_typeid;
__le16 length;
#define ICE_AQC_NVM_ERASE_LEN 0xFFFF
@@ -2108,6 +2168,7 @@ struct ice_aqc_nvm {
#define ICE_AQC_NVM_LLDP_STATUS_RD_LEN 4 /* In Bytes */
#define ICE_AQC_NVM_MINSREV_MOD_ID 0x130
+#define ICE_AQC_NVM_TX_TOPO_MOD_ID 0x14B
/* Used for reading and writing MinSRev using 0x0701 and 0x0703. Note that the
* type field is excluded from the section when reading and writing from
@@ -2124,6 +2185,13 @@ struct ice_aqc_nvm_minsrev {
__le16 orom_minsrev_h;
};
+struct ice_aqc_nvm_tx_topo_user_sel {
+ __le16 length;
+ u8 data;
+#define ICE_AQC_NVM_TX_TOPO_USER_SEL BIT(4)
+ u8 reserved;
+};
+
/* Used for 0x0704 as well as for 0x0705 commands */
struct ice_aqc_nvm_cfg {
u8 cmd_flags;
@@ -2218,14 +2286,25 @@ struct ice_aqc_lldp_get_mib {
#define ICE_AQ_LLDP_TX_ACTIVE 0
#define ICE_AQ_LLDP_TX_SUSPENDED 1
#define ICE_AQ_LLDP_TX_FLUSHED 3
+/* DCBX mode */
+#define ICE_AQ_LLDP_DCBX_S 6
+#define ICE_AQ_LLDP_DCBX_M (0x3 << ICE_AQ_LLDP_DCBX_S)
+#define ICE_AQ_LLDP_DCBX_NA 0
+#define ICE_AQ_LLDP_DCBX_CEE 1
+#define ICE_AQ_LLDP_DCBX_IEEE 2
/* The following bytes are reserved for the Get LLDP MIB command (0x0A00)
* and in the LLDP MIB Change Event (0x0A01). They are valid for the
* Get LLDP MIB (0x0A00) response only.
*/
- u8 reserved1;
+ u8 state;
+#define ICE_AQ_LLDP_MIB_CHANGE_STATE_S 0
+#define ICE_AQ_LLDP_MIB_CHANGE_STATE_M \
+ (0x1 << ICE_AQ_LLDP_MIB_CHANGE_STATE_S)
+#define ICE_AQ_LLDP_MIB_CHANGE_EXECUTED 0
+#define ICE_AQ_LLDP_MIB_CHANGE_PENDING 1
__le16 local_len;
__le16 remote_len;
- u8 reserved2[2];
+ u8 reserved[2];
__le32 addr_high;
__le32 addr_low;
};
@@ -2236,6 +2315,11 @@ struct ice_aqc_lldp_set_mib_change {
u8 command;
#define ICE_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
#define ICE_AQ_LLDP_MIB_UPDATE_DIS 0x1
+#define ICE_AQ_LLDP_MIB_PENDING_S 1
+#define ICE_AQ_LLDP_MIB_PENDING_M \
+ (0x1 << ICE_AQ_LLDP_MIB_PENDING_S)
+#define ICE_AQ_LLDP_MIB_PENDING_DISABLE 0
+#define ICE_AQ_LLDP_MIB_PENDING_ENABLE 1
u8 reserved[15];
};
@@ -2580,6 +2664,9 @@ struct ice_aqc_add_rdma_qset_data {
/* Move RDMA Queue Set (indirect 0x0C34) */
struct ice_aqc_move_rdma_qset_cmd {
u8 num_rdma_qset; /* Used by commands and response */
+#define ICE_AQC_PF_MODE_SAME_PF 0x0
+#define ICE_AQC_PF_MODE_GIVE_OWNERSHIP 0x1
+#define ICE_AQC_PF_MODE_KEEP_OWNERSHIP 0x2
u8 flags;
u8 reserved[6];
__le32 addr_high;
@@ -2656,8 +2743,8 @@ struct ice_aqc_get_pkg_info_resp {
struct ice_aqc_driver_shared_params {
u8 set_or_get_op;
#define ICE_AQC_DRIVER_PARAM_OP_MASK BIT(0)
-#define ICE_AQC_DRIVER_PARAM_SET 0
-#define ICE_AQC_DRIVER_PARAM_GET 1
+#define ICE_AQC_DRIVER_PARAM_SET ((u8)0)
+#define ICE_AQC_DRIVER_PARAM_GET ((u8)1)
u8 param_indx;
#define ICE_AQC_DRIVER_PARAM_MAX_IDX 15
u8 rsvd[2];
@@ -2676,16 +2763,18 @@ struct ice_aqc_event_lan_overflow {
/* Debug Dump Internal Data (indirect 0xFF08) */
struct ice_aqc_debug_dump_internals {
u8 cluster_id;
-#define ICE_AQC_DBG_DUMP_CLUSTER_ID_SW 0
-#define ICE_AQC_DBG_DUMP_CLUSTER_ID_TXSCHED 2
-#define ICE_AQC_DBG_DUMP_CLUSTER_ID_PROFILES 3
+#define ICE_AQC_DBG_DUMP_CLUSTER_ID_SW 0
+#define ICE_AQC_DBG_DUMP_CLUSTER_ID_TXSCHED 2
+#define ICE_AQC_DBG_DUMP_CLUSTER_ID_PROFILES 3
/* EMP_DRAM only dumpable in device debug mode */
-#define ICE_AQC_DBG_DUMP_CLUSTER_ID_EMP_DRAM 4
-#define ICE_AQC_DBG_DUMP_CLUSTER_ID_LINK 5
+#define ICE_AQC_DBG_DUMP_CLUSTER_ID_EMP_DRAM 4
+#define ICE_AQC_DBG_DUMP_CLUSTER_ID_LINK 5
/* AUX_REGS only dumpable in device debug mode */
-#define ICE_AQC_DBG_DUMP_CLUSTER_ID_AUX_REGS 6
-#define ICE_AQC_DBG_DUMP_CLUSTER_ID_DCB 7
-#define ICE_AQC_DBG_DUMP_CLUSTER_ID_L2P 8
+#define ICE_AQC_DBG_DUMP_CLUSTER_ID_AUX_REGS 6
+#define ICE_AQC_DBG_DUMP_CLUSTER_ID_DCB 7
+#define ICE_AQC_DBG_DUMP_CLUSTER_ID_L2P 8
+#define ICE_AQC_DBG_DUMP_CLUSTER_ID_QUEUE_MNG 9
+#define ICE_AQC_DBG_DUMP_CLUSTER_ID_FULL_CSR_SPACE 21
u8 reserved;
__le16 table_id; /* Used only for non-memory clusters */
__le32 idx; /* In table entries for tables, in bytes for memory */
@@ -2729,7 +2818,6 @@ enum ice_aqc_fw_logging_mod {
ICE_AQC_FW_LOG_ID_MAX,
};
-
/* Set Health Status (direct 0xFF20) */
struct ice_aqc_set_health_status_config {
u8 event_source;
@@ -2747,6 +2835,7 @@ struct ice_aqc_set_health_status_config {
#define ICE_AQC_HEALTH_STATUS_ERR_MOD_NOT_PRESENT 0x106
#define ICE_AQC_HEALTH_STATUS_INFO_MOD_UNDERUTILIZED 0x107
#define ICE_AQC_HEALTH_STATUS_ERR_UNKNOWN_MOD_LENIENT 0x108
+#define ICE_AQC_HEALTH_STATUS_ERR_MOD_DIAGNOSTIC_FEATURE 0x109
#define ICE_AQC_HEALTH_STATUS_ERR_INVALID_LINK_CFG 0x10B
#define ICE_AQC_HEALTH_STATUS_ERR_PORT_ACCESS 0x10C
#define ICE_AQC_HEALTH_STATUS_ERR_PORT_UNREACHABLE 0x10D
@@ -2768,7 +2857,16 @@ struct ice_aqc_set_health_status_config {
#define ICE_AQC_HEALTH_STATUS_ERR_DDP_AUTH 0x504
#define ICE_AQC_HEALTH_STATUS_ERR_NVM_COMPAT 0x505
#define ICE_AQC_HEALTH_STATUS_ERR_OROM_COMPAT 0x506
+#define ICE_AQC_HEALTH_STATUS_ERR_NVM_SEC_VIOLATION 0x507
+#define ICE_AQC_HEALTH_STATUS_ERR_OROM_SEC_VIOLATION 0x508
#define ICE_AQC_HEALTH_STATUS_ERR_DCB_MIB 0x509
+#define ICE_AQC_HEALTH_STATUS_ERR_MNG_TIMEOUT 0x50A
+#define ICE_AQC_HEALTH_STATUS_ERR_BMC_RESET 0x50B
+#define ICE_AQC_HEALTH_STATUS_ERR_LAST_MNG_FAIL 0x50C
+#define ICE_AQC_HEALTH_STATUS_ERR_RESOURCE_ALLOC_FAIL 0x50D
+#define ICE_AQC_HEALTH_STATUS_ERR_FW_LOOP 0x1000
+#define ICE_AQC_HEALTH_STATUS_ERR_FW_PFR_FAIL 0x1001
+#define ICE_AQC_HEALTH_STATUS_ERR_LAST_FAIL_AQ 0x1002
/* Get Health Status codes (indirect 0xFF21) */
struct ice_aqc_get_supported_health_status_codes {
@@ -2923,6 +3021,7 @@ struct ice_aq_desc {
struct ice_aqc_cfg_l2_node_cgd cfg_l2_node_cgd;
struct ice_aqc_query_port_ets port_ets;
struct ice_aqc_rl_profile rl_profile;
+ struct ice_aqc_node_attr node_attr;
struct ice_aqc_nvm nvm;
struct ice_aqc_nvm_cfg nvm_cfg;
struct ice_aqc_nvm_checksum nvm_checksum;
@@ -2949,6 +3048,7 @@ struct ice_aq_desc {
struct ice_aqc_dis_txqs dis_txqs;
struct ice_aqc_move_txqs move_txqs;
struct ice_aqc_add_rdma_qset add_rdma_qset;
+ struct ice_aqc_move_rdma_qset_cmd move_rdma_qset;
struct ice_aqc_txqs_cleanup txqs_cleanup;
struct ice_aqc_add_get_update_free_vsi vsi_cmd;
struct ice_aqc_add_update_free_vsi_resp add_update_free_vsi_res;
@@ -2975,6 +3075,7 @@ struct ice_aq_desc {
struct ice_aqc_clear_health_status clear_health_status;
struct ice_aqc_prog_topo_dev_nvm prog_topo_dev_nvm;
struct ice_aqc_read_topo_dev_nvm read_topo_dev_nvm;
+ struct ice_aqc_get_set_tx_topo get_set_tx_topo;
} params;
};
@@ -3125,6 +3226,10 @@ enum ice_adminq_opc {
ice_aqc_opc_query_node_to_root = 0x0413,
ice_aqc_opc_cfg_l2_node_cgd = 0x0414,
ice_aqc_opc_remove_rl_profiles = 0x0415,
+ ice_aqc_opc_set_tx_topo = 0x0417,
+ ice_aqc_opc_get_tx_topo = 0x0418,
+ ice_aqc_opc_cfg_node_attr = 0x0419,
+ ice_aqc_opc_query_node_attr = 0x041A,
/* PHY commands */
ice_aqc_opc_get_phy_caps = 0x0600,
@@ -3196,6 +3301,7 @@ enum ice_adminq_opc {
ice_aqc_opc_lldp_set_local_mib = 0x0A08,
ice_aqc_opc_lldp_stop_start_specific_agent = 0x0A09,
ice_aqc_opc_lldp_filter_ctrl = 0x0A0A,
+ ice_execute_pending_lldp_mib = 0x0A0B,
/* RSS commands */
ice_aqc_opc_set_rss_key = 0x0B02,
diff --git a/sys/dev/ice/ice_alloc.h b/sys/dev/ice/ice_alloc.h
index b281958be793..bfcb376d45b2 100644
--- a/sys/dev/ice/ice_alloc.h
+++ b/sys/dev/ice/ice_alloc.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright (c) 2021, Intel Corporation
+/* Copyright (c) 2022, Intel Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
diff --git a/sys/dev/ice/ice_bitops.h b/sys/dev/ice/ice_bitops.h
index 0e04cab87be9..c29963d0a318 100644
--- a/sys/dev/ice/ice_bitops.h
+++ b/sys/dev/ice/ice_bitops.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright (c) 2021, Intel Corporation
+/* Copyright (c) 2022, Intel Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -33,15 +33,25 @@
#ifndef _ICE_BITOPS_H_
#define _ICE_BITOPS_H_
+#include "ice_defs.h"
+#include "ice_osdep.h"
+
/* Define the size of the bitmap chunk */
typedef u32 ice_bitmap_t;
+/* NOTE!
+ * Do not use any of the functions declared in this file
+ * on memory that was not declared with ice_declare_bitmap.
+ * Not following this rule might cause issues like split
+ * locks.
+ */
+
/* Number of bits per bitmap chunk */
#define BITS_PER_CHUNK (BITS_PER_BYTE * sizeof(ice_bitmap_t))
/* Determine which chunk a bit belongs in */
#define BIT_CHUNK(nr) ((nr) / BITS_PER_CHUNK)
/* How many chunks are required to store this many bits */
-#define BITS_TO_CHUNKS(sz) DIVIDE_AND_ROUND_UP((sz), BITS_PER_CHUNK)
+#define BITS_TO_CHUNKS(sz) (((sz) + BITS_PER_CHUNK - 1) / BITS_PER_CHUNK)
/* Which bit inside a chunk this bit corresponds to */
#define BIT_IN_CHUNK(nr) ((nr) % BITS_PER_CHUNK)
/* How many bits are valid in the last chunk, assumes nr > 0 */
diff --git a/sys/dev/ice/ice_common.c b/sys/dev/ice/ice_common.c
index 3ae266b72d1f..c2efddeb4f7c 100644
--- a/sys/dev/ice/ice_common.c
+++ b/sys/dev/ice/ice_common.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright (c) 2021, Intel Corporation
+/* Copyright (c) 2022, Intel Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -39,118 +39,110 @@
#define ICE_PF_RESET_WAIT_COUNT 300
-/**
- * dump_phy_type - helper function that prints PHY type strings
- * @hw: pointer to the HW structure
- * @phy: 64 bit PHY type to decipher
- * @i: bit index within phy
- * @phy_string: string corresponding to bit i in phy
- * @prefix: prefix string to differentiate multiple dumps
- */
-static void
-dump_phy_type(struct ice_hw *hw, u64 phy, u8 i, const char *phy_string,
- const char *prefix)
-{
- if (phy & BIT_ULL(i))
- ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n", prefix, i,
- phy_string);
-}
+static const char * const ice_link_mode_str_low[] = {
+ [0] = "100BASE_TX",
+ [1] = "100M_SGMII",
+ [2] = "1000BASE_T",
+ [3] = "1000BASE_SX",
+ [4] = "1000BASE_LX",
+ [5] = "1000BASE_KX",
+ [6] = "1G_SGMII",
+ [7] = "2500BASE_T",
+ [8] = "2500BASE_X",
+ [9] = "2500BASE_KX",
+ [10] = "5GBASE_T",
+ [11] = "5GBASE_KR",
+ [12] = "10GBASE_T",
+ [13] = "10G_SFI_DA",
+ [14] = "10GBASE_SR",
+ [15] = "10GBASE_LR",
+ [16] = "10GBASE_KR_CR1",
+ [17] = "10G_SFI_AOC_ACC",
+ [18] = "10G_SFI_C2C",
+ [19] = "25GBASE_T",
+ [20] = "25GBASE_CR",
+ [21] = "25GBASE_CR_S",
+ [22] = "25GBASE_CR1",
+ [23] = "25GBASE_SR",
+ [24] = "25GBASE_LR",
+ [25] = "25GBASE_KR",
+ [26] = "25GBASE_KR_S",
+ [27] = "25GBASE_KR1",
+ [28] = "25G_AUI_AOC_ACC",
+ [29] = "25G_AUI_C2C",
+ [30] = "40GBASE_CR4",
+ [31] = "40GBASE_SR4",
+ [32] = "40GBASE_LR4",
+ [33] = "40GBASE_KR4",
+ [34] = "40G_XLAUI_AOC_ACC",
+ [35] = "40G_XLAUI",
+ [36] = "50GBASE_CR2",
+ [37] = "50GBASE_SR2",
+ [38] = "50GBASE_LR2",
+ [39] = "50GBASE_KR2",
+ [40] = "50G_LAUI2_AOC_ACC",
+ [41] = "50G_LAUI2",
+ [42] = "50G_AUI2_AOC_ACC",
+ [43] = "50G_AUI2",
+ [44] = "50GBASE_CP",
+ [45] = "50GBASE_SR",
+ [46] = "50GBASE_FR",
+ [47] = "50GBASE_LR",
+ [48] = "50GBASE_KR_PAM4",
+ [49] = "50G_AUI1_AOC_ACC",
+ [50] = "50G_AUI1",
+ [51] = "100GBASE_CR4",
+ [52] = "100GBASE_SR4",
+ [53] = "100GBASE_LR4",
+ [54] = "100GBASE_KR4",
+ [55] = "100G_CAUI4_AOC_ACC",
+ [56] = "100G_CAUI4",
+ [57] = "100G_AUI4_AOC_ACC",
+ [58] = "100G_AUI4",
+ [59] = "100GBASE_CR_PAM4",
+ [60] = "100GBASE_KR_PAM4",
+ [61] = "100GBASE_CP2",
+ [62] = "100GBASE_SR2",
+ [63] = "100GBASE_DR",
+};
+
+static const char * const ice_link_mode_str_high[] = {
+ [0] = "100GBASE_KR2_PAM4",
+ [1] = "100G_CAUI2_AOC_ACC",
+ [2] = "100G_CAUI2",
+ [3] = "100G_AUI2_AOC_ACC",
+ [4] = "100G_AUI2",
+};
/**
- * ice_dump_phy_type_low - helper function to dump phy_type_low
+ * ice_dump_phy_type - helper function to dump phy_type
* @hw: pointer to the HW structure
* @low: 64 bit value for phy_type_low
+ * @high: 64 bit value for phy_type_high
* @prefix: prefix string to differentiate multiple dumps
*/
static void
-ice_dump_phy_type_low(struct ice_hw *hw, u64 low, const char *prefix)
+ice_dump_phy_type(struct ice_hw *hw, u64 low, u64 high, const char *prefix)
{
+ u32 i;
+
ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_low: 0x%016llx\n", prefix,
(unsigned long long)low);
- dump_phy_type(hw, low, 0, "100BASE_TX", prefix);
- dump_phy_type(hw, low, 1, "100M_SGMII", prefix);
- dump_phy_type(hw, low, 2, "1000BASE_T", prefix);
- dump_phy_type(hw, low, 3, "1000BASE_SX", prefix);
- dump_phy_type(hw, low, 4, "1000BASE_LX", prefix);
- dump_phy_type(hw, low, 5, "1000BASE_KX", prefix);
- dump_phy_type(hw, low, 6, "1G_SGMII", prefix);
- dump_phy_type(hw, low, 7, "2500BASE_T", prefix);
- dump_phy_type(hw, low, 8, "2500BASE_X", prefix);
- dump_phy_type(hw, low, 9, "2500BASE_KX", prefix);
- dump_phy_type(hw, low, 10, "5GBASE_T", prefix);
- dump_phy_type(hw, low, 11, "5GBASE_KR", prefix);
- dump_phy_type(hw, low, 12, "10GBASE_T", prefix);
- dump_phy_type(hw, low, 13, "10G_SFI_DA", prefix);
- dump_phy_type(hw, low, 14, "10GBASE_SR", prefix);
- dump_phy_type(hw, low, 15, "10GBASE_LR", prefix);
- dump_phy_type(hw, low, 16, "10GBASE_KR_CR1", prefix);
- dump_phy_type(hw, low, 17, "10G_SFI_AOC_ACC", prefix);
- dump_phy_type(hw, low, 18, "10G_SFI_C2C", prefix);
- dump_phy_type(hw, low, 19, "25GBASE_T", prefix);
- dump_phy_type(hw, low, 20, "25GBASE_CR", prefix);
- dump_phy_type(hw, low, 21, "25GBASE_CR_S", prefix);
- dump_phy_type(hw, low, 22, "25GBASE_CR1", prefix);
- dump_phy_type(hw, low, 23, "25GBASE_SR", prefix);
- dump_phy_type(hw, low, 24, "25GBASE_LR", prefix);
- dump_phy_type(hw, low, 25, "25GBASE_KR", prefix);
- dump_phy_type(hw, low, 26, "25GBASE_KR_S", prefix);
- dump_phy_type(hw, low, 27, "25GBASE_KR1", prefix);
- dump_phy_type(hw, low, 28, "25G_AUI_AOC_ACC", prefix);
- dump_phy_type(hw, low, 29, "25G_AUI_C2C", prefix);
- dump_phy_type(hw, low, 30, "40GBASE_CR4", prefix);
- dump_phy_type(hw, low, 31, "40GBASE_SR4", prefix);
- dump_phy_type(hw, low, 32, "40GBASE_LR4", prefix);
- dump_phy_type(hw, low, 33, "40GBASE_KR4", prefix);
- dump_phy_type(hw, low, 34, "40G_XLAUI_AOC_ACC", prefix);
- dump_phy_type(hw, low, 35, "40G_XLAUI", prefix);
- dump_phy_type(hw, low, 36, "50GBASE_CR2", prefix);
- dump_phy_type(hw, low, 37, "50GBASE_SR2", prefix);
- dump_phy_type(hw, low, 38, "50GBASE_LR2", prefix);
- dump_phy_type(hw, low, 39, "50GBASE_KR2", prefix);
- dump_phy_type(hw, low, 40, "50G_LAUI2_AOC_ACC", prefix);
- dump_phy_type(hw, low, 41, "50G_LAUI2", prefix);
- dump_phy_type(hw, low, 42, "50G_AUI2_AOC_ACC", prefix);
- dump_phy_type(hw, low, 43, "50G_AUI2", prefix);
- dump_phy_type(hw, low, 44, "50GBASE_CP", prefix);
- dump_phy_type(hw, low, 45, "50GBASE_SR", prefix);
- dump_phy_type(hw, low, 46, "50GBASE_FR", prefix);
- dump_phy_type(hw, low, 47, "50GBASE_LR", prefix);
- dump_phy_type(hw, low, 48, "50GBASE_KR_PAM4", prefix);
- dump_phy_type(hw, low, 49, "50G_AUI1_AOC_ACC", prefix);
- dump_phy_type(hw, low, 50, "50G_AUI1", prefix);
- dump_phy_type(hw, low, 51, "100GBASE_CR4", prefix);
- dump_phy_type(hw, low, 52, "100GBASE_SR4", prefix);
- dump_phy_type(hw, low, 53, "100GBASE_LR4", prefix);
- dump_phy_type(hw, low, 54, "100GBASE_KR4", prefix);
- dump_phy_type(hw, low, 55, "100G_CAUI4_AOC_ACC", prefix);
- dump_phy_type(hw, low, 56, "100G_CAUI4", prefix);
- dump_phy_type(hw, low, 57, "100G_AUI4_AOC_ACC", prefix);
- dump_phy_type(hw, low, 58, "100G_AUI4", prefix);
- dump_phy_type(hw, low, 59, "100GBASE_CR_PAM4", prefix);
- dump_phy_type(hw, low, 60, "100GBASE_KR_PAM4", prefix);
- dump_phy_type(hw, low, 61, "100GBASE_CP2", prefix);
- dump_phy_type(hw, low, 62, "100GBASE_SR2", prefix);
- dump_phy_type(hw, low, 63, "100GBASE_DR", prefix);
-}
-
-/**
- * ice_dump_phy_type_high - helper function to dump phy_type_high
- * @hw: pointer to the HW structure
- * @high: 64 bit value for phy_type_high
- * @prefix: prefix string to differentiate multiple dumps
- */
-static void
-ice_dump_phy_type_high(struct ice_hw *hw, u64 high, const char *prefix)
-{
+ for (i = 0; i < ARRAY_SIZE(ice_link_mode_str_low); i++) {
+ if (low & BIT_ULL(i))
+ ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n",
+ prefix, i, ice_link_mode_str_low[i]);
+ }
+
ice_debug(hw, ICE_DBG_PHY, "%s: phy_type_high: 0x%016llx\n", prefix,
(unsigned long long)high);
- dump_phy_type(hw, high, 0, "100GBASE_KR2_PAM4", prefix);
- dump_phy_type(hw, high, 1, "100G_CAUI2_AOC_ACC", prefix);
- dump_phy_type(hw, high, 2, "100G_CAUI2", prefix);
- dump_phy_type(hw, high, 3, "100G_AUI2_AOC_ACC", prefix);
- dump_phy_type(hw, high, 4, "100G_AUI2", prefix);
+ for (i = 0; i < ARRAY_SIZE(ice_link_mode_str_high); i++) {
+ if (high & BIT_ULL(i))
+ ice_debug(hw, ICE_DBG_PHY, "%s: bit(%d): %s\n",
+ prefix, i, ice_link_mode_str_high[i]);
+ }
}
/**
@@ -227,13 +219,23 @@ bool ice_is_e810t(struct ice_hw *hw)
{
switch (hw->device_id) {
case ICE_DEV_ID_E810C_SFP:
- if (hw->subsystem_device_id == ICE_SUBDEV_ID_E810T ||
- hw->subsystem_device_id == ICE_SUBDEV_ID_E810T2)
+ switch (hw->subsystem_device_id) {
+ case ICE_SUBDEV_ID_E810T:
+ case ICE_SUBDEV_ID_E810T2:
+ case ICE_SUBDEV_ID_E810T3:
+ case ICE_SUBDEV_ID_E810T4:
+ case ICE_SUBDEV_ID_E810T5:
+ case ICE_SUBDEV_ID_E810T7:
return true;
+ }
break;
case ICE_DEV_ID_E810C_QSFP:
- if (hw->subsystem_device_id == ICE_SUBDEV_ID_E810T2)
+ switch (hw->subsystem_device_id) {
+ case ICE_SUBDEV_ID_E810T2:
+ case ICE_SUBDEV_ID_E810T5:
+ case ICE_SUBDEV_ID_E810T6:
return true;
+ }
break;
default:
break;
@@ -242,6 +244,31 @@ bool ice_is_e810t(struct ice_hw *hw)
return false;
}
+/**
+ * ice_is_e823
+ * @hw: pointer to the hardware structure
+ *
+ * returns true if the device is E823-L or E823-C based, false if not.
+ */
+bool ice_is_e823(struct ice_hw *hw)
+{
+ switch (hw->device_id) {
+ case ICE_DEV_ID_E823L_BACKPLANE:
+ case ICE_DEV_ID_E823L_SFP:
+ case ICE_DEV_ID_E823L_10G_BASE_T:
+ case ICE_DEV_ID_E823L_1GBE:
+ case ICE_DEV_ID_E823L_QSFP:
+ case ICE_DEV_ID_E823C_BACKPLANE:
+ case ICE_DEV_ID_E823C_QSFP:
+ case ICE_DEV_ID_E823C_SFP:
+ case ICE_DEV_ID_E823C_10G_BASE_T:
+ case ICE_DEV_ID_E823C_SGMII:
+ return true;
+ default:
+ return false;
+ }
+}
+
/**
* ice_clear_pf_cfg - Clear PF configuration
* @hw: pointer to the hardware structure
@@ -308,10 +335,10 @@ ice_aq_manage_mac_read(struct ice_hw *hw, void *buf, u16
buf_size,
if (resp[i].addr_type == ICE_AQC_MAN_MAC_ADDR_TYPE_LAN) {
ice_memcpy(hw->port_info->mac.lan_addr,
resp[i].mac_addr, ETH_ALEN,
- ICE_DMA_TO_NONDMA);
+ ICE_NONDMA_TO_NONDMA);
ice_memcpy(hw->port_info->mac.perm_addr,
resp[i].mac_addr,
- ETH_ALEN, ICE_DMA_TO_NONDMA);
+ ETH_ALEN, ICE_NONDMA_TO_NONDMA);
break;
}
return ICE_SUCCESS;
@@ -355,23 +382,30 @@ ice_aq_get_phy_caps(struct ice_port_info *pi, bool
qual_mods, u8 report_mode,
cmd->param0 |= CPU_TO_LE16(ICE_AQC_GET_PHY_RQM);
cmd->param0 |= CPU_TO_LE16(report_mode);
+
status = ice_aq_send_cmd(hw, &desc, pcaps, pcaps_size, cd);
ice_debug(hw, ICE_DBG_LINK, "get phy caps dump\n");
- if (report_mode == ICE_AQC_REPORT_TOPO_CAP_MEDIA)
+ switch (report_mode) {
+ case ICE_AQC_REPORT_TOPO_CAP_MEDIA:
prefix = "phy_caps_media";
- else if (report_mode == ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA)
+ break;
+ case ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA:
prefix = "phy_caps_no_media";
- else if (report_mode == ICE_AQC_REPORT_ACTIVE_CFG)
+ break;
+ case ICE_AQC_REPORT_ACTIVE_CFG:
prefix = "phy_caps_active";
- else if (report_mode == ICE_AQC_REPORT_DFLT_CFG)
+ break;
+ case ICE_AQC_REPORT_DFLT_CFG:
prefix = "phy_caps_default";
- else
+ break;
+ default:
prefix = "phy_caps_invalid";
+ }
- ice_dump_phy_type_low(hw, LE64_TO_CPU(pcaps->phy_type_low), prefix);
- ice_dump_phy_type_high(hw, LE64_TO_CPU(pcaps->phy_type_high), prefix);
+ ice_dump_phy_type(hw, LE64_TO_CPU(pcaps->phy_type_low),
+ LE64_TO_CPU(pcaps->phy_type_high), prefix);
ice_debug(hw, ICE_DBG_LINK, "%s: report_mode = 0x%x\n",
prefix, report_mode);
@@ -444,7 +478,7 @@ ice_aq_get_netlist_node(struct ice_hw *hw, struct
ice_aqc_get_link_topo *cmd,
*
* Find and return the node handle for a given node type and part number in the
* netlist. When found ICE_SUCCESS is returned, ICE_ERR_DOES_NOT_EXIST
- * otherwise. If @node_handle provided, it would be set to found node handle.
+ * otherwise. If node_handle provided, it would be set to found node handle.
*/
enum ice_status
ice_find_netlist_node(struct ice_hw *hw, u8 node_type_ctx, u8 node_part_number,
@@ -452,11 +486,12 @@ ice_find_netlist_node(struct ice_hw *hw, u8
node_type_ctx, u8 node_part_number,
{
struct ice_aqc_get_link_topo cmd;
u8 rec_node_part_number;
- enum ice_status status;
u16 rec_node_handle;
u8 idx;
for (idx = 0; idx < MAX_NETLIST_SIZE; idx++) {
+ enum ice_status status;
+
memset(&cmd, 0, sizeof(cmd));
cmd.addr.topo_params.node_type_ctx =
@@ -545,7 +580,6 @@ static enum ice_media_type ice_get_media_type(struct
ice_port_info *pi)
case ICE_PHY_TYPE_LOW_1000BASE_LX:
case ICE_PHY_TYPE_LOW_10GBASE_SR:
case ICE_PHY_TYPE_LOW_10GBASE_LR:
- case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
case ICE_PHY_TYPE_LOW_25GBASE_SR:
case ICE_PHY_TYPE_LOW_25GBASE_LR:
case ICE_PHY_TYPE_LOW_40GBASE_SR4:
@@ -602,6 +636,7 @@ static enum ice_media_type ice_get_media_type(struct
ice_port_info *pi)
case ICE_PHY_TYPE_LOW_2500BASE_X:
case ICE_PHY_TYPE_LOW_5GBASE_KR:
case ICE_PHY_TYPE_LOW_10GBASE_KR_CR1:
+ case ICE_PHY_TYPE_LOW_10G_SFI_C2C:
case ICE_PHY_TYPE_LOW_25GBASE_KR:
case ICE_PHY_TYPE_LOW_25GBASE_KR1:
case ICE_PHY_TYPE_LOW_25GBASE_KR_S:
@@ -629,6 +664,8 @@ static enum ice_media_type ice_get_media_type(struct
ice_port_info *pi)
return ICE_MEDIA_UNKNOWN;
}
+#define ice_get_link_status_datalen(hw) ICE_GET_LINK_STATUS_DATALEN_V1
+
/**
* ice_aq_get_link_info
* @pi: port information structure
@@ -668,8 +705,8 @@ ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
resp->cmd_flags = CPU_TO_LE16(cmd_flags);
resp->lport_num = pi->lport;
- status = ice_aq_send_cmd(hw, &desc, &link_data, sizeof(link_data), cd);
-
+ status = ice_aq_send_cmd(hw, &desc, &link_data,
+ ice_get_link_status_datalen(hw), cd);
*** 12050 LINES SKIPPED ***
