The branch main has been updated by mav:
URL:
https://cgit.FreeBSD.org/src/commit/?id=ae57fbc7ec65fcc75575a55c911e0da32ea9c20d
commit ae57fbc7ec65fcc75575a55c911e0da32ea9c20d
Author: Alexander Motin <m...@freebsd.org>
AuthorDate: 2022-05-31 02:51:00 +0000
Commit: Alexander Motin <m...@freebsd.org>
CommitDate: 2022-05-31 02:54:00 +0000
hwpmc: Update Intel's programmable counters restrictions.
Primarily remove unneeded restrictions from later CPUs.
MFC after: 1 month
---
sys/dev/hwpmc/hwpmc_core.c | 101 ++++++++++++++++++++++++---------------------
1 file changed, 54 insertions(+), 47 deletions(-)
diff --git a/sys/dev/hwpmc/hwpmc_core.c b/sys/dev/hwpmc/hwpmc_core.c
index 73cfee0b3975..043ca95a305f 100644
--- a/sys/dev/hwpmc/hwpmc_core.c
+++ b/sys/dev/hwpmc/hwpmc_core.c
@@ -613,20 +613,22 @@ iap_event_corei7_ok_on_counter(uint8_t evsel, int ri)
uint32_t mask;
switch (evsel) {
- /*
- * Events valid only on counter 0, 1.
- */
- case 0x40:
- case 0x41:
- case 0x42:
- case 0x43:
- case 0x51:
- case 0x63:
- mask = 0x3;
+ /* Events valid only on counter 0, 1. */
+ case 0x40:
+ case 0x41:
+ case 0x42:
+ case 0x43:
+ case 0x4C:
+ case 0x4E:
+ case 0x51:
+ case 0x52:
+ case 0x53:
+ case 0x63:
+ mask = 0x3;
break;
-
- default:
- mask = ~0; /* Any row index is ok. */
+ /* Any row index is ok. */
+ default:
+ mask = ~0;
}
return (mask & (1 << ri));
@@ -638,26 +640,23 @@ iap_event_westmere_ok_on_counter(uint8_t evsel, int ri)
uint32_t mask;
switch (evsel) {
- /*
- * Events valid only on counter 0.
- */
- case 0x60:
- case 0xB3:
+ /* Events valid only on counter 0. */
+ case 0x60:
+ case 0xB3:
mask = 0x1;
break;
- /*
- * Events valid only on counter 0, 1.
- */
- case 0x4C:
- case 0x4E:
- case 0x51:
- case 0x63:
+ /* Events valid only on counter 0, 1. */
+ case 0x4C:
+ case 0x4E:
+ case 0x51:
+ case 0x52:
+ case 0x63:
mask = 0x3;
break;
-
+ /* Any row index is ok. */
default:
- mask = ~0; /* Any row index is ok. */
+ mask = ~0;
}
return (mask & (1 << ri));
@@ -669,34 +668,35 @@ iap_event_sb_sbx_ib_ibx_ok_on_counter(uint8_t evsel, int
ri)
uint32_t mask;
switch (evsel) {
- /* Events valid only on counter 0. */
- case 0xB7:
+ /* Events valid only on counter 0. */
+ case 0xB7:
mask = 0x1;
break;
- /* Events valid only on counter 1. */
+ /* Events valid only on counter 1. */
case 0xC0:
mask = 0x2;
break;
- /* Events valid only on counter 2. */
+ /* Events valid only on counter 2. */
case 0x48:
case 0xA2:
case 0xA3:
mask = 0x4;
break;
- /* Events valid only on counter 3. */
+ /* Events valid only on counter 3. */
case 0xBB:
case 0xCD:
mask = 0x8;
break;
+ /* Any row index is ok. */
default:
- mask = ~0; /* Any row index is ok. */
+ mask = ~0;
}
return (mask & (1 << ri));
}
static int
-iap_event_ok_on_counter(uint8_t evsel, int ri)
+iap_event_core_ok_on_counter(uint8_t evsel, int ri)
{
uint32_t mask;
@@ -748,34 +748,41 @@ iap_allocate_pmc(int cpu, int ri, struct pmc *pm,
ev = IAP_EVSEL_GET(iap->pm_iap_config);
switch (core_cputype) {
+ case PMC_CPU_INTEL_CORE:
+ case PMC_CPU_INTEL_CORE2:
+ case PMC_CPU_INTEL_CORE2EXTREME:
+ if (iap_event_core_ok_on_counter(ev, ri) == 0)
+ return (EINVAL);
case PMC_CPU_INTEL_COREI7:
case PMC_CPU_INTEL_NEHALEM_EX:
if (iap_event_corei7_ok_on_counter(ev, ri) == 0)
return (EINVAL);
break;
- case PMC_CPU_INTEL_SKYLAKE:
- case PMC_CPU_INTEL_SKYLAKE_XEON:
- case PMC_CPU_INTEL_ICELAKE:
- case PMC_CPU_INTEL_ICELAKE_XEON:
- case PMC_CPU_INTEL_BROADWELL:
- case PMC_CPU_INTEL_BROADWELL_XEON:
+ case PMC_CPU_INTEL_WESTMERE:
+ case PMC_CPU_INTEL_WESTMERE_EX:
+ if (iap_event_westmere_ok_on_counter(ev, ri) == 0)
+ return (EINVAL);
+ break;
case PMC_CPU_INTEL_SANDYBRIDGE:
case PMC_CPU_INTEL_SANDYBRIDGE_XEON:
case PMC_CPU_INTEL_IVYBRIDGE:
case PMC_CPU_INTEL_IVYBRIDGE_XEON:
case PMC_CPU_INTEL_HASWELL:
case PMC_CPU_INTEL_HASWELL_XEON:
+ case PMC_CPU_INTEL_BROADWELL:
+ case PMC_CPU_INTEL_BROADWELL_XEON:
if (iap_event_sb_sbx_ib_ibx_ok_on_counter(ev, ri) == 0)
return (EINVAL);
break;
- case PMC_CPU_INTEL_WESTMERE:
- case PMC_CPU_INTEL_WESTMERE_EX:
- if (iap_event_westmere_ok_on_counter(ev, ri) == 0)
- return (EINVAL);
- break;
+ case PMC_CPU_INTEL_ATOM:
+ case PMC_CPU_INTEL_ATOM_SILVERMONT:
+ case PMC_CPU_INTEL_ATOM_GOLDMONT:
+ case PMC_CPU_INTEL_SKYLAKE:
+ case PMC_CPU_INTEL_SKYLAKE_XEON:
+ case PMC_CPU_INTEL_ICELAKE:
+ case PMC_CPU_INTEL_ICELAKE_XEON:
default:
- if (iap_event_ok_on_counter(ev, ri) == 0)
- return (EINVAL);
+ break;
}
pm->pm_md.pm_iap.pm_iap_evsel = iap->pm_iap_config;
