The branch stable/13 has been updated by andrew: URL: https://cgit.FreeBSD.org/src/commit/?id=9705371ada9b78bf314a8217c51b58270d55a472
commit 9705371ada9b78bf314a8217c51b58270d55a472 Author: Andrew Turner <[email protected]> AuthorDate: 2022-03-11 10:56:42 +0000 Commit: Andrew Turner <[email protected]> CommitDate: 2022-04-04 09:37:07 +0000 Correct the location of the arm64 PMCR register This was one of the last registers to not be in alphabetical order in armreg.h. Fix this to make it easier to find. Sponsored by: Innovate UK (cherry picked from commit a1b4e4fa9a2f8bef9adff9e93cc5152e46a2ff4e) --- sys/arm64/include/armreg.h | 55 +++++++++++++++++++++++----------------------- 1 file changed, 27 insertions(+), 28 deletions(-) diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h index 3a26c7bb5d40..dcaab1375bf8 100644 --- a/sys/arm64/include/armreg.h +++ b/sys/arm64/include/armreg.h @@ -968,6 +968,33 @@ #define PMBSR_EC_SHIFT 26 #define PMBSR_EC_MASK (UL(0x3f) << PMBSR_EC_SHIFT) +/* PMCR_EL0 - Perfomance Monitoring Counters */ +#define PMCR_E (1 << 0) /* Enable all counters */ +#define PMCR_P (1 << 1) /* Reset all counters */ +#define PMCR_C (1 << 2) /* Clock counter reset */ +#define PMCR_D (1 << 3) /* CNTR counts every 64 clk cycles */ +#define PMCR_X (1 << 4) /* Export to ext. monitoring (ETM) */ +#define PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/ +#define PMCR_LC (1 << 6) /* Long cycle count enable */ +#define PMCR_IMP_SHIFT 24 /* Implementer code */ +#define PMCR_IMP_MASK (0xff << PMCR_IMP_SHIFT) +#define PMCR_IMP_ARM 0x41 +#define PMCR_IDCODE_SHIFT 16 /* Identification code */ +#define PMCR_IDCODE_MASK (0xff << PMCR_IDCODE_SHIFT) +#define PMCR_IDCODE_CORTEX_A57 0x01 +#define PMCR_IDCODE_CORTEX_A72 0x02 +#define PMCR_IDCODE_CORTEX_A53 0x03 +#define PMCR_IDCODE_CORTEX_A73 0x04 +#define PMCR_IDCODE_CORTEX_A35 0x0a +#define PMCR_IDCODE_CORTEX_A76 0x0b +#define PMCR_IDCODE_NEOVERSE_N1 0x0c +#define PMCR_IDCODE_CORTEX_A77 0x10 +#define PMCR_IDCODE_CORTEX_A55 0x45 +#define PMCR_IDCODE_NEOVERSE_E1 0x46 +#define PMCR_IDCODE_CORTEX_A75 0x4a +#define PMCR_N_SHIFT 11 /* Number of counters implemented */ +#define PMCR_N_MASK (0x1f << PMCR_N_SHIFT) + /* PMSCR_EL1 */ #define PMSCR_EL1 MRS_REG(PMSCR_EL1) #define PMSCR_EL1_op0 0x3 @@ -1433,32 +1460,4 @@ #define TTBR_CnP_SHIFT 0 #define TTBR_CnP (1ul << TTBR_CnP_SHIFT) - -/* Perfomance Monitoring Counters */ -#define PMCR_E (1 << 0) /* Enable all counters */ -#define PMCR_P (1 << 1) /* Reset all counters */ -#define PMCR_C (1 << 2) /* Clock counter reset */ -#define PMCR_D (1 << 3) /* CNTR counts every 64 clk cycles */ -#define PMCR_X (1 << 4) /* Export to ext. monitoring (ETM) */ -#define PMCR_DP (1 << 5) /* Disable CCNT if non-invasive debug*/ -#define PMCR_LC (1 << 6) /* Long cycle count enable */ -#define PMCR_IMP_SHIFT 24 /* Implementer code */ -#define PMCR_IMP_MASK (0xff << PMCR_IMP_SHIFT) -#define PMCR_IMP_ARM 0x41 -#define PMCR_IDCODE_SHIFT 16 /* Identification code */ -#define PMCR_IDCODE_MASK (0xff << PMCR_IDCODE_SHIFT) -#define PMCR_IDCODE_CORTEX_A57 0x01 -#define PMCR_IDCODE_CORTEX_A72 0x02 -#define PMCR_IDCODE_CORTEX_A53 0x03 -#define PMCR_IDCODE_CORTEX_A73 0x04 -#define PMCR_IDCODE_CORTEX_A35 0x0a -#define PMCR_IDCODE_CORTEX_A76 0x0b -#define PMCR_IDCODE_NEOVERSE_N1 0x0c -#define PMCR_IDCODE_CORTEX_A77 0x10 -#define PMCR_IDCODE_CORTEX_A55 0x45 -#define PMCR_IDCODE_NEOVERSE_E1 0x46 -#define PMCR_IDCODE_CORTEX_A75 0x4a -#define PMCR_N_SHIFT 11 /* Number of counters implemented */ -#define PMCR_N_MASK (0x1f << PMCR_N_SHIFT) - #endif /* !_MACHINE_ARMREG_H_ */
