The branch stable/13 has been updated by mav:
URL:
https://cgit.FreeBSD.org/src/commit/?id=f8aedfec5d5b59947ca427002c4ed8920dfbf32b
commit f8aedfec5d5b59947ca427002c4ed8920dfbf32b
Author: Alexander Motin <m...@freebsd.org>
AuthorDate: 2021-11-25 01:13:38 +0000
Commit: Alexander Motin <m...@freebsd.org>
CommitDate: 2021-12-09 01:37:28 +0000
ig4: Add PCI IDs for Intel Alder Lake I2C controller.
Submitted by: Dmitry Luhtionov <dmitryluhtio...@gmail.com>
MFC after: 2 weeks
(cherry picked from commit e8e8d2290ee68ddf8753ea345d4424f959bdb69d)
---
sys/dev/ichiic/ig4_pci.c | 40 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/sys/dev/ichiic/ig4_pci.c b/sys/dev/ichiic/ig4_pci.c
index 2d80a8b1800a..71b95c3d95fb 100644
--- a/sys/dev/ichiic/ig4_pci.c
+++ b/sys/dev/ichiic/ig4_pci.c
@@ -144,6 +144,26 @@ static int ig4iic_pci_detach(device_t dev);
#define PCI_CHIP_GEMINILAKE_I2C_5 0x31b68086
#define PCI_CHIP_GEMINILAKE_I2C_6 0x31b88086
#define PCI_CHIP_GEMINILAKE_I2C_7 0x31ba8086
+#define PCI_CHIP_ALDERLAKE_P_I2C_0 0x51e88086
+#define PCI_CHIP_ALDERLAKE_P_I2C_1 0x51e98086
+#define PCI_CHIP_ALDERLAKE_P_I2C_2 0x51ea8086
+#define PCI_CHIP_ALDERLAKE_P_I2C_3 0x51eb8086
+#define PCI_CHIP_ALDERLAKE_P_I2C_4 0x51c58086
+#define PCI_CHIP_ALDERLAKE_P_I2C_5 0x51c68086
+#define PCI_CHIP_ALDERLAKE_P_I2C_6 0x51d88086
+#define PCI_CHIP_ALDERLAKE_P_I2C_7 0x51d98086
+#define PCI_CHIP_ALDERLAKE_S_I2C_0 0x7acc8086
+#define PCI_CHIP_ALDERLAKE_S_I2C_1 0x7acd8086
+#define PCI_CHIP_ALDERLAKE_S_I2C_2 0x7ace8086
+#define PCI_CHIP_ALDERLAKE_S_I2C_3 0x7acf8086
+#define PCI_CHIP_ALDERLAKE_S_I2C_4 0x7afc8086
+#define PCI_CHIP_ALDERLAKE_S_I2C_5 0x7afd8086
+#define PCI_CHIP_ALDERLAKE_M_I2C_0 0x54e88086
+#define PCI_CHIP_ALDERLAKE_M_I2C_1 0x54e98086
+#define PCI_CHIP_ALDERLAKE_M_I2C_2 0x54ea8086
+#define PCI_CHIP_ALDERLAKE_M_I2C_3 0x54eb8086
+#define PCI_CHIP_ALDERLAKE_M_I2C_4 0x54c58086
+#define PCI_CHIP_ALDERLAKE_M_I2C_5 0x54c68086
struct ig4iic_pci_device {
uint32_t devid;
@@ -230,6 +250,26 @@ static struct ig4iic_pci_device ig4iic_pci_devices[] = {
{ PCI_CHIP_GEMINILAKE_I2C_5, "Intel Gemini Lake I2C Controller-5",
IG4_GEMINILAKE},
{ PCI_CHIP_GEMINILAKE_I2C_6, "Intel Gemini Lake I2C Controller-6",
IG4_GEMINILAKE},
{ PCI_CHIP_GEMINILAKE_I2C_7, "Intel Gemini Lake I2C Controller-7",
IG4_GEMINILAKE},
+ { PCI_CHIP_ALDERLAKE_P_I2C_0, "Intel Alder Lake-P I2C Controller-0",
IG4_TIGERLAKE},
+ { PCI_CHIP_ALDERLAKE_P_I2C_1, "Intel Alder Lake-P I2C Controller-1",
IG4_TIGERLAKE},
+ { PCI_CHIP_ALDERLAKE_P_I2C_2, "Intel Alder Lake-P I2C Controller-2",
IG4_TIGERLAKE},
+ { PCI_CHIP_ALDERLAKE_P_I2C_3, "Intel Alder Lake-P I2C Controller-3",
IG4_TIGERLAKE},
+ { PCI_CHIP_ALDERLAKE_P_I2C_4, "Intel Alder Lake-P I2C Controller-4",
IG4_TIGERLAKE},
+ { PCI_CHIP_ALDERLAKE_P_I2C_5, "Intel Alder Lake-P I2C Controller-5",
IG4_TIGERLAKE},
+ { PCI_CHIP_ALDERLAKE_P_I2C_6, "Intel Alder Lake-P I2C Controller-6",
IG4_TIGERLAKE},
+ { PCI_CHIP_ALDERLAKE_P_I2C_7, "Intel Alder Lake-P I2C Controller-7",
IG4_TIGERLAKE},
+ { PCI_CHIP_ALDERLAKE_S_I2C_0, "Intel Alder Lake-S I2C Controller-0",
IG4_TIGERLAKE},
+ { PCI_CHIP_ALDERLAKE_S_I2C_1, "Intel Alder Lake-S I2C Controller-1",
IG4_TIGERLAKE},
+ { PCI_CHIP_ALDERLAKE_S_I2C_2, "Intel Alder Lake-S I2C Controller-2",
IG4_TIGERLAKE},
+ { PCI_CHIP_ALDERLAKE_S_I2C_3, "Intel Alder Lake-S I2C Controller-3",
IG4_TIGERLAKE},
+ { PCI_CHIP_ALDERLAKE_S_I2C_4, "Intel Alder Lake-S I2C Controller-4",
IG4_TIGERLAKE},
+ { PCI_CHIP_ALDERLAKE_S_I2C_5, "Intel Alder Lake-S I2C Controller-5",
IG4_TIGERLAKE},
+ { PCI_CHIP_ALDERLAKE_M_I2C_0, "Intel Alder Lake-M I2C Controller-0",
IG4_TIGERLAKE},
+ { PCI_CHIP_ALDERLAKE_M_I2C_1, "Intel Alder Lake-M I2C Controller-1",
IG4_TIGERLAKE},
+ { PCI_CHIP_ALDERLAKE_M_I2C_2, "Intel Alder Lake-M I2C Controller-2",
IG4_TIGERLAKE},
+ { PCI_CHIP_ALDERLAKE_M_I2C_3, "Intel Alder Lake-M I2C Controller-3",
IG4_TIGERLAKE},
+ { PCI_CHIP_ALDERLAKE_M_I2C_4, "Intel Alder Lake-M I2C Controller-4",
IG4_TIGERLAKE},
+ { PCI_CHIP_ALDERLAKE_M_I2C_5, "Intel Alder Lake-M I2C Controller-5",
IG4_TIGERLAKE},
};
static int
