The branch main has been updated by mhorne:
URL:
https://cgit.FreeBSD.org/src/commit/?id=b826cc3caf6abc6a5d1926bd478b464938d45697
commit b826cc3caf6abc6a5d1926bd478b464938d45697
Author: Mitchell Horne <mho...@freebsd.org>
AuthorDate: 2021-11-08 19:33:25 +0000
Commit: Mitchell Horne <mho...@freebsd.org>
CommitDate: 2021-11-08 19:33:25 +0000
hwpmc: initialize arm64 counter/interrupt state
Performance counters and overflow interrupts are assumed to be disabled
by default, but this is not guaranteed. Ensure we disable both during
per-cpu initialization, before enabling the PMU. Otherwise, some systems
(such as the Ampere eMAG) would experience an interrupt storm upon
loading the hwpmc module.
Reviewed by: br
MFC after: 5 days
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D32854
---
sys/dev/hwpmc/hwpmc_arm64.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/sys/dev/hwpmc/hwpmc_arm64.c b/sys/dev/hwpmc/hwpmc_arm64.c
index 14283b22644d..14c176894c6a 100644
--- a/sys/dev/hwpmc/hwpmc_arm64.c
+++ b/sys/dev/hwpmc/hwpmc_arm64.c
@@ -483,6 +483,16 @@ arm64_pcpu_init(struct pmc_mdep *md, int cpu)
pc->pc_hwpmcs[i + first_ri] = phw;
}
+ /*
+ * Disable all counters and overflow interrupts. Upon reset they are in
+ * an undefined state.
+ *
+ * Don't issue an isb here, just wait for the one in arm64_pmcr_write()
+ * to make the writes visible.
+ */
+ WRITE_SPECIALREG(pmcntenclr_el0, 0xffffffff);
+ WRITE_SPECIALREG(pmintenclr_el1, 0xffffffff);
+
/* Enable unit */
pmcr = arm64_pmcr_read();
pmcr |= PMCR_E;
