The branch main has been updated by mw:
URL:
https://cgit.FreeBSD.org/src/commit/?id=e245ee2774b3e1d8b1462866a4084cc3e5a806a8
commit e245ee2774b3e1d8b1462866a4084cc3e5a806a8
Author: Marcin Wojtas <m...@freebsd.org>
AuthorDate: 2021-04-29 09:39:09 +0000
Commit: Marcin Wojtas <m...@freebsd.org>
CommitDate: 2021-04-30 22:58:26 +0000
gicv3_its: Flush cache after allocating ITT memory
It has to be zeroed before committing it to device.
We do that by allocating it with M_ZERO, but there was no
memory barrier or cache flush to ensure its sees it zeroed.
This fixes MSIX on LS1028A SoC.
Submitted by: Kornel Duleba <min...@semihalf.com>
Reviewed by: andrew
Obtained from: Semihalf
Sponsored by: Alstom Group
Differential Revision: https://reviews.freebsd.org/D30033
---
sys/arm64/arm64/gicv3_its.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/sys/arm64/arm64/gicv3_its.c b/sys/arm64/arm64/gicv3_its.c
index 11cf05b04cfe..8ba7aa3b2047 100644
--- a/sys/arm64/arm64/gicv3_its.c
+++ b/sys/arm64/arm64/gicv3_its.c
@@ -1197,6 +1197,10 @@ its_device_get(device_t dev, device_t child, u_int nvecs)
return (NULL);
}
+ /* Make sure device sees zeroed ITT. */
+ if ((sc->sc_its_flags & ITS_FLAGS_CMDQ_FLUSH) != 0)
+ cpu_dcache_wb_range(its_dev->itt, its_dev->itt_size);
+
mtx_lock_spin(&sc->sc_its_dev_lock);
TAILQ_INSERT_TAIL(&sc->sc_its_dev_list, its_dev, entry);
mtx_unlock_spin(&sc->sc_its_dev_lock);
_______________________________________________
dev-commits-src-all@freebsd.org mailing list
https://lists.freebsd.org/mailman/listinfo/dev-commits-src-all
To unsubscribe, send any mail to "dev-commits-src-all-unsubscr...@freebsd.org"
