NEWS | 51 +
configure.ac | 7
man/Makefile.am | 41
src/Makefile.am | 11
src/bios_reader/.gitignore | 4
src/bios_reader/Makefile.am | 16
src/bios_reader/bios_dumper.c | 107 --
src/bios_reader/bios_reader.c | 587 --------------
src/bios_reader/swf_dumper.c | 112 --
src/common.h | 40
src/drmmode_display.c | 347 ++++----
src/i810_driver.c | 26
src/i810_video.c | 5
src/i830.h | 79 -
src/i830_accel.c | 1
src/i830_batchbuffer.c | 24
src/i830_batchbuffer.h | 15
src/i830_bios.c | 394 ---------
src/i830_bios.h | 631 ---------------
src/i830_common.h | 236 -----
src/i830_display.h | 42 -
src/i830_dri.c | 631 ++++++++++++++-
src/i830_dri.h | 61 -
src/i830_driver.c | 185 ----
src/i830_hwmc.c | 36
src/i830_hwmc.h | 8
src/i830_memory.c | 418 ----------
src/i830_render.c | 1
src/i830_ring.h | 93 --
src/i830_uxa.c | 47 -
src/i830_video.c | 432 +++++-----
src/i830_video.h | 3
src/i915_hwmc.c | 609 --------------
src/i915_hwmc.h | 12
src/i915_video.c | 2
src/i965_hwmc.c | 2
src/i965_hwmc.h | 12
src/i965_render.c | 37
src/i965_video.c | 3
src/reg_dumper/.gitignore | 7
src/reg_dumper/Makefile.am | 41
src/reg_dumper/audio.c | 460 -----------
src/reg_dumper/gtt.c | 117 --
src/reg_dumper/hotplug.c | 126 ---
src/reg_dumper/lid.c | 146 ---
src/reg_dumper/main.c | 109 --
src/reg_dumper/reg_dumper.h | 87 --
src/reg_dumper/statuspage.c | 84 --
src/reg_dumper/util.c | 85 --
src/reg_dumper/xprintf.c | 58 -
src/xvmc/i915_structs.h | 121 --
src/xvmc/i915_xvmc.c | 1751 ++++++------------------------------------
src/xvmc/i915_xvmc.h | 20
src/xvmc/i965_xvmc.c | 12
src/xvmc/intel_batchbuffer.c | 58 -
src/xvmc/intel_xvmc.c | 2
src/xvmc/intel_xvmc.h | 5
src/xvmc/xvmc_vld.c | 20
uxa/uxa-accel.c | 2
uxa/uxa-glyphs.c | 6
uxa/uxa-render.c | 242 +++--
61 files changed, 1820 insertions(+), 7107 deletions(-)
New commits:
commit 753914acc31947df8e9f2fa3b9c39de745098709
Author: Carl Worth <cwo...@cworth.org>
Date: Mon Mar 15 17:32:57 2010 -0700
Bump version to 2.10.902
For the imminent 2.10.902 snapshot release.
diff --git a/configure.ac b/configure.ac
index 17f3725..3877064 100644
--- a/configure.ac
+++ b/configure.ac
@@ -22,7 +22,7 @@
AC_PREREQ(2.57)
AC_INIT([xf86-video-intel],
- 2.10.901,
+ 2.10.902,
[https://bugs.freedesktop.org/enter_bug.cgi?product=xorg],
xf86-video-intel)
commit 185196cb010cb8426ca929a9dc3f028ec9b383db
Author: Carl Worth <cwo...@cworth.org>
Date: Mon Mar 15 17:32:20 2010 -0700
NEWS: Add notes for the 2.10.902 snapshot.
Which I'm about to push out.
diff --git a/NEWS b/NEWS
index 39d5567..ee18bd2 100644
--- a/NEWS
+++ b/NEWS
@@ -1,3 +1,30 @@
+Snapshot 2.10.902 (2010-03-15)
+==============================
+Some significant bug fixes
+--------------------------
+Fix video color problems due to YUV plane ordering issue. This fixed a
+regression that showed up recently (only in these release candidates).
+
+Fix recent regression leading to corruption under compiz:
+
+ https://bugs.freedesktop.org/show_bug.cgi?id=26814
+
+Further DRI2 improvements/fixes from Mario Kleiner and Jesse Barnes,
+(including support for SwapBuffers request with divisor != 0).
+
+Fix build against X server 1.6 branch.
+
+Avoid flooding logs after an error occurs.
+
+And dramatic code cleanups
+--------------------------
+Eric Anholt removed several cases of old, useless code, (conditions
+that could not occur now that we require KMS, etc.).
+
+Daniel Vetter eliminated piles of code by modernizing the XvMC
+memory-management and completely removing the old i830_memory
+allocator (i830_allocate_memory, i830_free_memory), etc.
+
Snapshot 2.10.901 (2010-02-26)
==============================
The most significant new feature of this release is support for new
commit 318aa9ed799197810e2039dbe3ec51559dcc888c
Author: Daniel Vetter <daniel.vet...@ffwll.ch>
Date: Mon Mar 8 23:22:53 2010 +0100
i915 XvMC: fixup colors
My cleanup accidently created a inconsistency in the YUV plane ordering.
I think we can safely assume that I'm colorblind ;)
As Carl Worth rightly pointed out, this change deserves a more elaborate
explanation:
For Xv planar formats, the three planes are stored consecutively in
memory, ordered Y U V. Now for some totally odd reason (= none at all),
i915 xvmc stored it in Y V U order. Right after the release of 2.10, with
commit "Xv: consolidate xmvc passthrough handling" I've inadvertently
broken xvmc support (which started this whole odyssey into xvmc). When
fixing stuff up, I neglected this special plane ordering and simply
assumed it to be the same as Xv and dropped that special case for i915 in
src/i830_video.c. This patch completes the change to standard YUV plane
ordering by making the corresponding change in src/xvmc/i915_xvmc.c.
Signed-off-by: Daniel Vetter <daniel.vet...@ffwll.ch>
diff --git a/src/xvmc/i915_xvmc.c b/src/xvmc/i915_xvmc.c
index 190b736..0888d63 100644
--- a/src/xvmc/i915_xvmc.c
+++ b/src/xvmc/i915_xvmc.c
@@ -31,9 +31,9 @@
#include "i915_structs.h"
#include "i915_program.h"
-#define UOFFSET(surface) (SIZE_Y420(surface->width, surface->height) + \
+#define UOFFSET(surface) (SIZE_Y420(surface->width, surface->height))
+#define VOFFSET(surface) (SIZE_Y420(surface->width, surface->height) + \
SIZE_UV420(surface->width, surface->height))
-#define VOFFSET(surface) (SIZE_Y420(surface->width, surface->height))
typedef union {
int16_t component[2];
commit 68629b63740fb6e62c258b8a46669e77660fa4e4
Author: Jesse Barnes <jbar...@virtuousgeek.org>
Date: Mon Mar 8 15:42:39 2010 -0800
DRI2: make WaitMSC error handling more consistent with ScheduleSwap
Just make it mirror ScheduleSwap: complete the wait on any error
condition so as not to crash the client if the kernel is misbehaving.
Signed-off-by: Jesse Barnes <jbar...@virtuousgeek.org>
diff --git a/src/i830_dri.c b/src/i830_dri.c
index fc17807..7c595dd 100644
--- a/src/i830_dri.c
+++ b/src/i830_dri.c
@@ -862,16 +862,12 @@ I830DRI2ScheduleWaitMSC(ClientPtr client, DrawablePtr
draw, CARD64 target_msc,
remainder &= 0xffffffff;
/* Drawable not visible, return immediately */
- if (pipe == -1) {
- DRI2WaitMSCComplete(client, draw, target_msc, 0, 0);
- return TRUE;
- }
+ if (pipe == -1)
+ goto out_complete;
wait_info = xcalloc(1, sizeof(DRI2FrameEventRec));
- if (!wait_info) {
- DRI2WaitMSCComplete(client, draw, 0, 0, 0);
- return TRUE;
- }
+ if (!wait_info)
+ goto out_complete;
wait_info->drawable_id = draw->id;
wait_info->client = client;
@@ -886,7 +882,7 @@ I830DRI2ScheduleWaitMSC(ClientPtr client, DrawablePtr draw,
CARD64 target_msc,
if (ret) {
xf86DrvMsg(scrn->scrnIndex, X_WARNING,
"get vblank counter failed: %s\n", strerror(errno));
- return FALSE;
+ goto out_complete;
}
current_msc = vbl.reply.sequence;
@@ -914,7 +910,7 @@ I830DRI2ScheduleWaitMSC(ClientPtr client, DrawablePtr draw,
CARD64 target_msc,
if (ret) {
xf86DrvMsg(scrn->scrnIndex, X_WARNING,
"get vblank counter failed: %s\n",
strerror(errno));
- return FALSE;
+ goto out_complete;
}
wait_info->frame = vbl.reply.sequence;
@@ -947,13 +943,17 @@ I830DRI2ScheduleWaitMSC(ClientPtr client, DrawablePtr
draw, CARD64 target_msc,
if (ret) {
xf86DrvMsg(scrn->scrnIndex, X_WARNING,
"get vblank counter failed: %s\n", strerror(errno));
- return FALSE;
+ goto out_complete;
}
wait_info->frame = vbl.reply.sequence;
DRI2BlockClient(client, draw);
return TRUE;
+
+out_complete:
+ DRI2WaitMSCComplete(client, draw, target_msc, 0, 0);
+ return TRUE;
}
#endif
commit 6df74e61afb7831ebf3fbab8782f46ddccbe262b
Author: Jesse Barnes <jbar...@virtuousgeek.org>
Date: Mon Mar 8 15:33:20 2010 -0800
DRI2: truncate OML values to 32 bits
We can only handle 32 bit values unless we totally virtualize the count,
since the kernel only handles 32 bits itself. Rather than adding all
that overhead, just tolerate the occasional missed event everytime the
counter runs over.
Reported-by: Mario Kleiner <mario.klei...@tuebingen.mpg.de>
Signed-off-by: Jesse Barnes <jbar...@virtuousgeek.org>
diff --git a/src/i830_dri.c b/src/i830_dri.c
index e8f2424..fc17807 100644
--- a/src/i830_dri.c
+++ b/src/i830_dri.c
@@ -645,6 +645,12 @@ I830DRI2ScheduleSwap(ClientPtr client, DrawablePtr draw,
DRI2BufferPtr front,
BoxRec box;
RegionRec region;
+ /* Truncate to match kernel interfaces; means occasional overflow
+ * misses, but that's generally not a big deal */
+ *target_msc &= 0xffffffff;
+ divisor &= 0xffffffff;
+ remainder &= 0xffffffff;
+
swap_info = xcalloc(1, sizeof(DRI2FrameEventRec));
/* Drawable not displayed... just complete the swap */
@@ -849,6 +855,12 @@ I830DRI2ScheduleWaitMSC(ClientPtr client, DrawablePtr
draw, CARD64 target_msc,
int ret, pipe = I830DRI2DrawablePipe(draw);
CARD64 current_msc;
+ /* Truncate to match kernel interfaces; means occasional overflow
+ * misses, but that's generally not a big deal */
+ target_msc &= 0xffffffff;
+ divisor &= 0xffffffff;
+ remainder &= 0xffffffff;
+
/* Drawable not visible, return immediately */
if (pipe == -1) {
DRI2WaitMSCComplete(client, draw, target_msc, 0, 0);
commit c66d57080dc034aa7877f47612065e388bbc38a2
Author: Jesse Barnes <jbar...@virtuousgeek.org>
Date: Mon Mar 8 15:26:24 2010 -0800
DRI2: more WaitMSC fixes
A couple more niggles: make sure we return a target_msc that at least
matches the current count; this is a little more friendly to clients
that missed an event. Also check for >= when calculating the remainder
so we'll catch the *next* vblank event when the calculation is
satisfied, rather than the current one as might happen at times.
Reported-by: Mario Kleiner <mario.klei...@tuebingen.mpg.de>
Signed-off-by: Jesse Barnes <jbar...@virtuousgeek.org>
diff --git a/src/i830_dri.c b/src/i830_dri.c
index a81eada..e8f2424 100644
--- a/src/i830_dri.c
+++ b/src/i830_dri.c
@@ -885,6 +885,14 @@ I830DRI2ScheduleWaitMSC(ClientPtr client, DrawablePtr
draw, CARD64 target_msc,
* client.
*/
if (divisor == 0 || current_msc < target_msc) {
+ /* If target_msc already reached or passed, set it to
+ * current_msc to ensure we return a reasonable value back
+ * to the caller. This keeps the client from continually
+ * sending us MSC targets from the past by forcibly updating
+ * their count on this call.
+ */
+ if (current_msc >= target_msc)
+ target_msc = current_msc;
vbl.request.type = DRM_VBLANK_ABSOLUTE | DRM_VBLANK_EVENT;
if (pipe > 0)
vbl.request.type |= DRM_VBLANK_SECONDARY;
@@ -919,7 +927,7 @@ I830DRI2ScheduleWaitMSC(ClientPtr client, DrawablePtr draw,
CARD64 target_msc,
* seq % divisor == remainder, so we need to wait for the next time
* that will happen.
*/
- if ((current_msc % divisor) > remainder)
+ if ((current_msc % divisor) >= remainder)
vbl.request.sequence += divisor;
vbl.request.signal = (unsigned long)wait_info;
commit 7845c6ade82085488192bd76729d92fb7b534cc0
Author: Jesse Barnes <jbar...@virtuousgeek.org>
Date: Mon Mar 8 15:19:14 2010 -0800
DRI2: fixup stray curly brace
Got left in the wrong column after the last cleanup.
Signed-off-by: Jesse Barnes <jbar...@virtuousgeek.org>
diff --git a/src/i830_dri.c b/src/i830_dri.c
index 88e9d90..a81eada 100644
--- a/src/i830_dri.c
+++ b/src/i830_dri.c
@@ -553,7 +553,7 @@ void I830DRI2FrameEventHandler(unsigned int frame, unsigned
int tv_sec,
I830DRI2CopyRegion(drawable,
®ion, event->front, event->back);
swap_type = DRI2_BLIT_COMPLETE;
- }
+ }
DRI2SwapComplete(event->client, drawable, frame, tv_sec,
tv_usec,
swap_type,
event->event_complete, event->event_data);
commit 9656d329e4df28cfe138b657d04e5136bc794ce2
Author: Eric Anholt <e...@anholt.net>
Date: Mon Mar 8 14:34:04 2010 -0800
Put back the pitch alignment for new framebuffers.
I confused a dead assignment with dead code, because one of the args
to the function was an outvalue. Fixes corruption under compiz.
Bug #26814.
diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index 22c967a..ae200ca 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -1262,6 +1262,7 @@ drmmode_xf86crtc_resize (ScrnInfoPtr scrn, int width, int
height)
return TRUE;
pitch = i830_pad_drawable_width(width, intel->cpp);
+ i830_tiled_width(intel, &pitch, intel->cpp);
xf86DrvMsg(scrn->scrnIndex, X_INFO,
"Allocate new frame buffer %dx%d stride %d\n",
width, height, pitch);
commit b71ca26a026a356763c51c763bcdd8024fc4a783
Author: Jesse Barnes <jbar...@virtuousgeek.org>
Date: Mon Mar 8 11:27:42 2010 -0800
DRI2: fixup ScheduleWaitMSC similarly to ScheduleSwap
My merge of Mario's patch for this was botched. Fix it up so that OML
waits work correctly, and remove a bogus warning from ScheduleSwap.
Reported-by: Mario Kleiner <mario.klei...@tuebingen.mpg.de>
Signed-off-by: Jesse Barnes <jbar...@virtuousgeek.org>
diff --git a/src/i830_dri.c b/src/i830_dri.c
index 96d41e7..88e9d90 100644
--- a/src/i830_dri.c
+++ b/src/i830_dri.c
@@ -689,13 +689,6 @@ I830DRI2ScheduleSwap(ClientPtr client, DrawablePtr draw,
DRI2BufferPtr front,
if (*target_msc > 0)
*target_msc -= flip;
- if ((*target_msc != 1) && (*target_msc > vbl.reply.sequence) &&
- ((*target_msc - vbl.reply.sequence) > 100))
- xf86DrvMsg(scrn->scrnIndex, X_WARNING,
- "vblank event >100 frames away: cur %ld, target %ld\n",
- (unsigned long)vbl.reply.sequence,
- (unsigned long)*target_msc);
-
/*
* If divisor is zero, or current_msc is smaller than target_msc
* we just need to make sure target_msc passes before initiating
@@ -891,7 +884,7 @@ I830DRI2ScheduleWaitMSC(ClientPtr client, DrawablePtr draw,
CARD64 target_msc,
* we just need to make sure target_msc passes before waking up the
* client.
*/
- if (divisor == 0) {
+ if (divisor == 0 || current_msc < target_msc) {
vbl.request.type = DRM_VBLANK_ABSOLUTE | DRM_VBLANK_EVENT;
if (pipe > 0)
vbl.request.type |= DRM_VBLANK_SECONDARY;
@@ -917,13 +910,17 @@ I830DRI2ScheduleWaitMSC(ClientPtr client, DrawablePtr
draw, CARD64 target_msc,
if (pipe > 0)
vbl.request.type |= DRM_VBLANK_SECONDARY;
+ vbl.request.sequence = current_msc - (current_msc % divisor) +
+ remainder;
+
/*
- * If the calculated remainder and the condition isn't satisified, it
- * means we've passed the last point where seq % divisor == remainder,
- * so we need to wait for the next time that will happen.
+ * If calculated remainder is larger than requested remainder,
+ * it means we've passed the last point where
+ * seq % divisor == remainder, so we need to wait for the next time
+ * that will happen.
*/
- if ((current_msc % divisor) != remainder)
- vbl.request.sequence += divisor;
+ if ((current_msc % divisor) > remainder)
+ vbl.request.sequence += divisor;
vbl.request.signal = (unsigned long)wait_info;
ret = drmWaitVBlank(intel->drmSubFD, &vbl);
commit 06b54e089eb21736e6d4f6462bbfca987be0c5cc
Author: Matt Turner <matts...@gmail.com>
Date: Sun Mar 7 14:27:27 2010 -0500
Don't check for Xinerama.
It doesn't seem to be used anywhere, so don't require it.
CC: Eric Anholt <e...@anholt.net>
CC: Jesse Barnes <jbar...@virtuousgeek.org>
Signed-off-by: Matt Turner <matts...@gmail.com>
diff --git a/configure.ac b/configure.ac
index 3d58aec..17f3725 100644
--- a/configure.ac
+++ b/configure.ac
@@ -82,7 +82,6 @@ AC_ARG_ENABLE(kms-only, AC_HELP_STRING([--enable-kms-only],
[KMS_ONLY=no])
# Checks for extensions
-XORG_DRIVER_CHECK_EXT(XINERAMA, xineramaproto)
XORG_DRIVER_CHECK_EXT(RANDR, randrproto)
XORG_DRIVER_CHECK_EXT(RENDER, renderproto)
XORG_DRIVER_CHECK_EXT(XF86DRI, xextproto x11)
commit 8ece6cf5afa1bb0d8d9328696422f42f3c3adbd6
Author: Robert Hooker <sarv...@ubuntu.com>
Date: Sat Mar 6 14:09:12 2010 -0500
Fix build against xserver 1.6 branch.
Signed-off-by: Robert Hooker <sarv...@ubuntu.com>
Reviewed-by: Chris Wilson <ch...@chris-wilson.co.uk>
diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index b1531bd..22c967a 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -701,7 +701,11 @@ drmmode_output_lvds_edid(xf86OutputPtr output,
DisplayModePtr modes)
max_vrefresh = max(max_vrefresh, 60.0);
max_vrefresh *= (1 + SYNC_TOLERANCE);
+#if XORG_VERSION_CURRENT >= XORG_VERSION_NUMERIC(1,6,99,0,0)
m = xf86GetDefaultModes();
+#else
+ m = xf86GetDefaultModes(0,0);
+#endif
xf86ValidateModesSize(output->scrn, m, max_x, max_y, 0);
commit 1cd556420277f103c47ade422f3ec8f8efb2d282
Author: Mario Kleiner <mario.klei...@tuebingen.mpg.de>
Date: Fri Mar 5 12:32:18 2010 -0800
DRI2: handle target_msc, divisor and remainder properly in DRI2ScheduleSwap
The current code in I830DRI2ScheduleSwap() only schedules the correct
vblank events for the case divisor == 0, i.e., the simple
glXSwapBuffers() case.
In a glXSwapBuffersMscOML() request, divisor can be > 0, which would go
wrong.
This modified code should handle target_msc, divisor, remainder and the
different cases defined in the OML_sync_control extension correctly for
the divisor > 0 case.
It also tries to make sure that the effective framecount of swap
satisfies all constraints, taking the 1 frame delay in pageflipping mode
and possible delays in blitting/exchange mode due to
DRM_VBLANK_NEXTONMISS into account.
The swap_interval logic in the X-Servers DRI2SwapBuffers() call expects
the returned swap_target from the DDX to be reasonably accurate,
otherwise implementation of swap_interval for the glXSwapBuffers() as
defined in the SGI_swap_interval extension may become unreliable.
For non-pageflipped mode, the returned swap_target is always correct due
to the adjustments done by drmWaitVBlank(), as DRM_VBLANK_NEXTONMISS is
set.
In pageflipped mode, DRM_VBLANK_NEXTONMISS can't be used without severe
impact on performance, so the code in I830DRI2ScheduleSwap() must make
manual adjustments to the returned vbl.reply.sequence number.
This patch adds the needed adjustments.
Signed-off-by: Mario Kleiner <mario.klei...@tuebingen.mpg.de>
diff --git a/src/i830_dri.c b/src/i830_dri.c
index 002f119..96d41e7 100644
--- a/src/i830_dri.c
+++ b/src/i830_dri.c
@@ -641,6 +641,7 @@ I830DRI2ScheduleSwap(ClientPtr client, DrawablePtr draw,
DRI2BufferPtr front,
int ret, pipe = I830DRI2DrawablePipe(draw), flip = 0;
DRI2FrameEventPtr swap_info;
enum DRI2FrameEventType swap_type = DRI2_SWAP;
+ CARD64 current_msc;
BoxRec box;
RegionRec region;
@@ -670,6 +671,8 @@ I830DRI2ScheduleSwap(ClientPtr client, DrawablePtr draw,
DRI2BufferPtr front,
goto blit_fallback;
}
+ current_msc = vbl.reply.sequence;
+
/* Flips need to be submitted one frame before */
if (DRI2CanFlip(draw) && !intel->shadow_present &&
intel->use_pageflipping) {
@@ -679,6 +682,13 @@ I830DRI2ScheduleSwap(ClientPtr client, DrawablePtr draw,
DRI2BufferPtr front,
swap_info->type = swap_type;
+ /* Correct target_msc by 'flip' if swap_type == DRI2_FLIP.
+ * Do it early, so handling of different timing constraints
+ * for divisor, remainder and msc vs. target_msc works.
+ */
+ if (*target_msc > 0)
+ *target_msc -= flip;
+
if ((*target_msc != 1) && (*target_msc > vbl.reply.sequence) &&
((*target_msc - vbl.reply.sequence) > 100))
xf86DrvMsg(scrn->scrnIndex, X_WARNING,
@@ -687,17 +697,32 @@ I830DRI2ScheduleSwap(ClientPtr client, DrawablePtr draw,
DRI2BufferPtr front,
(unsigned long)*target_msc);
/*
- * If divisor is zero, we just need to make sure target_msc passes
- * before waking up the client.
+ * If divisor is zero, or current_msc is smaller than target_msc
+ * we just need to make sure target_msc passes before initiating
+ * the swap.
*/
- if (divisor == 0) {
- vbl.request.type = DRM_VBLANK_NEXTONMISS |
- DRM_VBLANK_ABSOLUTE | DRM_VBLANK_EVENT;
+ if (divisor == 0 || current_msc < *target_msc) {
+ vbl.request.type = DRM_VBLANK_ABSOLUTE | DRM_VBLANK_EVENT;
if (pipe > 0)
vbl.request.type |= DRM_VBLANK_SECONDARY;
+ /* If non-pageflipping, but blitting/exchanging, we need to use
+ * DRM_VBLANK_NEXTONMISS to avoid unreliable timestamping later
+ * on.
+ */
+ if (flip == 0)
+ vbl.request.type |= DRM_VBLANK_NEXTONMISS;
+ if (pipe > 0)
+ vbl.request.type |= DRM_VBLANK_SECONDARY;
+
+ /* If target_msc already reached or passed, set it to
+ * current_msc to ensure we return a reasonable value back
+ * to the caller. This makes swap_interval logic more robust.
+ */
+ if (current_msc >= *target_msc)
+ *target_msc = current_msc;
+
vbl.request.sequence = *target_msc;
- vbl.request.sequence -= flip;
vbl.request.signal = (unsigned long)swap_info;
ret = drmWaitVBlank(intel->drmSubFD, &vbl);
if (ret) {
@@ -707,7 +732,7 @@ I830DRI2ScheduleSwap(ClientPtr client, DrawablePtr draw,
DRI2BufferPtr front,
goto blit_fallback;
}
- *target_msc = vbl.reply.sequence;
+ *target_msc = vbl.reply.sequence + flip;
swap_info->frame = *target_msc;
return TRUE;
@@ -715,42 +740,35 @@ I830DRI2ScheduleSwap(ClientPtr client, DrawablePtr draw,
DRI2BufferPtr front,
/*
* If we get here, target_msc has already passed or we don't have one,
- * so we queue an event that will satisfy the divisor/remainderequation.
+ * and we need to queue an event that will satisfy the divisor/remainder
+ * equation.
*/
- if ((vbl.reply.sequence % divisor) == remainder) {
- BoxRec box;
- RegionRec region;
-
- box.x1 = 0;
- box.y1 = 0;
- box.x2 = draw->width;
- box.y2 = draw->height;
- REGION_INIT(pScreen, ®ion, &box, 0);
-
- I830DRI2CopyRegion(draw, ®ion, front, back);
-
- DRI2SwapComplete(client, draw, 0, 0, 0,
- DRI2_BLIT_COMPLETE, func, data);
- if (swap_info)
- xfree(swap_info);
- return TRUE;
- }
-
vbl.request.type = DRM_VBLANK_ABSOLUTE | DRM_VBLANK_EVENT;
+ if (flip == 0)
+ vbl.request.type |= DRM_VBLANK_NEXTONMISS;
if (pipe > 0)
vbl.request.type |= DRM_VBLANK_SECONDARY;
+ vbl.request.sequence = current_msc - (current_msc % divisor) +
+ remainder;
+
/*
- * If we have no remainder, and the test above failed, it means we've
- * passed the last point where seq % divisor == remainder, so we need
- * to wait for the next time that will happen.
+ * If the calculated deadline vbl.request.sequence is smaller than
+ * or equal to current_msc, it means we've passed the last point
+ * when effective onset frame seq could satisfy
+ * seq % divisor == remainder, so we need to wait for the next time
+ * this will happen.
+
+ * This comparison takes the 1 frame swap delay in pageflipping mode
+ * into account, as well as a potential DRM_VBLANK_NEXTONMISS delay
+ * if we are blitting/exchanging instead of flipping.
*/
- if (!remainder)
+ if (vbl.request.sequence <= current_msc)
vbl.request.sequence += divisor;
- vbl.request.sequence = vbl.reply.sequence -
- (vbl.reply.sequence % divisor) + remainder;
+ /* Account for 1 frame extra pageflip delay if flip > 0 */
vbl.request.sequence -= flip;
+
vbl.request.signal = (unsigned long)swap_info;
ret = drmWaitVBlank(intel->drmSubFD, &vbl);
if (ret) {
@@ -760,7 +778,8 @@ I830DRI2ScheduleSwap(ClientPtr client, DrawablePtr draw,
DRI2BufferPtr front,
goto blit_fallback;
}
- *target_msc = vbl.reply.sequence;
+ /* Adjust returned value for 1 fame pageflip offset of flip > 0 */
+ *target_msc = vbl.reply.sequence + flip;
swap_info->frame = *target_msc;
return TRUE;
commit 13119ffc034a3e9d6c76339d4fedc62bb3b41257
Author: Mario Kleiner <mario.klei...@tuebingen.mpg.de>
Date: Fri Mar 5 11:33:45 2010 -0800
DRI2: make MSC waits handle specific target_mscs and divisor/remainders
Previous code only handled divisor == 0 case correctly. This should
honor a given target_msc for the divisor > 0 case and handle the
(msc % divisor) == remainder constraint correctly.
Signed-off-by: Mario Kleiner <mario.klei...@tuebingen.mpg.de>
diff --git a/src/i830_dri.c b/src/i830_dri.c
index 0738cdb..002f119 100644
--- a/src/i830_dri.c
+++ b/src/i830_dri.c
@@ -835,6 +835,7 @@ I830DRI2ScheduleWaitMSC(ClientPtr client, DrawablePtr draw,
CARD64 target_msc,
DRI2FrameEventPtr wait_info;
drmVBlank vbl;
int ret, pipe = I830DRI2DrawablePipe(draw);
+ CARD64 current_msc;
/* Drawable not visible, return immediately */
if (pipe == -1) {
@@ -864,9 +865,12 @@ I830DRI2ScheduleWaitMSC(ClientPtr client, DrawablePtr
draw, CARD64 target_msc,
return FALSE;
}
+ current_msc = vbl.reply.sequence;
+
/*
- * If divisor is zero, we just need to make sure target_msc passes
- * before waking up the client.
+ * If divisor is zero, or current_msc is smaller than target_msc,
+ * we just need to make sure target_msc passes before waking up the
+ * client.
*/
if (divisor == 0) {
vbl.request.type = DRM_VBLANK_ABSOLUTE | DRM_VBLANK_EVENT;
@@ -895,15 +899,13 @@ I830DRI2ScheduleWaitMSC(ClientPtr client, DrawablePtr
draw, CARD64 target_msc,
vbl.request.type |= DRM_VBLANK_SECONDARY;
/*
- * If we have no remainder and the condition isn't satisified, it means
- * we've passed the last point where seq % divisor == remainder, so we
need
- * to wait for the next time that will happen.
+ * If the calculated remainder and the condition isn't satisified, it
+ * means we've passed the last point where seq % divisor == remainder,
+ * so we need to wait for the next time that will happen.
*/
- if (((vbl.reply.sequence % divisor) != remainder) && !remainder)
+ if ((current_msc % divisor) != remainder)
vbl.request.sequence += divisor;
- vbl.request.sequence = vbl.reply.sequence - (vbl.reply.sequence %
divisor) +
- remainder;
vbl.request.signal = (unsigned long)wait_info;
ret = drmWaitVBlank(intel->drmSubFD, &vbl);
if (ret) {
commit b6e0b92f398823629ba8a1ea8f5e62fbf959e725
Author: Jesse Barnes <jbar...@virtuousgeek.org>
Date: Thu Mar 4 10:07:26 2010 -0800
DRI2: handle offscreen drawables better at swap time
If a drawable isn't visible due to DPMS or redirection, we'll just blit
it rather than schedule a swap event. However, we didn't reset the
target_msc, so the swap target we receive from the server could get out
of sync with the vblank count of the drawable's display. So at DPMS on
time, the swap target would be the last good vblank count plus some
large number (since the swaps won't have been throttled).
Solve this by zeroing out the swap target like we should when we fall
back to a blit. Also make the kernel error cases more friendly by
making them fall back to blits too.
Signed-off-by: Jesse Barnes <jbar...@virtuousgeek.org>
diff --git a/src/i830_dri.c b/src/i830_dri.c
index 64aeb76..0738cdb 100644
--- a/src/i830_dri.c
+++ b/src/i830_dri.c
@@ -641,28 +641,14 @@ I830DRI2ScheduleSwap(ClientPtr client, DrawablePtr draw,
DRI2BufferPtr front,
int ret, pipe = I830DRI2DrawablePipe(draw), flip = 0;
DRI2FrameEventPtr swap_info;
enum DRI2FrameEventType swap_type = DRI2_SWAP;
+ BoxRec box;
+ RegionRec region;
swap_info = xcalloc(1, sizeof(DRI2FrameEventRec));
/* Drawable not displayed... just complete the swap */
- if (pipe == -1 || !swap_info) {
- BoxRec box;
- RegionRec region;
-
- box.x1 = 0;
- box.y1 = 0;
- box.x2 = draw->width;
- box.y2 = draw->height;
- REGION_INIT(pScreen, ®ion, &box, 0);
-
- I830DRI2CopyRegion(draw, ®ion, front, back);
-
- DRI2SwapComplete(client, draw, 0, 0, 0, DRI2_BLIT_COMPLETE, func,
- data);
- if (swap_info)
- xfree(swap_info);
- return TRUE;
- }
+ if (pipe == -1 || !swap_info)
+ goto blit_fallback;
swap_info->drawable_id = draw->id;
swap_info->client = client;
@@ -681,7 +667,7 @@ I830DRI2ScheduleSwap(ClientPtr client, DrawablePtr draw,
DRI2BufferPtr front,
xf86DrvMsg(scrn->scrnIndex, X_WARNING,
"first get vblank counter failed: %s\n",
strerror(errno));
- return FALSE;
+ goto blit_fallback;
}
/* Flips need to be submitted one frame before */
@@ -693,6 +679,13 @@ I830DRI2ScheduleSwap(ClientPtr client, DrawablePtr draw,
DRI2BufferPtr front,
swap_info->type = swap_type;
+ if ((*target_msc != 1) && (*target_msc > vbl.reply.sequence) &&
+ ((*target_msc - vbl.reply.sequence) > 100))
+ xf86DrvMsg(scrn->scrnIndex, X_WARNING,
+ "vblank event >100 frames away: cur %ld, target %ld\n",
+ (unsigned long)vbl.reply.sequence,
+ (unsigned long)*target_msc);
+
/*
* If divisor is zero, we just need to make sure target_msc passes
* before waking up the client.
@@ -711,7 +704,7 @@ I830DRI2ScheduleSwap(ClientPtr client, DrawablePtr draw,
DRI2BufferPtr front,
xf86DrvMsg(scrn->scrnIndex, X_WARNING,
"divisor 0 get vblank counter failed: %s\n",
strerror(errno));
- return FALSE;
+ goto blit_fallback;
}
*target_msc = vbl.reply.sequence;
@@ -764,13 +757,28 @@ I830DRI2ScheduleSwap(ClientPtr client, DrawablePtr draw,
DRI2BufferPtr front,
xf86DrvMsg(scrn->scrnIndex, X_WARNING,
"final get vblank counter failed: %s\n",
strerror(errno));
- return FALSE;
+ goto blit_fallback;
}
*target_msc = vbl.reply.sequence;
swap_info->frame = *target_msc;
return TRUE;
+
+blit_fallback:
+ box.x1 = 0;
+ box.y1 = 0;
+ box.x2 = draw->width;
+ box.y2 = draw->height;
+ REGION_INIT(pScreen, ®ion, &box, 0);
+
+ I830DRI2CopyRegion(draw, ®ion, front, back);
+
+ DRI2SwapComplete(client, draw, 0, 0, 0, DRI2_BLIT_COMPLETE, func, data);
+ if (swap_info)
+ xfree(swap_info);
+ *target_msc = 0; /* offscreen, so zero out target vblank count */
+ return TRUE;
}
/*
commit 54ac4e2df987b72529a523ffbde357bec27e3658
Author: Chris Wilson <ch...@chris-wilson.co.uk>
Date: Thu Mar 4 21:34:52 2010 +0000
Rate limit batch buffer error.
Once we hit this error it's unlikely that we're coming back - so don't
flood the logs with redundant information.
Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
diff --git a/src/i830_batchbuffer.c b/src/i830_batchbuffer.c
index bf0b55b..a02e980 100644
--- a/src/i830_batchbuffer.c
+++ b/src/i830_batchbuffer.c
@@ -156,11 +156,17 @@ void intel_batch_submit(ScrnInfoPtr scrn)
ret =
dri_bo_exec(intel->batch_bo, intel->batch_used, NULL, 0,
0xffffffff);
- if (ret != 0)
- xf86DrvMsg(scrn->scrnIndex, X_ERROR,
- "Failed to submit batch buffer, expect rendering
corruption "
- "or even a frozen display: %s.\n",
- strerror(-ret));
+ if (ret != 0) {
+ static int once;
+
+ if (!once) {
+ xf86DrvMsg(scrn->scrnIndex, X_ERROR,
+ "Failed to submit batch buffer, expect
rendering corruption "
+ "or even a frozen display: %s.\n",
+ strerror(-ret));
+ once = 1;
+ }
+ }
while (!list_is_empty(&intel->batch_pixmaps)) {
struct intel_pixmap *entry;
commit 066d9b64ee243e0d255d7e12c2134951eef4ade7
Author: Daniel Vetter <daniel.vet...@ffwll.ch>
Date: Thu Mar 4 20:50:20 2010 +0100
i915 XvMC: kill dead code
This kills one wip remnant from my i830_memory cleanup and the last
remainings of the subpicture support.
Signed-off-by: Daniel Vetter <daniel.vet...@ffwll.ch>
diff --git a/src/i915_hwmc.c b/src/i915_hwmc.c
index 8ba122b..457c89b 100644
--- a/src/i915_hwmc.c
+++ b/src/i915_hwmc.c
@@ -231,26 +231,6 @@ static int i915_xvmc_put_image(ScrnInfoPtr scrn,
int ret;
if (FOURCC_XVMC == id) {
-#if 0
- switch (xvmc_cmd->command) {
- case INTEL_XVMC_COMMAND_DISPLAY:
- if ((xvmc_cmd->srfNo >= I915_XVMC_MAX_SURFACES) ||
- !pXvMC->surfaces[xvmc_cmd->srfNo] ||
- !pXvMC->sfprivs[xvmc_cmd->srfNo]) {
- xf86DrvMsg(scrn->scrnIndex, X_ERROR,
- "[XvMC] i915 put image: Invalid
parameters!\n");
- return 1;
- }
-
- /* use char *buf to hold our surface offset...hacky! */
- buf =
- (unsigned char *)pXvMC->sfprivs[xvmc_cmd->srfNo]->
- surface->bo->offset;
- break;
- default:
- return 0;
- }
-#endif
/* Pass the GEM object name through the pointer arg. */
buf = (void *)(uintptr_t)xvmc_cmd->handle;
}
@@ -295,10 +275,6 @@ static XF86MCAdaptorRec pAdapt = {
.name = "Intel(R) Textured Video",
.num_surfaces = ARRAY_SIZE(ppSI),
.surfaces = ppSI,
-#if 0
- .num_subpictures = ARRARY_SIZE(i915_subpicture_list),
- .subpictures = i915_subpicture_list,
-#endif
.num_subpictures = 0,
.subpictures = NULL,
.CreateContext =
commit 7b7c724da97f358f5d2d4d4dae75cfc85bde2c62
Author: Eric Anholt <e...@anholt.net>
Date: Thu Mar 4 10:29:09 2010 -0800
Remove remaining fbOffset setting.
In the long long ago, fbOffset was used for DGA. The server now has
only one reference to fbOffset, a leftover setting of it in fbdevhw.
We can safely ignore it now, which is good since we weren't updating
it in other places where the front buffer offset could change.
diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index 9cdb7e8..b1531bd 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -1368,7 +1368,6 @@ drmmode_do_pageflip(ScreenPtr screen, dri_bo *new_front,
dri_bo *old_front,
dri_bo_pin(new_front, 0);
dri_bo_unpin(new_front);
- scrn->fbOffset = new_front->offset;
intel->front_buffer = new_front;
drmmode->old_fb_id = old_fb_id;
diff --git a/src/i830.h b/src/i830.h
index 6d88a4c..7593cde 100644
--- a/src/i830.h
+++ b/src/i830.h
@@ -432,7 +432,6 @@ Bool i830_tiled_width(intel_screen_private *intel, int
*width, int cpp);
int i830_pad_drawable_width(int width, int cpp);
/* i830_memory.c */
-Bool i830_reinit_memory(ScrnInfoPtr scrn);
unsigned long i830_get_fence_size(intel_screen_private *intel, unsigned long
size);
unsigned long i830_get_fence_pitch(intel_screen_private *intel, unsigned long
pitch,
uint32_t tiling_mode);
diff --git a/src/i830_driver.c b/src/i830_driver.c
index 284ad71..53d8663 100644
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