NEWS | 7
RELEASING | 2
configure.ac | 12
man/intel.man | 20
src/Makefile.am | 68 --
src/bios_reader/bios_reader.c | 22
src/brw_structs.h | 21
src/drmmode_display.c | 232 ++++++++-
src/exa_sf.g4a | 107 ----
src/exa_sf.g4b | 15
src/exa_sf_mask.g4a | 107 ----
src/exa_sf_mask.g4b | 15
src/exa_wm.g4i | 156 ------
src/exa_wm_affine.g4i | 44 -
src/exa_wm_ca.g4a | 38 -
src/exa_wm_ca.g4b | 4
src/exa_wm_ca_srcalpha.g4a | 37 -
src/exa_wm_ca_srcalpha.g4b | 4
src/exa_wm_mask_affine.g4a | 41 -
src/exa_wm_mask_affine.g4b | 8
src/exa_wm_mask_projective.g4a | 53 --
src/exa_wm_mask_projective.g4b | 16
src/exa_wm_mask_sample_a.g4a | 48 -
src/exa_wm_mask_sample_a.g4b | 2
src/exa_wm_mask_sample_argb.g4a | 48 -
src/exa_wm_mask_sample_argb.g4b | 2
src/exa_wm_noca.g4a | 38 -
src/exa_wm_noca.g4b | 4
src/exa_wm_nomask.g4a | 143 -----
src/exa_wm_projective.g4i | 51 --
src/exa_wm_src_affine.g4a | 45 -
src/exa_wm_src_affine.g4b | 8
src/exa_wm_src_projective.g4a | 49 -
src/exa_wm_src_projective.g4b | 16
src/exa_wm_src_sample_a.g4a | 47 -
src/exa_wm_src_sample_a.g4b | 2
src/exa_wm_src_sample_argb.g4a | 47 -
src/exa_wm_src_sample_argb.g4b | 2
src/exa_wm_src_sample_planar.g4a | 65 --
src/exa_wm_src_sample_planar.g4b | 4
src/exa_wm_write.g4a | 74 ---
src/exa_wm_write.g4b | 18
src/exa_wm_xy.g4a | 52 --
src/exa_wm_xy.g4b | 4
src/exa_wm_yuv_rgb.g4a | 98 ---
src/exa_wm_yuv_rgb.g4b | 12
src/i810_reg.h | 6
src/i830.h | 29 -
src/i830_accel.c | 11
src/i830_batchbuffer.c | 2
src/i830_bios.c | 98 +++
src/i830_bios.h | 2
src/i830_display.c | 5
src/i830_dri.c | 55 +-
src/i830_driver.c | 279 +++++------
src/i830_hdmi.c | 18
src/i830_hwmc.c | 4
src/i830_lvds.c | 83 ++-
src/i830_memory.c | 155 +++---
src/i830_quirks.c | 4
src/i830_render.c | 4
src/i830_sdvo.c | 165 ++++++
src/i830_sdvo_regs.h | 2
src/i830_tv.c | 3
src/i830_uxa.c | 62 +-
src/i830_video.c | 467 ++++++++++---------
src/i965_render.c | 340 +++++++++++--
src/i965_video.c | 190 +++++--
src/packed_yuv_sf.g4a | 45 -
src/packed_yuv_sf.g4b | 17
src/packed_yuv_wm.g4a | 221 --------
src/packed_yuv_wm.g4b | 79 ---
src/render_program/Makefile.am | 82 +++
src/render_program/exa_sf.g4a | 107 ++++
src/render_program/exa_sf.g4b | 15
src/render_program/exa_sf.g4b.gen5 | 15
src/render_program/exa_sf_mask.g4a | 107 ++++
src/render_program/exa_sf_mask.g4b | 15
src/render_program/exa_sf_mask.g4b.gen5 | 15
src/render_program/exa_wm.g4i | 156 ++++++
src/render_program/exa_wm_affine.g4i | 44 +
src/render_program/exa_wm_ca.g4a | 38 +
src/render_program/exa_wm_ca.g4b | 4
src/render_program/exa_wm_ca.g4b.gen5 | 4
src/render_program/exa_wm_ca_srcalpha.g4a | 37 +
src/render_program/exa_wm_ca_srcalpha.g4b | 4
src/render_program/exa_wm_ca_srcalpha.g4b.gen5 | 4
src/render_program/exa_wm_mask_affine.g4a | 41 +
src/render_program/exa_wm_mask_affine.g4b | 8
src/render_program/exa_wm_mask_affine.g4b.gen5 | 8
src/render_program/exa_wm_mask_projective.g4a | 53 ++
src/render_program/exa_wm_mask_projective.g4b | 16
src/render_program/exa_wm_mask_projective.g4b.gen5 | 16
src/render_program/exa_wm_mask_sample_a.g4a | 48 +
src/render_program/exa_wm_mask_sample_a.g4b | 2
src/render_program/exa_wm_mask_sample_a.g4b.gen5 | 2
src/render_program/exa_wm_mask_sample_argb.g4a | 48 +
src/render_program/exa_wm_mask_sample_argb.g4b | 2
src/render_program/exa_wm_mask_sample_argb.g4b.gen5 | 2
src/render_program/exa_wm_noca.g4a | 38 +
src/render_program/exa_wm_noca.g4b | 4
src/render_program/exa_wm_noca.g4b.gen5 | 4
src/render_program/exa_wm_projective.g4i | 51 ++
src/render_program/exa_wm_src_affine.g4a | 45 +
src/render_program/exa_wm_src_affine.g4b | 8
src/render_program/exa_wm_src_affine.g4b.gen5 | 8
src/render_program/exa_wm_src_projective.g4a | 49 +
src/render_program/exa_wm_src_projective.g4b | 16
src/render_program/exa_wm_src_projective.g4b.gen5 | 16
src/render_program/exa_wm_src_sample_a.g4a | 47 +
src/render_program/exa_wm_src_sample_a.g4b | 2
src/render_program/exa_wm_src_sample_a.g4b.gen5 | 2
src/render_program/exa_wm_src_sample_argb.g4a | 47 +
src/render_program/exa_wm_src_sample_argb.g4b | 2
src/render_program/exa_wm_src_sample_argb.g4b.gen5 | 2
src/render_program/exa_wm_src_sample_planar.g4a | 65 ++
src/render_program/exa_wm_src_sample_planar.g4b | 4
src/render_program/exa_wm_src_sample_planar.g4b.gen5 | 4
src/render_program/exa_wm_write.g4a | 74 +++
src/render_program/exa_wm_write.g4b | 18
src/render_program/exa_wm_write.g4b.gen5 | 18
src/render_program/exa_wm_xy.g4a | 52 ++
src/render_program/exa_wm_xy.g4b | 4
src/render_program/exa_wm_xy.g4b.gen5 | 4
src/render_program/exa_wm_yuv_rgb.g4a | 98 +++
src/render_program/exa_wm_yuv_rgb.g4b | 12
src/render_program/exa_wm_yuv_rgb.g4b.gen5 | 12
src/xvmc/intel_batchbuffer.c | 4
uxa/uxa-render.c | 5
129 files changed, 3189 insertions(+), 2673 deletions(-)
New commits:
commit 82905c7c0b871a97ec435a765c2ca407903ba595
Author: Carl Worth <cwo...@cworth.org>
Date: Mon Jul 13 05:29:49 2009 -0700
Increment version to 2.7.99.902
diff --git a/configure.ac b/configure.ac
index 486fed7..077c1ff 100644
--- a/configure.ac
+++ b/configure.ac
@@ -22,7 +22,7 @@
AC_PREREQ(2.57)
AC_INIT([xf86-video-intel],
- 2.7.99.901,
+ 2.7.99.902,
[https://bugs.freedesktop.org/enter_bug.cgi?product=xorg],
xf86-video-intel)
commit 925bc6cbd430a00928fac2ef58724dd37c3bc349
Author: Carl Worth <cwo...@cworth.org>
Date: Mon Jul 13 05:27:40 2009 -0700
RELEASING: Fix typo in instructions
diff --git a/RELEASING b/RELEASING
index 2196c8f..e32ecf6 100644
--- a/RELEASING
+++ b/RELEASING
@@ -37,7 +37,7 @@ The process for releasing a new tarball is as follows:
At the very least, add the release notes from the NEWS file.
- The message is generated as xf86-video-inte-<version>.announce
+ The message is generated as xf86-video-intel-<version>.announce
For snapshots and release candidates, mail to:
commit 67c0afc7b7446a7b98aa7c65043ddba4c7c72b82
Author: Carl Worth <cwo...@cworth.org>
Date: Mon Jul 13 05:27:06 2009 -0700
NEWS: Add notes for 2.7.99.902
diff --git a/NEWS b/NEWS
index 294a78c..ddc2f40 100644
--- a/NEWS
+++ b/NEWS
@@ -1,3 +1,10 @@
+Snapshot 2.7.99.902 (2009-07-13)
+--------------------------------
+This is the first release candidate in preparation for the upcoming
+2.8.0 release. Most major and critical bugs should be fixed, but some
+minor bugs may still be present. We will appreciate any feedback we
+can get from testing of this snapshot to improve the 2.8.0 release.
+
Snapshot 2.7.99.901 (2009-06-10)
--------------------------------
This is the first release candidate in preparation for the upcoming
commit 34c674dd45879b8ba8395b93b16c8a9e7b848f1f
Author: Keith Packard <kei...@keithp.com>
Date: Sat Jul 11 22:53:42 2009 -0700
Remove vestiges of NoAccel options from i830_driver.c
The enum and OptionInfoRec weren't removed in the initial patch
Signed-off-by: Keith Packard <kei...@keithp.com>
diff --git a/src/i830_driver.c b/src/i830_driver.c
index fe2565c..dfc2bdf 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -162,7 +162,6 @@ static PciChipsets I830PciChipsets[] = {
*/
typedef enum {
- OPTION_NOACCEL,
OPTION_DRI,
OPTION_VIDEO_KEY,
OPTION_COLOR_KEY,
@@ -181,7 +180,6 @@ typedef enum {
} I830Opts;
static OptionInfoRec I830Options[] = {
- {OPTION_NOACCEL, "NoAccel", OPTV_BOOLEAN, {0}, FALSE},
{OPTION_DRI, "DRI", OPTV_BOOLEAN, {0}, TRUE},
{OPTION_COLOR_KEY, "ColorKey", OPTV_INTEGER, {0}, FALSE},
{OPTION_VIDEO_KEY, "VideoKey", OPTV_INTEGER, {0}, FALSE},
commit 33d6e7a2355dfb8ad324c4fa28ce61c7e051b435
Author: Keith Packard <kei...@keithp.com>
Date: Sat Jul 11 22:53:11 2009 -0700
intel.man: Mark NoAccel option as i810/i815 only
The NoAccel option is not valid for other chips.
Signed-off-by: Keith Packard <kei...@keithp.com>
diff --git a/man/intel.man b/man/intel.man
index 6330e4b..d498d7e 100644
--- a/man/intel.man
+++ b/man/intel.man
@@ -56,11 +56,6 @@ The following driver
.B Options
are supported
.TP
-.BI "Option \*qNoAccel\*q \*q" boolean \*q
-Disable or enable acceleration.
-.IP
-Default: acceleration is enabled.
-.TP
.BI "Option \*qColorKey\*q \*q" integer \*q
This sets the default pixel value for the YUV video overlay key.
.IP
@@ -134,6 +129,11 @@ This option specifies the amount of system memory to use
for graphics, in KB.
The default is 8192 if AGP allocable memory is < 128 MB, 16384 if < 192 MB,
24576 if higher. DRI require at least a value of 16384. Higher values may give
better 3D performance, at expense of available system memory.
+.TP
+.BI "Option \*qNoAccel\*q \*q" boolean \*q
+Disable or enable acceleration.
+.IP
+Default: acceleration is enabled.
.PP
The following driver
commit ed8a9a94e1a670ca35311c9ed83d0c479530d41a
Author: Keith Packard <kei...@keithp.com>
Date: Fri Jul 10 17:13:14 2009 -0700
i830_uxa_prepare_access: Flush and wait for idle for non-bo pixmaps
Without kernel support and explicit knowledge about where in the ring the
last rendering operation for a specific pixmap was, we must synchronize with
any outstanding rendering before accessing a pixmap which does not have a
buffer object.
Signed-off-by: Keith Packard <kei...@keithp.com>
diff --git a/src/i830_uxa.c b/src/i830_uxa.c
index c3fdcec..2050c48 100644
--- a/src/i830_uxa.c
+++ b/src/i830_uxa.c
@@ -477,13 +477,12 @@ static Bool
i830_uxa_prepare_access (PixmapPtr pixmap, uxa_access_t access)
{
dri_bo *bo = i830_get_pixmap_bo (pixmap);
+ ScrnInfoPtr scrn = xf86Screens[pixmap->drawable.pScreen->myNum];
+
+ intel_batch_flush(scrn, FALSE);
if (bo) {
- ScreenPtr screen = pixmap->drawable.pScreen;
- ScrnInfoPtr scrn = xf86Screens[screen->myNum];
I830Ptr i830 = I830PTR(scrn);
-
- intel_batch_flush(scrn, FALSE);
/* No VT sema or GEM? No GTT mapping. */
if (!scrn->vtSema || !i830->have_gem) {
@@ -517,7 +516,9 @@ i830_uxa_prepare_access (PixmapPtr pixmap, uxa_access_t
access)
drm_intel_gem_bo_start_gtt_access(bo, access == UXA_ACCESS_RW);
pixmap->devPrivate.ptr = i830->FbBase + bo->offset;
}
- }
+ } else
+ i830_wait_ring_idle(scrn);
+
return TRUE;
}
commit cb19ac207b784d814f6f389110fd1b21a0f34e8b
Author: Keith Packard <kei...@keithp.com>
Date: Fri Jul 10 14:01:02 2009 -0700
KMS: Keep screen pixmap devPrivate.ptr NULL during init and resize
The frame buffer only has a valid address between prepare_access and
finish_access calls, so remove all other attempts to compute an address from
the driver.
Signed-off-by: Keith Packard <kei...@keithp.com>
diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index 7cfdc5b..df10fb5 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -1056,12 +1056,9 @@ drmmode_xf86crtc_resize (ScrnInfoPtr scrn, int width,
int height)
goto fail;
i830_set_pixmap_bo(screen->GetScreenPixmap(screen),
pI830->front_buffer->bo);
- scrn->fbOffset = pI830->front_buffer->offset;
screen->ModifyPixmapHeader(screen->GetScreenPixmap(screen),
width, height, -1, -1, pitch * pI830->cpp,
NULL);
- xf86DrvMsg(scrn->scrnIndex, X_INFO, "New front buffer at 0x%lx\n",
- pI830->front_buffer->offset);
for (i = 0; i < xf86_config->num_crtc; i++) {
xf86CrtcPtr crtc = xf86_config->crtc[i];
commit 704b88dd50a7e7e3f362264b86d0401bee8603aa
Author: Keith Packard <kei...@keithp.com>
Date: Wed Jul 8 13:06:47 2009 -0700
i830_bind_memory: Under UMS: Bind GEM bos with dri_bo_pin, else through the
GART
We only need to get static offsets for objects when not running KMS,
otherwise the kernel will manage those as needed for us.
Binding objects is done in one of two ways. For GEM buffer objects, we use
dri_bo_pin. For GART allocated memory, we bind that to the GART.
diff --git a/src/i830_memory.c b/src/i830_memory.c
index 556b511..f2f3966 100644
--- a/src/i830_memory.c
+++ b/src/i830_memory.c
@@ -199,10 +199,11 @@ i830_bind_memory(ScrnInfoPtr pScrn, i830_memory *mem)
{
I830Ptr pI830 = I830PTR(pScrn);
- if (mem == NULL || mem->bound)
+ if (mem == NULL || mem->bound || pI830->use_drm_mode)
return TRUE;
- if (mem->bo != NULL && !pI830->use_drm_mode) {
+ if (pI830->have_gem && mem->bo != NULL) {
+
if (dri_bo_pin(mem->bo, mem->alignment) != 0) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"Failed to pin %s: %s\n",
@@ -213,9 +214,7 @@ i830_bind_memory(ScrnInfoPtr pScrn, i830_memory *mem)
mem->bound = TRUE;
mem->offset = mem->bo->offset;
mem->end = mem->offset + mem->size;
- }
-
- if (!mem->bound) {
+ } else {
if (!pI830->gtt_acquired)
return TRUE;
@@ -228,8 +227,7 @@ i830_bind_memory(ScrnInfoPtr pScrn, i830_memory *mem)
mem->bound = TRUE;
}
- if (mem->tiling != TILE_NONE && !pI830->use_drm_mode &&
- !pI830->kernel_exec_fencing) {
+ if (mem->tiling != TILE_NONE && !pI830->kernel_exec_fencing) {
mem->fence_nr = i830_set_tiling(pScrn, mem->offset, mem->pitch,
mem->allocated_size, mem->tiling);
}
@@ -1114,7 +1112,7 @@ i830_allocate_framebuffer(ScrnInfoPtr pScrn)
return NULL;
}
- if (!pI830->use_drm_mode && pI830->FbBase && front_buffer->bound)
+ if (pI830->FbBase && front_buffer->bound)
memset (pI830->FbBase + front_buffer->offset, 0, size);
i830_set_max_gtt_map_size(pScrn);
commit 7b273732f70e91df8b41d5c48e1379271557dd8e
Author: Keith Packard <kei...@keithp.com>
Date: Wed Jul 8 11:53:13 2009 -0700
Allocate GTT space for GEM only under UMS
GEM requires GTT space to map objects. Under KMS, the kernel driver has
already provided all available GTT space to GEM, so the X server need not do
anything.
Signed-off-by: Keith Packard <kei...@keithp.com>
diff --git a/src/i830_driver.c b/src/i830_driver.c
index e5e5fd7..fe2565c 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -2674,8 +2674,8 @@ I830ScreenInit(int scrnIndex, ScreenPtr pScreen, int
argc, char **argv)
if (!pI830->use_drm_mode)
I830MapMMIO(pScrn);
- /* Need FB mapped to set up the fake bufmgr if we end up doing that
- * in i830_memory_init() -> i830_allocator_init().
+ /* Need FB mapped to access non-GEM objects like
+ * a UMS frame buffer, or the fake bufmgr.
*/
if (!pI830->use_drm_mode) {
if (!I830MapMem(pScrn))
@@ -2701,10 +2701,6 @@ I830ScreenInit(int scrnIndex, ScreenPtr pScreen, int
argc, char **argv)
if (!miSetPixmapDepths())
return FALSE;
- i830_init_bufmgr(pScrn);
-
- pScrn->fbOffset = pI830->front_buffer->offset;
-
if (!pI830->use_drm_mode) {
vgaHWSetMmioFuncs(hwp, pI830->MMIOBase, 0);
vgaHWGetIOBase(hwp);
diff --git a/src/i830_memory.c b/src/i830_memory.c
index 2953f3b..556b511 100644
--- a/src/i830_memory.c
+++ b/src/i830_memory.c
@@ -334,10 +334,8 @@ i830_reset_allocations(ScrnInfoPtr pScrn)
}
/* Free any allocations in buffer objects */
- if (pI830->memory_manager) {
- while (pI830->bo_list != NULL)
- i830_free_memory(pScrn, pI830->bo_list);
- }
+ while (pI830->bo_list != NULL)
+ i830_free_memory(pScrn, pI830->bo_list);
/* Null out the pointers for all the allocations we just freed. This is
* kind of gross, but at least it's just one place now.
@@ -405,12 +403,14 @@ i830_allocator_init(ScrnInfoPtr pScrn, unsigned long size)
pI830->memory_list = start;
- /* Now that we have our manager set up, initialize the kernel MM if
- * possible, covering almost all of the aperture. We need libdri interface
- * 5.4 or newer so we can rely on the lock being held after DRIScreenInit,
- * rather than after DRIFinishScreenInit.
+ /* Now that we have our manager set up, give the kernel a piece of the
+ * aperture for GEM buffer object mapping. This is only needed for UXA
+ * and/or DRI2 when the kernel hasn't already managed this itself under
+ * KMS. We need libdri interface5.4 or newer so we can rely on the lock
+ * being held after DRIScreenInit, rather than after DRIFinishScreenInit.
*/
- if (pI830->directRenderingType == DRI_DRI2) {
+
+ if (!pI830->use_drm_mode) {
int mmsize;
/* Take over all of the graphics aperture minus enough to for
@@ -426,53 +426,49 @@ i830_allocator_init(ScrnInfoPtr pScrn, unsigned long size)
}
if (pI830->CursorNeedsPhysical) {
mmsize -= 2 * (ROUND_TO(HWCURSOR_SIZE, GTT_PAGE_SIZE) +
- ROUND_TO(HWCURSOR_SIZE_ARGB, GTT_PAGE_SIZE));
+ ROUND_TO(HWCURSOR_SIZE_ARGB, GTT_PAGE_SIZE));
}
if (pI830->fb_compression)
mmsize -= MB(6) + ROUND_TO_PAGE(FBC_LL_SIZE + FBC_LL_PAD);
+
/* Can't do GEM on stolen memory */
mmsize -= pI830->stolen_size;
/* Create the aperture allocation */
pI830->memory_manager =
- i830_allocate_aperture(pScrn, "DRI memory manager",
- mmsize, 0, GTT_PAGE_SIZE,
- ALIGN_BOTH_ENDS | NEED_NON_STOLEN,
- TILE_NONE);
+ i830_allocate_aperture(pScrn, "DRI memory manager",
+ mmsize, 0, GTT_PAGE_SIZE,
+ ALIGN_BOTH_ENDS | NEED_NON_STOLEN,
+ TILE_NONE);
if (pI830->memory_manager != NULL) {
- if (!pI830->use_drm_mode) {
- struct drm_i915_gem_init init;
- int ret;
-
- sp.param = I915_SETPARAM_NUM_USED_FENCES;
- sp.value = 0; /* kernel gets them all */
-
- ret = drmCommandWrite(pI830->drmSubFD, DRM_I915_SETPARAM,
- &sp, sizeof(sp));
- if (ret == 0)
- pI830->kernel_exec_fencing = TRUE;
-
- init.gtt_start = pI830->memory_manager->offset;
- init.gtt_end = pI830->memory_manager->offset +
- pI830->memory_manager->size;
-
- /* Tell the kernel to manage it */
- ret = ioctl(pI830->drmSubFD, DRM_IOCTL_I915_GEM_INIT, &init);
- if (ret != 0) {
- xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
- "Failed to initialize kernel memory manager\n");
- i830_free_memory(pScrn, pI830->memory_manager);
- pI830->memory_manager = NULL;
- }
+ struct drm_i915_gem_init init;
+ int ret;
+
+ sp.param = I915_SETPARAM_NUM_USED_FENCES;
+ sp.value = 0; /* kernel gets them all */
+
+ ret = drmCommandWrite(pI830->drmSubFD, DRM_I915_SETPARAM,
+ &sp, sizeof(sp));
+ if (ret == 0)
+ pI830->kernel_exec_fencing = TRUE;
+ init.gtt_start = pI830->memory_manager->offset;
+ init.gtt_end = pI830->memory_manager->offset +
pI830->memory_manager->size;
+
+ /* Tell the kernel to manage it */
+ ret = ioctl(pI830->drmSubFD, DRM_IOCTL_I915_GEM_INIT, &init);
+ if (ret == 0) {
pI830->have_gem = TRUE;
i830_init_bufmgr(pScrn);
+ } else {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "Failed to initialize kernel memory manager\n");
+ i830_free_memory(pScrn, pI830->memory_manager);
+ pI830->memory_manager = NULL;
}
} else {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"Failed to allocate space for kernel memory manager\n");
- i830_free_memory(pScrn, pI830->memory_manager);
- pI830->memory_manager = NULL;
}
}
@@ -842,9 +838,15 @@ i830_allocate_memory(ScrnInfoPtr pScrn, const char *name,
size = i830_get_fence_size(pI830, size);
alignment = i830_get_fence_alignment(pI830, size);
}
- if (pI830->use_drm_mode || (pI830->memory_manager &&
- !(flags & NEED_PHYSICAL_ADDR) &&
- !(flags & NEED_LIFETIME_FIXED)))
+ /*
+ * Create a kernel buffer object when suitable.
+ * Under KMS, all graphics memory must be managed by the
+ * kernel. Under UMS, we separately reserve space for
+ * a few objects (overlays, power context, cursors, etc).
+ */
+ if (pI830->have_gem &&
+ (pI830->use_drm_mode ||
+ !(flags & (NEED_PHYSICAL_ADDR|NEED_LIFETIME_FIXED))))
{
return i830_allocate_memory_bo(pScrn, name, size, pitch, alignment,
flags, tile_format);
} else
@@ -917,31 +919,33 @@ i830_describe_allocations(ScrnInfoPtr pScrn, int
verbosity, const char *prefix)
"%s0x%08lx: end of aperture\n",
prefix, pI830->FbMapSize);
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, verbosity,
+ "%sBO memory allocation layout:\n", prefix);
if (pI830->memory_manager) {
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, verbosity,
- "%sBO memory allocation layout:\n", prefix);
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, verbosity,
"%s0x%08lx: start of memory manager\n",
prefix, pI830->memory_manager->offset);
- for (mem = pI830->bo_list; mem != NULL; mem = mem->next) {
- char *tile_suffix = "";
-
- if (mem->tiling == TILE_XMAJOR)
- tile_suffix = " X tiled";
- else if (mem->tiling == TILE_YMAJOR)
- tile_suffix = " Y tiled";
-
- if (mem->bound) {
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, verbosity,
- "%s0x%08lx-0x%08lx: %s (%ld kB)%s\n", prefix,
- mem->offset, mem->end - 1, mem->name,
- mem->size / 1024, tile_suffix);
- } else {
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, verbosity,
- "%sunpinned : %s (%ld kB)%s\n", prefix,
- mem->name, mem->size / 1024, tile_suffix);
- }
+ }
+ for (mem = pI830->bo_list; mem != NULL; mem = mem->next) {
+ char *tile_suffix = "";
+
+ if (mem->tiling == TILE_XMAJOR)
+ tile_suffix = " X tiled";
+ else if (mem->tiling == TILE_YMAJOR)
+ tile_suffix = " Y tiled";
+
+ if (mem->bound) {
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, verbosity,
+ "%s0x%08lx-0x%08lx: %s (%ld kB)%s\n", prefix,
+ mem->offset, mem->end - 1, mem->name,
+ mem->size / 1024, tile_suffix);
+ } else {
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, verbosity,
+ "%sunpinned : %s (%ld kB)%s\n", prefix,
+ mem->name, mem->size / 1024, tile_suffix);
}
+ }
+ if (pI830->memory_manager) {
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, verbosity,
"%s0x%08lx: end of memory manager\n",
prefix, pI830->memory_manager->end);
@@ -953,7 +957,7 @@ i830_allocate_ringbuffer(ScrnInfoPtr pScrn)
{
I830Ptr pI830 = I830PTR(pScrn);
- if (pI830->memory_manager || pI830->ring.mem != NULL)
+ if (pI830->have_gem || pI830->ring.mem != NULL)
return TRUE;
/* We don't have any mechanism in the DRM yet to alert it that we've moved
@@ -1277,7 +1281,7 @@ i830_allocate_2d_memory(ScrnInfoPtr pScrn)
return FALSE;
}
- if (pI830->memory_manager == NULL) {
+ if (!pI830->have_gem) {
pI830->fake_bufmgr_mem = i830_allocate_memory(pScrn, "fake bufmgr",
MB(8), PITCH_NONE,
GTT_PAGE_SIZE, 0,
TILE_NONE);
@@ -1286,6 +1290,7 @@ i830_allocate_2d_memory(ScrnInfoPtr pScrn)
"Failed to allocate fake bufmgr space.\n");
return FALSE;
}
+ i830_init_bufmgr(pScrn);
}
if (!pI830->use_drm_mode)
commit 56bfee8705f5d7d965227013b205dbc4c93e220c
Author: Keith Packard <kei...@keithp.com>
Date: Fri Jul 10 14:49:20 2009 -0700
Always set screen pixmap data pointer at init and resize times
For non-DRM environments, the screen pixmap will be GART allocated memory
and not a libdrm buffer object and so uxa will only use devPrivate.ptr to
find the associated memory. Make sure devPrivate.ptr is set each time the
framebuffer is allocated so that uxa will be able to draw to it.
Signed-off-by: Keith Packard <kei...@keithp.com>
diff --git a/src/i830_driver.c b/src/i830_driver.c
index ee39a1b..e5e5fd7 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -880,7 +880,6 @@ i830_xf86crtc_resize (ScrnInfoPtr scrn, int width, int
height)
i830_memory *new_front, *old_front;
Bool tiled;
ScreenPtr screen = screenInfo.screens[scrn->scrnIndex];
- pointer data = NULL;
scrn->displayWidth = i830_pad_drawable_width(width, i830->cpp);
tiled = i830_tiled_width(i830, &scrn->displayWidth, i830->cpp);
@@ -900,15 +899,15 @@ i830_xf86crtc_resize (ScrnInfoPtr scrn, int width, int
height)
i830_set_pixmap_bo(screen->GetScreenPixmap(screen),
new_front->bo);
scrn->fbOffset = i830->front_buffer->offset;
- if (!new_front->bo)
- data = i830->FbBase + scrn->fbOffset;
+
screen->ModifyPixmapHeader(screen->GetScreenPixmap(screen),
width, height, -1, -1, scrn->displayWidth *
i830->cpp,
- data);
+ i830->FbBase + scrn->fbOffset);
+
/* ick. xf86EnableDisableFBAccess smashes the screen pixmap devPrivate,
* so update the value it uses
*/
- scrn->pixmapPrivate.ptr = data;
+ scrn->pixmapPrivate.ptr = i830->FbBase + scrn->fbOffset;
xf86DrvMsg(scrn->scrnIndex, X_INFO, "New front buffer at 0x%lx\n",
i830->front_buffer->offset);
i830_set_new_crtc_bo(scrn);
@@ -2719,6 +2718,12 @@ I830ScreenInit(int scrnIndex, ScreenPtr pScreen, int
argc, char **argv)
if (pScrn->virtualX > pScrn->displayWidth)
pScrn->displayWidth = pScrn->virtualX;
+ /* If the front buffer is not a BO, we need to
+ * set the initial framebuffer pixmap to point at
+ * it
+ */
+ pScrn->fbOffset = pI830->front_buffer->offset;
+
DPRINTF(PFX, "assert( if(!fbScreenInit(pScreen, ...) )\n");
if (!fbScreenInit(pScreen, pI830->FbBase + pScrn->fbOffset,
pScrn->virtualX, pScrn->virtualY,
commit 98087a0b966d5dc69faf72719153a2c878ba3de1
Author: Keith Packard <kei...@keithp.com>
Date: Wed Jul 8 11:47:25 2009 -0700
Make xorg.conf DRI option work under KMS. Fix name of I830AccelMethodInit
KMS mode does not call I830AccelMethodInit as that does the user
modesetting initialization (yes, it was misnamed), but that means that the
DRI option
was ignored. Create a new i830_check_dri_option function to do the option
detection, then remove that from I830AccelMethodInit, which is renamed
i830_user_modesetting_init to reflect what it actually does.
Signed-off-by: Keith Packard <kei...@keithp.com>
diff --git a/src/i830_driver.c b/src/i830_driver.c
index cc0a1f6..ee39a1b 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -1301,12 +1301,10 @@ I830PreInitCrtcConfig(ScrnInfoPtr pScrn)
xf86CrtcSetSizeRange (pScrn, 320, 200, max_width, max_height);
}
-static Bool
-I830AccelMethodInit(ScrnInfoPtr pScrn)
+static void
+i830_check_dri_option(ScrnInfoPtr pScrn)
{
I830Ptr pI830 = I830PTR(pScrn);
- int i, num_pipe;
-
pI830->directRenderingType = DRI_NONE;
if (!xf86ReturnOptValBool(pI830->Options, OPTION_DRI, TRUE))
pI830->directRenderingType = DRI_DISABLED;
@@ -1316,6 +1314,13 @@ I830AccelMethodInit(ScrnInfoPtr pScrn)
"runs only at depths 16 and 24.\n");
pI830->directRenderingType = DRI_DISABLED;
}
+}
+
+static Bool
+i830_user_modesetting_init(ScrnInfoPtr pScrn)
+{
+ I830Ptr pI830 = I830PTR(pScrn);
+ int i, num_pipe;
I830MapMMIO(pScrn);
@@ -1442,7 +1447,6 @@ I830DrmModeInit(ScrnInfoPtr pScrn)
return FALSE;
}
- pI830->directRenderingType = DRI_NONE;
pI830->have_gem = TRUE;
i830_init_bufmgr(pScrn);
@@ -1587,6 +1591,8 @@ I830PreInit(ScrnInfoPtr pScrn, int flags)
if (!i830_detect_chipset(pScrn))
return FALSE;
+ i830_check_dri_option(pScrn);
+
if (pI830->use_drm_mode) {
if (!I830DrmModeInit(pScrn))
return FALSE;
@@ -1595,7 +1601,7 @@ I830PreInit(ScrnInfoPtr pScrn, int flags)
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"VBIOS initialization failed.\n");
I830PreInitCrtcConfig(pScrn);
- if (!I830AccelMethodInit(pScrn))
+ if (!i830_user_modesetting_init(pScrn))
return FALSE;
}
commit d655a3ff423e69c19a5dc07140cbf3caaa32cb86
Author: Keith Packard <kei...@keithp.com>
Date: Wed Jul 8 18:06:40 2009 -0700
Remove NoAccel support
This removes yet another 'debugging' option that hasn't seen real use in a
long time, and wasn't supported under KMS in any case.
Signed-off-by: Keith Packard <kei...@keithp.com>
diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index e9296dc..7cfdc5b 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -329,8 +329,6 @@ drmmode_crtc_shadow_allocate(xf86CrtcPtr crtc, int width,
int height)
return NULL;
}
- drm_intel_gem_bo_map_gtt(drmmode_crtc->rotate_bo);
-
ret = drmModeAddFB(drmmode->fd, width, height, crtc->scrn->depth,
crtc->scrn->bitsPerPixel, rotate_pitch,
drmmode_crtc->rotate_bo->handle,
@@ -341,7 +339,7 @@ drmmode_crtc_shadow_allocate(xf86CrtcPtr crtc, int width,
int height)
return NULL;
}
- return drmmode_crtc->rotate_bo->virtual;
+ return drmmode_crtc->rotate_bo;
}
static PixmapPtr
@@ -353,8 +351,14 @@ drmmode_crtc_shadow_create(xf86CrtcPtr crtc, void *data,
int width, int height)
unsigned long rotate_pitch;
PixmapPtr rotate_pixmap;
- if (!data)
+ if (!data) {
data = drmmode_crtc_shadow_allocate (crtc, width, height);
+ if (!data) {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "Couldn't allocate shadow pixmap for rotated
CRTC\n");
+ return NULL;
+ }
+ }
rotate_pitch =
i830_pad_drawable_width(width, drmmode->cpp) * drmmode->cpp;
@@ -363,11 +367,12 @@ drmmode_crtc_shadow_create(xf86CrtcPtr crtc, void *data,
int width, int height)
pScrn->depth,
pScrn->bitsPerPixel,
rotate_pitch,
- data);
+ NULL);
if (rotate_pixmap == NULL) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"Couldn't allocate shadow pixmap for rotated
CRTC\n");
+ return NULL;
}
if (drmmode_crtc->rotate_bo)
@@ -393,7 +398,6 @@ drmmode_crtc_shadow_destroy(xf86CrtcPtr crtc, PixmapPtr
rotate_pixmap, void *dat
* unbound. */
drmModeRmFB(drmmode->fd, drmmode_crtc->rotate_fb_id);
drmmode_crtc->rotate_fb_id = 0;
- drm_intel_gem_bo_unmap_gtt(drmmode_crtc->rotate_bo);
dri_bo_unreference(drmmode_crtc->rotate_bo);
drmmode_crtc->rotate_bo = NULL;
}
diff --git a/src/i830.h b/src/i830.h
index dc5e0c8..f7ca687 100644
--- a/src/i830.h
+++ b/src/i830.h
@@ -317,12 +317,6 @@ enum backlight_control {
BCM_KERNEL,
};
-typedef enum accel_method {
- ACCEL_UNINIT = 0,
- ACCEL_NONE,
- ACCEL_UXA
-} accel_method_t;
-
enum dri_type {
DRI_DISABLED,
DRI_NONE,
@@ -431,7 +425,6 @@ typedef struct _I830Rec {
Bool fence_used[FENCE_NEW_NR];
- accel_method_t accel;
CloseScreenProcPtr CloseScreen;
void (*batch_flush_notify)(ScrnInfoPtr pScrn);
@@ -827,8 +820,7 @@ i830_wait_ring_idle(ScrnInfoPtr pScrn)
{
I830Ptr pI830 = I830PTR(pScrn);
- if (pI830->accel != ACCEL_NONE)
- I830WaitLpRing(pScrn, pI830->ring.mem->size - 8, 0);
+ I830WaitLpRing(pScrn, pI830->ring.mem->size - 8, 0);
}
static inline int i830_fb_compression_supported(I830Ptr pI830)
@@ -841,10 +833,9 @@ static inline int i830_fb_compression_supported(I830Ptr
pI830)
return FALSE;
if (IS_IGDNG(pI830))
return FALSE;
- /* fbc depends on tiled surface. And we don't support tiled
- * front buffer with unaccelerated.
+ /* fbc depends on tiled surface.
*/
- if (!pI830->tiling || (IS_I965G(pI830) && pI830->accel == ACCEL_NONE))
+ if (!pI830->tiling)
return FALSE;
/* We have not gotten FBC to work consistently on 965GM. Our best
* working theory right now is that FBC simply isn't reliable on
diff --git a/src/i830_accel.c b/src/i830_accel.c
index b365e3f..96a7bde 100644
--- a/src/i830_accel.c
+++ b/src/i830_accel.c
@@ -136,7 +136,7 @@ I830Sync(ScrnInfoPtr pScrn)
if (I810_DEBUG & (DEBUG_VERBOSE_ACCEL | DEBUG_VERBOSE_SYNC))
ErrorF("I830Sync\n");
- if (pI830->accel == ACCEL_NONE || !pScrn->vtSema || !pI830->batch_bo)
+ if (!pScrn->vtSema || !pI830->batch_bo)
return;
I830EmitFlush(pScrn);
@@ -236,12 +236,5 @@ I830AccelInit(ScreenPtr pScreen)
if (pI830->directRenderingType >= DRI_DRI2)
pI830->accel_pixmap_pitch_alignment = 512;
- switch (pI830->accel) {
- case ACCEL_UXA:
- return i830_uxa_init(pScreen);
- case ACCEL_UNINIT:
- case ACCEL_NONE:
- break;
- }
- return FALSE;
+ return i830_uxa_init(pScreen);
}
diff --git a/src/i830_dri.c b/src/i830_dri.c
index 240c519..40d11e4 100644
--- a/src/i830_dri.c
+++ b/src/i830_dri.c
@@ -373,11 +373,6 @@ Bool I830DRI2ScreenInit(ScreenPtr pScreen)
int dri2_minor = 0;
#endif
- if (pI830->accel != ACCEL_UXA) {
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "DRI2 requires UXA\n");
- return FALSE;
- }
-
#ifdef USE_DRI2_1_1_0
if (xf86LoaderCheckSymbol("DRI2Version")) {
DRI2Version(& dri2_major, & dri2_minor);
diff --git a/src/i830_driver.c b/src/i830_driver.c
index 257bd6c..cc0a1f6 100644
--- a/src/i830_driver.c
+++ b/src/i830_driver.c
@@ -598,49 +598,6 @@ I830LoadPalette(ScrnInfoPtr pScrn, int numColors, int
*indices,
}
}
-static void
-i830_update_front_offset(ScrnInfoPtr pScrn)
-{
- ScreenPtr pScreen = pScrn->pScreen;
- I830Ptr pI830 = I830PTR(pScrn);
- int pitch = pScrn->displayWidth * pI830->cpp;
- pointer data = NULL;
-
- /* Update buffer locations, which may have changed as a result of
- * i830_bind_all_memory().
- */
- pScrn->fbOffset = pI830->front_buffer->offset;
-
- if (pI830->starting || pI830->accel == ACCEL_UXA)
- return;
-
- /* If we are still in ScreenInit, there is no screen pixmap to be updated
- * yet. We'll fix it up at CreateScreenResources.
- */
- if (!pI830->have_gem) {
- data = pI830->FbBase + pScrn->fbOffset; /* default to legacy */
- } else {
- dri_bo *bo = pI830->front_buffer->bo;
-
- if (bo) {
- if (pI830->kernel_exec_fencing) {
- if (drm_intel_gem_bo_map_gtt(bo))
- xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "%s: bo map failed\n",
- __FUNCTION__);
- data = bo->virtual;
- } else {
- /* Will already be pinned by bind_all_memory in this case */
- drm_intel_gem_bo_start_gtt_access(bo, 1);
- data = pI830->FbBase + bo->offset;
- }
- }
- }
- if (!pScreen->ModifyPixmapHeader(pScreen->GetScreenPixmap(pScreen),
- pScrn->virtualX, pScrn->virtualY, -1, -1,
- pitch, data))
--
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