src/atombios_crtc.c | 4 -
src/legacy_crtc.c | 48 ++++++++-------------
src/legacy_output.c | 11 ++--
src/r600_state.h | 6 +-
src/radeon.h | 3 -
src/radeon_accel.c | 9 +++-
src/radeon_atombios.c | 46 ++++++++++++--------
src/radeon_commonfuncs.c | 40 +++++++++---------
src/radeon_crtc.c | 13 +++--
src/radeon_cursor.c | 70 ++++++++++++++++++++-----------
src/radeon_dri.c | 9 ++--
src/radeon_driver.c | 68 +++++-------------------------
src/radeon_exa_render.c | 16 ++++---
src/radeon_output.c | 86 +++++++++++++++++++++++++++++----------
src/radeon_probe.h | 1
src/radeon_reg.h | 38 +++++++++--------
src/radeon_textured_videofuncs.c | 22 ++++-----
src/radeon_version.h | 1
18 files changed, 264 insertions(+), 227 deletions(-)
New commits:
commit 248b435ae63d7122971a8021f8aa8e0963d8a850
Author: Alex Deucher <alexdeuc...@gmail.com>
Date: Fri May 8 12:55:26 2009 -0400
R3xx/R4xx tex vid: increase the guardband limit for rendering with a tri
limit goes from 2880 to 4021 now that we've switched to 1/12 subpixel mode.
This allows us to render with a clipped tri at higher resolutions preventing
diagonal tearing.
diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c
index a88d0ab..9f7cd4c 100644
--- a/src/radeon_textured_videofuncs.c
+++ b/src/radeon_textured_videofuncs.c
@@ -2014,7 +2014,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn,
RADEONPortPrivPtr pPriv
* We render a single, large triangle and use the scissor
* functionality to restrict it to the desired rectangle.
* Due to guardband limits on r3xx/r4xx, we can only use
- * the single triangle up to 2880 pixels; above that we
+ * the single triangle up to 4021 pixels; above that we
* render as a quad.
*/
@@ -2041,7 +2041,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn,
RADEONPortPrivPtr pPriv
#endif
if (IS_R300_3D || IS_R500_3D) {
- if (IS_R300_3D && ((dstw+dsth) > 2880))
+ if (IS_R300_3D && ((dstw+dsth) > 4021))
use_quad = TRUE;
/*
* Set up the scissor area to that of the output size.
commit cd03bc17ccb30f1598af61c455b623c14ea42e6b
Author: Alex Deucher <alexdeuc...@gmail.com>
Date: Fri May 8 12:54:00 2009 -0400
r3xx-r5xx: switch to 1/12 subpixel precision
- based on similar patch in Jerome's cs ddx tree
- also fix clipping offsets
- should eventually allow for 4k render targets
- mesa driver uses 1/12 mode, this avoids changing the
subpixel mode when switching between ddx and mesa
diff --git a/src/radeon_accel.c b/src/radeon_accel.c
index 70347fe..f90b386 100644
--- a/src/radeon_accel.c
+++ b/src/radeon_accel.c
@@ -493,7 +493,7 @@ void RADEONEngineInit(ScrnInfoPtr pScrn)
"num quad-pipes is %d\n", info->accel_state->num_gb_pipes);
if (IS_R300_3D || IS_R500_3D) {
- uint32_t gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 |
R300_SUBPIXEL_1_16);
+ uint32_t gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
switch(info->accel_state->num_gb_pipes) {
case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
diff --git a/src/radeon_commonfuncs.c b/src/radeon_commonfuncs.c
index a9bc7d2..13b6533 100644
--- a/src/radeon_commonfuncs.c
+++ b/src/radeon_commonfuncs.c
@@ -69,7 +69,7 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr pScrn)
OUT_ACCEL_REG(RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN |
RADEON_WAIT_3D_IDLECLEAN);
FINISH_ACCEL();
- gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 |
R300_SUBPIXEL_1_16);
+ gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
switch(info->accel_state->num_gb_pipes) {
case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
@@ -105,21 +105,21 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr
pScrn)
OUT_ACCEL_REG(R300_GB_AA_CONFIG, 0);
OUT_ACCEL_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_DC_FLUSH_3D |
R300_DC_FREE_3D);
OUT_ACCEL_REG(R300_RB3D_ZCACHE_CTLSTAT, R300_ZC_FLUSH | R300_ZC_FREE);
- OUT_ACCEL_REG(R300_GB_MSPOS0, ((8 << R300_MS_X0_SHIFT) |
- (8 << R300_MS_Y0_SHIFT) |
- (8 << R300_MS_X1_SHIFT) |
- (8 << R300_MS_Y1_SHIFT) |
- (8 << R300_MS_X2_SHIFT) |
- (8 << R300_MS_Y2_SHIFT) |
- (8 << R300_MSBD0_Y_SHIFT) |
- (7 << R300_MSBD0_X_SHIFT)));
- OUT_ACCEL_REG(R300_GB_MSPOS1, ((8 << R300_MS_X3_SHIFT) |
- (8 << R300_MS_Y3_SHIFT) |
- (8 << R300_MS_X4_SHIFT) |
- (8 << R300_MS_Y4_SHIFT) |
- (8 << R300_MS_X5_SHIFT) |
- (8 << R300_MS_Y5_SHIFT) |
- (8 << R300_MSBD1_SHIFT)));
+ OUT_ACCEL_REG(R300_GB_MSPOS0, ((6 << R300_MS_X0_SHIFT) |
+ (6 << R300_MS_Y0_SHIFT) |
+ (6 << R300_MS_X1_SHIFT) |
+ (6 << R300_MS_Y1_SHIFT) |
+ (6 << R300_MS_X2_SHIFT) |
+ (6 << R300_MS_Y2_SHIFT) |
+ (6 << R300_MSBD0_Y_SHIFT) |
+ (6 << R300_MSBD0_X_SHIFT)));
+ OUT_ACCEL_REG(R300_GB_MSPOS1, ((6 << R300_MS_X3_SHIFT) |
+ (6 << R300_MS_Y3_SHIFT) |
+ (6 << R300_MS_X4_SHIFT) |
+ (6 << R300_MS_Y4_SHIFT) |
+ (6 << R300_MS_X5_SHIFT) |
+ (6 << R300_MS_Y5_SHIFT) |
+ (6 << R300_MSBD1_SHIFT)));
FINISH_ACCEL();
BEGIN_ACCEL(5);
@@ -552,10 +552,10 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr
pScrn)
OUT_ACCEL_REG(R300_SC_EDGERULE, 0xA5294A5);
if (IS_R300_3D) {
/* clip has offset 1440 */
- OUT_ACCEL_REG(R300_SC_CLIP_0_A, ((1088 << R300_CLIP_X_SHIFT) |
- (1088 << R300_CLIP_Y_SHIFT)));
- OUT_ACCEL_REG(R300_SC_CLIP_0_B, (((1080 + 2920) <<
R300_CLIP_X_SHIFT) |
- ((1080 + 2920) <<
R300_CLIP_Y_SHIFT)));
+ OUT_ACCEL_REG(R300_SC_CLIP_0_A, ((1440 << R300_CLIP_X_SHIFT) |
+ (1440 << R300_CLIP_Y_SHIFT)));
+ OUT_ACCEL_REG(R300_SC_CLIP_0_B, ((4080 << R300_CLIP_X_SHIFT) |
+ (4080 << R300_CLIP_Y_SHIFT)));
} else {
OUT_ACCEL_REG(R300_SC_CLIP_0_A, ((0 << R300_CLIP_X_SHIFT) |
(0 << R300_CLIP_Y_SHIFT)));
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
index 0724bc8..effcd89 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
@@ -1933,8 +1933,12 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op,
PicturePtr pSrcPicture,
/* Clear out scissoring */
BEGIN_ACCEL(2);
- OUT_ACCEL_REG(R300_SC_SCISSOR0, ((0 << R300_SCISSOR_X_SHIFT) |
- (0 << R300_SCISSOR_Y_SHIFT)));
+ if (IS_R300_3D)
+ OUT_ACCEL_REG(R300_SC_SCISSOR0, ((1440 << R300_SCISSOR_X_SHIFT) |
+ (1440 << R300_SCISSOR_Y_SHIFT)));
+ else
+ OUT_ACCEL_REG(R300_SC_SCISSOR0, ((0 << R300_SCISSOR_X_SHIFT) |
+ (0 << R300_SCISSOR_Y_SHIFT)));
OUT_ACCEL_REG(R300_SC_SCISSOR1, ((8191 << R300_SCISSOR_X_SHIFT) |
(8191 << R300_SCISSOR_Y_SHIFT)));
FINISH_ACCEL();
diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c
index 7260356..a88d0ab 100644
--- a/src/radeon_textured_videofuncs.c
+++ b/src/radeon_textured_videofuncs.c
@@ -2049,10 +2049,10 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr
pScrn, RADEONPortPrivPtr pPriv
BEGIN_ACCEL(2);
if (IS_R300_3D) {
/* R300 has an offset */
- OUT_ACCEL_REG(R300_SC_SCISSOR0, (((dstX + 1088) <<
R300_SCISSOR_X_SHIFT) |
- ((dstY + 1088) <<
R300_SCISSOR_Y_SHIFT)));
- OUT_ACCEL_REG(R300_SC_SCISSOR1, (((dstX + dstw + 1088 - 1) <<
R300_SCISSOR_X_SHIFT) |
- ((dstY + dsth + 1088 - 1) <<
R300_SCISSOR_Y_SHIFT)));
+ OUT_ACCEL_REG(R300_SC_SCISSOR0, (((dstX + 1440) <<
R300_SCISSOR_X_SHIFT) |
+ ((dstY + 1440) <<
R300_SCISSOR_Y_SHIFT)));
+ OUT_ACCEL_REG(R300_SC_SCISSOR1, (((dstX + dstw + 1440 - 1) <<
R300_SCISSOR_X_SHIFT) |
+ ((dstY + dsth + 1440 - 1) <<
R300_SCISSOR_Y_SHIFT)));
} else {
OUT_ACCEL_REG(R300_SC_SCISSOR0, (((dstX) <<
R300_SCISSOR_X_SHIFT) |
((dstY) <<
R300_SCISSOR_Y_SHIFT)));
commit 26472556fcbbf13e2e4ac2355d587651d6c8f662
Author: Alex Deucher <alexdeuc...@gmail.com>
Date: Fri May 8 12:37:47 2009 -0400
R3xx-R5xx: don't set TX_OFFSET_RS in RS_INST_COUNT
Isn't necessary and seems to cause problems for RS690 users
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
index 571204a..0724bc8 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
@@ -1492,7 +1492,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op,
PicturePtr pSrcPicture,
R300_RS_COUNT_HIRES_EN));
/* R300_INST_COUNT_RS - highest RS instruction used */
- OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(1) |
R300_TX_OFFSET_RS(6));
+ OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(1));
OUT_ACCEL_REG(R300_US_CODE_OFFSET, (R300_ALU_CODE_OFFSET(0) |
R300_ALU_CODE_SIZE(0) |
@@ -1514,7 +1514,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op,
PicturePtr pSrcPicture,
((2 << R300_RS_COUNT_IT_COUNT_SHIFT) |
R300_RS_COUNT_HIRES_EN));
- OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0) |
R300_TX_OFFSET_RS(6));
+ OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0));
OUT_ACCEL_REG(R300_US_CODE_OFFSET, (R300_ALU_CODE_OFFSET(0) |
R300_ALU_CODE_SIZE(0) |
@@ -1741,7 +1741,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op,
PicturePtr pSrcPicture,
R300_RS_COUNT_HIRES_EN));
/* 2 RS instructions: 1 for tex0 (src), 1 for tex1 (mask) */
- OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(1) |
R300_TX_OFFSET_RS(6));
+ OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(1));
OUT_ACCEL_REG(R500_US_CODE_ADDR, (R500_US_CODE_START_ADDR(0) |
R500_US_CODE_END_ADDR(2)));
@@ -1753,7 +1753,7 @@ static Bool FUNC_NAME(R300PrepareComposite)(int op,
PicturePtr pSrcPicture,
((2 << R300_RS_COUNT_IT_COUNT_SHIFT) |
R300_RS_COUNT_HIRES_EN));
- OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0) |
R300_TX_OFFSET_RS(6));
+ OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0));
OUT_ACCEL_REG(R500_US_CODE_ADDR, (R500_US_CODE_START_ADDR(0) |
R500_US_CODE_END_ADDR(1)));
diff --git a/src/radeon_textured_videofuncs.c b/src/radeon_textured_videofuncs.c
index 6cb2870..7260356 100644
--- a/src/radeon_textured_videofuncs.c
+++ b/src/radeon_textured_videofuncs.c
@@ -393,7 +393,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn,
RADEONPortPrivPtr pPriv
R300_RS_COUNT_HIRES_EN));
/* R300_INST_COUNT_RS - highest RS instruction used */
- OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(1) |
R300_TX_OFFSET_RS(6));
+ OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(1));
/* Pixel stack frame size. */
OUT_ACCEL_REG(R300_US_PIXSIZE, 5);
@@ -770,7 +770,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn,
RADEONPortPrivPtr pPriv
((2 << R300_RS_COUNT_IT_COUNT_SHIFT) |
R300_RS_COUNT_HIRES_EN));
/* R300_INST_COUNT_RS - highest RS instruction used */
- OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0) |
R300_TX_OFFSET_RS(6));
+ OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0));
OUT_ACCEL_REG(R300_US_PIXSIZE, 2); /* highest temp used */
@@ -902,7 +902,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn,
RADEONPortPrivPtr pPriv
((2 << R300_RS_COUNT_IT_COUNT_SHIFT) |
R300_RS_COUNT_HIRES_EN));
/* R300_INST_COUNT_RS - highest RS instruction used */
- OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0) |
R300_TX_OFFSET_RS(6));
+ OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0));
OUT_ACCEL_REG(R300_US_PIXSIZE, 0); /* highest temp used */
@@ -975,7 +975,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn,
RADEONPortPrivPtr pPriv
R300_RS_COUNT_HIRES_EN));
/* R300_INST_COUNT_RS - highest RS instruction used */
- OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(1) |
R300_TX_OFFSET_RS(6));
+ OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(1));
/* Pixel stack frame size. */
OUT_ACCEL_REG(R300_US_PIXSIZE, 5);
@@ -1447,7 +1447,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn,
RADEONPortPrivPtr pPriv
R300_RS_COUNT_HIRES_EN));
/* R300_INST_COUNT_RS - highest RS instruction used */
- OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0) |
R300_TX_OFFSET_RS(6));
+ OUT_ACCEL_REG(R300_RS_INST_COUNT, R300_INST_COUNT_RS(0));
/* Pixel stack frame size. */
OUT_ACCEL_REG(R300_US_PIXSIZE, 0); /* highest temp used */
commit 96667eebd8c7949873d63454746129d270bb36e5
Author: Alex Deucher <alexdeuc...@gmail.com>
Date: Sun May 3 13:09:39 2009 -0400
RS690: gpio/connector fixes
Fixes bug 21521
diff --git a/src/radeon_atombios.c b/src/radeon_atombios.c
index 1dde10d..10158a8 100644
--- a/src/radeon_atombios.c
+++ b/src/radeon_atombios.c
@@ -1535,19 +1535,6 @@ static void RADEONApplyATOMQuirks(ScrnInfoPtr pScrn, int
index)
}
}
- /* Acer board, gpios for DFPs are not off by one */
- if ((info->Chipset == PCI_CHIP_RS690_791E) &&
- (PCI_SUB_VENDOR_ID(info->PciInfo) == 0x105b) &&
- (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x0e0b)) {
- if (index == ATOM_DEVICE_DFP3_INDEX) {
- info->BiosConnector[index].ConnectorType = CONNECTOR_DVI_I;
- info->BiosConnector[index].output_id = 0;
- info->BiosConnector[index].ddc_i2c =
RADEONLookupGPIOLineForDDC(pScrn, 0);
- }
- if (index == ATOM_DEVICE_DFP2_INDEX)
- info->BiosConnector[index].ddc_i2c =
RADEONLookupGPIOLineForDDC(pScrn, 1);
- }
-
/* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
if ((info->Chipset == PCI_CHIP_RS600_7941) &&
(PCI_SUB_VENDOR_ID(info->PciInfo) == 0x147b) &&
@@ -2254,12 +2241,14 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable
(ScrnInfoPtr pScrn)
info->BiosConnector[i].ddc_i2c.valid = FALSE;
else if ((info->ChipFamily == CHIP_FAMILY_RS690) ||
(info->ChipFamily == CHIP_FAMILY_RS740)) {
- /* IGP DFP ports use non-standard gpio entries */
- if ((i == ATOM_DEVICE_DFP2_INDEX) || (i == ATOM_DEVICE_DFP3_INDEX))
{
+ /* IGP DFP ports sometimes use non-standard gpio entries */
+ if ((i == ATOM_DEVICE_DFP2_INDEX) &&
(ci.sucI2cId.sbfAccess.bfI2C_LineMux == 2))
info->BiosConnector[i].ddc_i2c =
RADEONLookupGPIOLineForDDC(pScrn,
ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1);
- info->BiosConnector[i].output_id =
ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1;
- } else
+ else if ((i == ATOM_DEVICE_DFP3_INDEX) &&
(ci.sucI2cId.sbfAccess.bfI2C_LineMux == 1))
+ info->BiosConnector[i].ddc_i2c =
+ RADEONLookupGPIOLineForDDC(pScrn,
ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1);
+ else
info->BiosConnector[i].ddc_i2c =
RADEONLookupGPIOLineForDDC(pScrn,
ci.sucI2cId.sbfAccess.bfI2C_LineMux);
} else
@@ -2318,6 +2307,8 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable
(ScrnInfoPtr pScrn)
((j == ATOM_DEVICE_CRT1_INDEX) ||
(j == ATOM_DEVICE_CRT2_INDEX))) {
info->BiosConnector[i].devices |=
info->BiosConnector[j].devices;
+ if (info->BiosConnector[i].ConnectorType ==
CONNECTOR_DVI_D)
+ info->BiosConnector[i].ConnectorType =
CONNECTOR_DVI_I;
info->BiosConnector[j].valid = FALSE;
} else if (((j == ATOM_DEVICE_DFP1_INDEX) ||
(j == ATOM_DEVICE_DFP2_INDEX) ||
@@ -2325,6 +2316,8 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable
(ScrnInfoPtr pScrn)
((i == ATOM_DEVICE_CRT1_INDEX) ||
(i == ATOM_DEVICE_CRT2_INDEX))) {
info->BiosConnector[j].devices |=
info->BiosConnector[i].devices;
+ if (info->BiosConnector[j].ConnectorType ==
CONNECTOR_DVI_D)
+ info->BiosConnector[j].ConnectorType =
CONNECTOR_DVI_I;
info->BiosConnector[i].valid = FALSE;
} else {
info->BiosConnector[i].shared_ddc = TRUE;
commit faa782c7a56de99900c9b3f54714f010ce73dcf3
Author: Alex Deucher <alexdeuc...@gmail.com>
Date: Thu Apr 16 11:58:19 2009 -0400
RS690/RS740: fix connector enumeration in some cases
Should fix Masta-G's issue reported on IRC.
diff --git a/src/radeon_atombios.c b/src/radeon_atombios.c
index b2332bb..1dde10d 100644
--- a/src/radeon_atombios.c
+++ b/src/radeon_atombios.c
@@ -2255,10 +2255,11 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable
(ScrnInfoPtr pScrn)
else if ((info->ChipFamily == CHIP_FAMILY_RS690) ||
(info->ChipFamily == CHIP_FAMILY_RS740)) {
/* IGP DFP ports use non-standard gpio entries */
- if ((i == ATOM_DEVICE_DFP2_INDEX) || (i == ATOM_DEVICE_DFP3_INDEX))
+ if ((i == ATOM_DEVICE_DFP2_INDEX) || (i == ATOM_DEVICE_DFP3_INDEX))
{
info->BiosConnector[i].ddc_i2c =
RADEONLookupGPIOLineForDDC(pScrn,
ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1);
- else
+ info->BiosConnector[i].output_id =
ci.sucI2cId.sbfAccess.bfI2C_LineMux + 1;
+ } else
info->BiosConnector[i].ddc_i2c =
RADEONLookupGPIOLineForDDC(pScrn,
ci.sucI2cId.sbfAccess.bfI2C_LineMux);
} else
commit f2c0fa5e3d96f1bcc916e1a36268bdc7acd4cda7
Author: Alex Deucher <alexdeuc...@gmail.com>
Date: Wed May 6 12:24:35 2009 -0400
AVIVO: set default cursor mode in cursor init
Should fix bug 21557
diff --git a/src/radeon_cursor.c b/src/radeon_cursor.c
index 59df132..5ecdfad 100644
--- a/src/radeon_cursor.c
+++ b/src/radeon_cursor.c
@@ -342,23 +342,17 @@ Bool RADEONCursorInit(ScreenPtr pScreen)
{
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
RADEONInfoPtr info = RADEONPTR(pScrn);
+ unsigned char *RADEONMMIO = info->MMIO;
xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
- int width;
- int width_bytes;
- int height;
- int size_bytes;
int c;
- size_bytes = CURSOR_WIDTH * 4 * CURSOR_HEIGHT;
- width = pScrn->displayWidth;
- width_bytes = width * (pScrn->bitsPerPixel / 8);
- height = ((size_bytes * xf86_config->num_crtc) + width_bytes - 1) /
width_bytes;
- int align = IS_AVIVO_VARIANT ? 4096 : 256;
+ for (c = 0; c < xf86_config->num_crtc; c++) {
+ xf86CrtcPtr crtc = xf86_config->crtc[c];
+ RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
- if (!info->useEXA) {
- for (c = 0; c < xf86_config->num_crtc; c++) {
- xf86CrtcPtr crtc = xf86_config->crtc[c];
- RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
+ if (!info->useEXA) {
+ int size_bytes = CURSOR_WIDTH * 4 * CURSOR_HEIGHT;
+ int align = IS_AVIVO_VARIANT ? 4096 : 256;
radeon_crtc->cursor_offset =
radeon_legacy_allocate_memory(pScrn, &radeon_crtc->cursor_mem,
size_bytes, align);
@@ -372,6 +366,10 @@ Bool RADEONCursorInit(ScreenPtr pScreen)
c,
(unsigned int)radeon_crtc->cursor_offset);
}
+ /* set the cursor mode the same on both crtcs to avoid corruption */
+ if (IS_AVIVO_VARIANT)
+ OUTREG(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset,
+ (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT));
}
return xf86_cursors_init (pScreen, CURSOR_WIDTH, CURSOR_HEIGHT,
commit b6cd47ec007af2022af180f537a7ba01244b2c88
Author: Alex Deucher <alexdeuc...@gmail.com>
Date: Fri May 8 12:21:33 2009 -0400
AVIVO: fix cursor corruption bands for real
Don't have to leave both cursors enabled, just have to use
the same mode for both cursors whether or not they are enabled.
diff --git a/src/radeon_cursor.c b/src/radeon_cursor.c
index 4f646bc..59df132 100644
--- a/src/radeon_cursor.c
+++ b/src/radeon_cursor.c
@@ -100,7 +100,10 @@ avivo_setup_cursor(xf86CrtcPtr crtc, Bool enable)
RADEONInfoPtr info = RADEONPTR(crtc->scrn);
unsigned char *RADEONMMIO = info->MMIO;
- OUTREG(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset, 0);
+ /* always use the same cursor mode even if the cursor is disabled,
+ * otherwise you may end up with cursor curruption bands
+ */
+ OUTREG(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset,
(AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT));
if (enable) {
OUTREG(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
@@ -156,7 +159,6 @@ radeon_crtc_show_cursor (xf86CrtcPtr crtc)
OUTREGP(RADEON_MM_DATA, RADEON_CRTC_CUR_EN | 2 << 20,
~(RADEON_CRTC_CUR_EN | RADEON_CRTC_CUR_MODE_MASK));
}
- radeon_crtc->cursor_enabled = TRUE;
}
void
@@ -169,18 +171,7 @@ radeon_crtc_hide_cursor (xf86CrtcPtr crtc)
unsigned char *RADEONMMIO = info->MMIO;
if (IS_AVIVO_VARIANT) {
- DisplayModePtr mode = &crtc->mode;
-
avivo_lock_cursor(crtc, TRUE);
- /* Set position offscreen. This will prevent the cursor
- * from showing up even if it's enabled to work-around
- * corruption issues.
- */
- if (mode) {
- OUTREG(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset,
- ((crtc->x + mode->CrtcHDisplay) << 16) | (crtc->y +
mode->CrtcVDisplay));
- OUTREG(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, 0);
- }
avivo_setup_cursor(crtc, FALSE);
avivo_lock_cursor(crtc, FALSE);
} else {
@@ -197,13 +188,13 @@ radeon_crtc_hide_cursor (xf86CrtcPtr crtc)
OUTREGP(RADEON_MM_DATA, 0, ~RADEON_CRTC_CUR_EN);
}
- radeon_crtc->cursor_enabled = FALSE;
}
void
radeon_crtc_set_cursor_position (xf86CrtcPtr crtc, int x, int y)
{
ScrnInfoPtr pScrn = crtc->scrn;
+ RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
int crtc_id = radeon_crtc->crtc_id;
RADEONInfoPtr info = RADEONPTR(pScrn);
@@ -218,9 +209,7 @@ radeon_crtc_set_cursor_position (xf86CrtcPtr crtc, int x,
int y)
if (yorigin >= CURSOR_HEIGHT) yorigin = CURSOR_HEIGHT - 1;
if (IS_AVIVO_VARIANT) {
- xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
int w = CURSOR_WIDTH;
- int i;
/* avivo cursor spans the full fb width */
if (crtc->rotatedData == NULL) {
@@ -228,15 +217,8 @@ radeon_crtc_set_cursor_position (xf86CrtcPtr crtc, int x,
int y)
y += crtc->y;
}
- for (i = 0; i < xf86_config->num_crtc; i++) {
- xf86CrtcPtr crtc = xf86_config->crtc[i];
- RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
-
- if (!radeon_crtc->enabled)
- break;
- }
-
- if (i == xf86_config->num_crtc) {
+ if (pRADEONEnt->Controller[0]->enabled &&
+ pRADEONEnt->Controller[1]->enabled) {
int cursor_end, frame_end;
cursor_end = x - xorigin + w;
@@ -252,22 +234,6 @@ radeon_crtc_set_cursor_position (xf86CrtcPtr crtc, int x,
int y)
}
if (w <= 0)
w = 1;
-
- /* both cursors should be enabled when dualhead is active
- * or you may get corruption bands
- */
- if (!pRADEONEnt->Controller[0]->cursor_enabled) {
- avivo_lock_cursor(pRADEONEnt->pCrtc[0], TRUE);
- avivo_setup_cursor(pRADEONEnt->pCrtc[0], TRUE);
- avivo_lock_cursor(pRADEONEnt->pCrtc[0], FALSE);
- pRADEONEnt->Controller[0]->cursor_enabled = TRUE;
- }
- if (!pRADEONEnt->Controller[1]->cursor_enabled) {
- avivo_lock_cursor(pRADEONEnt->pCrtc[1], TRUE);
- avivo_setup_cursor(pRADEONEnt->pCrtc[1], TRUE);
- avivo_lock_cursor(pRADEONEnt->pCrtc[1], FALSE);
- pRADEONEnt->Controller[1]->cursor_enabled = TRUE;
- }
}
avivo_lock_cursor(crtc, TRUE);
diff --git a/src/radeon_probe.h b/src/radeon_probe.h
index dbccd85..3e4f47c 100644
--- a/src/radeon_probe.h
+++ b/src/radeon_probe.h
@@ -159,7 +159,6 @@ typedef struct _RADEONCrtcPrivateRec {
int can_tile;
Bool enabled;
Bool initialized;
- Bool cursor_enabled;
} RADEONCrtcPrivateRec, *RADEONCrtcPrivatePtr;
typedef struct _radeon_encoder {
commit cb8081a8e70b3354037f8ca99380288fe2eb9828
Author: Alex Deucher <alexdeuc...@gmail.com>
Date: Mon May 4 12:57:36 2009 -0400
AVIVO: move cusor offscreen when disabling
Adapted from Yang's patch. Setting size to zero is
actually a 1x1 cursor.
diff --git a/src/radeon_cursor.c b/src/radeon_cursor.c
index 96df1d7..4f646bc 100644
--- a/src/radeon_cursor.c
+++ b/src/radeon_cursor.c
@@ -169,13 +169,18 @@ radeon_crtc_hide_cursor (xf86CrtcPtr crtc)
unsigned char *RADEONMMIO = info->MMIO;
if (IS_AVIVO_VARIANT) {
+ DisplayModePtr mode = &crtc->mode;
+
avivo_lock_cursor(crtc, TRUE);
- /* set size to zero as proper size will get set in
- * set_cursor_postion(). This will prevent the cursor
+ /* Set position offscreen. This will prevent the cursor
* from showing up even if it's enabled to work-around
* corruption issues.
*/
- OUTREG(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset, 0);
+ if (mode) {
+ OUTREG(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset,
+ ((crtc->x + mode->CrtcHDisplay) << 16) | (crtc->y +
mode->CrtcVDisplay));
+ OUTREG(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, 0);
+ }
avivo_setup_cursor(crtc, FALSE);
avivo_lock_cursor(crtc, FALSE);
} else {
commit 0e49efbe8c271c26cec4dfca063c73755dc2d25f
Author: Alex Deucher <alexdeuc...@gmail.com>
Date: Sun May 3 18:52:00 2009 -0400
r2xx-r4xx: fix typo in last i2c fix and clarify hw i2c pin sel
diff --git a/src/radeon_output.c b/src/radeon_output.c
index 67d94fe..ee8de6a 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -1656,12 +1656,12 @@ RADEONI2CDoLock(xf86OutputPtr output, I2CBusPtr b, int
lock_state)
* holds the i2c port in a bad state - switch hw i2c away before
* doing DDC - do this for all r200s/r300s for safety sakes */
if ((info->ChipFamily >= CHIP_FAMILY_R200) && (!IS_AVIVO_VARIANT)) {
- if (pRADEONI2CBus->mask_clk_reg == RADEON_GPIO_CRT2_DDC)
+ if (pRADEONI2CBus->mask_clk_reg == RADEON_GPIO_MONID)
OUTREG(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
-
R200_DVI_I2C_PIN_SEL(R200_SEL_DVI_DDC)));
+
R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1)));
else
OUTREG(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST |
-
R200_DVI_I2C_PIN_SEL(R200_SEL_CRT2_DDC)));
+
R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3)));
}
temp = INREG(pRADEONI2CBus->a_clk_reg);
diff --git a/src/radeon_reg.h b/src/radeon_reg.h
index c0d34d1..914fe51 100644
--- a/src/radeon_reg.h
+++ b/src/radeon_reg.h
@@ -936,11 +936,11 @@
#define RADEON_GENMO_WT 0x03c2 /* VGA */
#define RADEON_GENS0 0x03c2 /* VGA */
#define RADEON_GENS1 0x03da /* VGA, 0x03ba */
-#define RADEON_GPIO_MONID 0x0068 /* DDC interface via I2C */
+#define RADEON_GPIO_MONID 0x0068 /* DDC interface via I2C */
/* DDC3 */
#define RADEON_GPIO_MONIDB 0x006c
#define RADEON_GPIO_CRT2_DDC 0x006c
-#define RADEON_GPIO_DVI_DDC 0x0064
-#define RADEON_GPIO_VGA_DDC 0x0060
+#define RADEON_GPIO_DVI_DDC 0x0064 /* DDC2 */
+#define RADEON_GPIO_VGA_DDC 0x0060 /* DDC1 */
# define RADEON_GPIO_A_0 (1 << 0)
# define RADEON_GPIO_A_1 (1 << 1)
# define RADEON_GPIO_Y_0 (1 << 8)
@@ -997,9 +997,9 @@
#define RADEON_DVI_I2C_CNTL_0 0x02e0
# define R200_DVI_I2C_PIN_SEL(x) ((x) << 3)
-# define R200_SEL_DVI_DDC 0
-# define R200_SEL_VGA_DDC 1
-# define R200_SEL_CRT2_DDC 2
+# define R200_SEL_DDC1 0 /* 0x60 - VGA_DDC */
+# define R200_SEL_DDC2 1 /* 0x64 - DVI_DDC */
+# define R200_SEL_DDC3 2 /* 0x68 - MONID_DDC */
#define RADEON_DVI_I2C_CNTL_1 0x02e4
#define RADEON_DVI_I2C_DATA 0x02e8
commit 421085949e195596000e37ea6693489db7c075b5
Author: Alex Deucher <alexdeuc...@gmail.com>
Date: Wed Apr 29 12:38:15 2009 -0400
radeon: fix several dpms issues
- atom dpms was unblanking for standby/suspend
- return if r600+ in radeon_crtc_modeset_ioctl()
- remove seprate standby/suspend handling in legacy
crtc dpms. we turn the outputs off, so turn the
crtcs off too.
- disable the crtcs in legacy crtc dpms
- move radeon_crtc_modeset_ioctl() calls to radeon_crtc_dpms()
so they will get called for both atom and legacy paths
Should fix bug 21321
diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c
index 31c032b..f060d8d 100644
--- a/src/atombios_crtc.c
+++ b/src/atombios_crtc.c
@@ -167,13 +167,13 @@ atombios_crtc_dpms(xf86CrtcPtr crtc, int mode)
RADEONInfoPtr info = RADEONPTR(crtc->scrn);
switch (mode) {
case DPMSModeOn:
- case DPMSModeStandby:
- case DPMSModeSuspend:
if (IS_DCE3_VARIANT)
atombios_enable_crtc_memreq(info->atomBIOS, radeon_crtc->crtc_id,
1);
atombios_enable_crtc(info->atomBIOS, radeon_crtc->crtc_id, 1);
atombios_blank_crtc(info->atomBIOS, radeon_crtc->crtc_id, 0);
break;
+ case DPMSModeStandby:
+ case DPMSModeSuspend:
case DPMSModeOff:
atombios_blank_crtc(info->atomBIOS, radeon_crtc->crtc_id, 1);
atombios_enable_crtc(info->atomBIOS, radeon_crtc->crtc_id, 0);
diff --git a/src/legacy_crtc.c b/src/legacy_crtc.c
index 829b453..5ea13bc 100644
--- a/src/legacy_crtc.c
+++ b/src/legacy_crtc.c
@@ -649,6 +649,9 @@ radeon_crtc_modeset_ioctl(xf86CrtcPtr crtc, Bool post)
if (!info->directRenderingEnabled)
return;
+ if (info->ChipFamily >= CHIP_FAMILY_R600)
+ return;
+
modeset.crtc = radeon_crtc->crtc_id;
modeset.cmd = post ? _DRM_POST_MODESET : _DRM_PRE_MODESET;
@@ -661,55 +664,42 @@ radeon_crtc_modeset_ioctl(xf86CrtcPtr crtc, Bool post)
void
legacy_crtc_dpms(xf86CrtcPtr crtc, int mode)
{
- int mask;
+ uint32_t mask;
RADEONCrtcPrivatePtr radeon_crtc = crtc->driver_private;
RADEONEntPtr pRADEONEnt = RADEONEntPriv(crtc->scrn);
unsigned char *RADEONMMIO = pRADEONEnt->MMIO;
- mask = radeon_crtc->crtc_id ? (RADEON_CRTC2_DISP_DIS |
RADEON_CRTC2_VSYNC_DIS | RADEON_CRTC2_HSYNC_DIS | RADEON_CRTC2_DISP_REQ_EN_B) :
(RADEON_CRTC_DISPLAY_DIS | RADEON_CRTC_HSYNC_DIS | RADEON_CRTC_VSYNC_DIS);
-
- if (mode == DPMSModeOff)
- radeon_crtc_modeset_ioctl(crtc, FALSE);
+ if (radeon_crtc->crtc_id)
+ mask = (RADEON_CRTC2_EN |
+ RADEON_CRTC2_DISP_DIS |
+ RADEON_CRTC2_VSYNC_DIS |
+ RADEON_CRTC2_HSYNC_DIS |
+ RADEON_CRTC2_DISP_REQ_EN_B);
+ else
+ mask = (RADEON_CRTC_DISPLAY_DIS |
+ RADEON_CRTC_HSYNC_DIS |
+ RADEON_CRTC_VSYNC_DIS);
switch(mode) {
case DPMSModeOn:
if (radeon_crtc->crtc_id) {
- OUTREGP(RADEON_CRTC2_GEN_CNTL, 0, ~mask);
+ OUTREGP(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~mask);
} else {
- OUTREGP(RADEON_CRTC_GEN_CNTL, 0, ~RADEON_CRTC_DISP_REQ_EN_B);
+ OUTREGP(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN |
RADEON_CRTC_DISP_REQ_EN_B));
OUTREGP(RADEON_CRTC_EXT_CNTL, 0, ~mask);
}
break;
case DPMSModeStandby:
- if (radeon_crtc->crtc_id) {
- OUTREGP(RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_DISP_DIS |
RADEON_CRTC2_HSYNC_DIS), ~mask);
- } else {
- OUTREGP(RADEON_CRTC_GEN_CNTL, 0, ~RADEON_CRTC_DISP_REQ_EN_B);
- OUTREGP(RADEON_CRTC_EXT_CNTL, (RADEON_CRTC_DISPLAY_DIS |
RADEON_CRTC_HSYNC_DIS), ~mask);
- }
- break;
case DPMSModeSuspend:
- if (radeon_crtc->crtc_id) {
- OUTREGP(RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_DISP_DIS |
RADEON_CRTC2_VSYNC_DIS), ~mask);
- } else {
- OUTREGP(RADEON_CRTC_GEN_CNTL, 0, ~RADEON_CRTC_DISP_REQ_EN_B);
- OUTREGP(RADEON_CRTC_EXT_CNTL, (RADEON_CRTC_DISPLAY_DIS |
RADEON_CRTC_VSYNC_DIS), ~mask);
- }
- break;
case DPMSModeOff:
if (radeon_crtc->crtc_id) {
OUTREGP(RADEON_CRTC2_GEN_CNTL, mask, ~mask);
} else {
- OUTREGP(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B,
~RADEON_CRTC_DISP_REQ_EN_B);
+ OUTREGP(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B,
~(RADEON_CRTC_EN | RADEON_CRTC_DISP_REQ_EN_B));
OUTREGP(RADEON_CRTC_EXT_CNTL, mask, ~mask);
}
break;
}
-
- if (mode != DPMSModeOff) {
- radeon_crtc_modeset_ioctl(crtc, TRUE);
- radeon_crtc_load_lut(crtc);
- }
}
@@ -912,7 +902,6 @@ RADEONInitCrtcRegisters(xf86CrtcPtr crtc, RADEONSavePtr
save,
/*save->bios_4_scratch = info->SavedReg->bios_4_scratch;*/
save->crtc_gen_cntl = (RADEON_CRTC_EXT_DISP_EN
- | RADEON_CRTC_EN
| (format << 8)
| ((mode->Flags & V_DBLSCAN)
? RADEON_CRTC_DBL_SCAN_EN
@@ -1160,8 +1149,7 @@ RADEONInitCrtc2Registers(xf86CrtcPtr crtc, RADEONSavePtr
save,
else
save->crtc2_gen_cntl = 0;
- save->crtc2_gen_cntl |= (RADEON_CRTC2_EN
- | (format << 8)
+ save->crtc2_gen_cntl |= ((format << 8)
| RADEON_CRTC2_VSYNC_DIS
| RADEON_CRTC2_HSYNC_DIS
| RADEON_CRTC2_DISP_DIS
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index cd0d55e..6080e7e 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -77,6 +77,9 @@ radeon_crtc_dpms(xf86CrtcPtr crtc, int mode)
if ((mode == DPMSModeOn) && radeon_crtc->enabled)
return;
+ if (mode == DPMSModeOff)
+ radeon_crtc_modeset_ioctl(crtc, FALSE);
+
if (IS_AVIVO_VARIANT || info->r4xx_atom) {
atombios_crtc_dpms(crtc, mode);
} else {
@@ -97,6 +100,11 @@ radeon_crtc_dpms(xf86CrtcPtr crtc, int mode)
}
}
+ if (mode != DPMSModeOff) {
+ radeon_crtc_modeset_ioctl(crtc, TRUE);
+ radeon_crtc_load_lut(crtc);
+ }
+
if (mode == DPMSModeOn)
radeon_crtc->enabled = TRUE;
else
commit fbb04716e4c28347c9e627f3cc78b4420e9abfa0
Author: Alex Deucher <alexdeuc...@gmail.com>
Date: Wed Apr 29 01:55:10 2009 -0400
AVIVO: better fix for cursor flickering/corruption issues
Should prevent ghost cursor from being left on screen.
diff --git a/src/radeon_cursor.c b/src/radeon_cursor.c
index ba2d6ae..96df1d7 100644
--- a/src/radeon_cursor.c
+++ b/src/radeon_cursor.c
@@ -138,25 +138,9 @@ radeon_crtc_show_cursor (xf86CrtcPtr crtc)
unsigned char *RADEONMMIO = info->MMIO;
if (IS_AVIVO_VARIANT) {
- RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
-
- /* both cursors should be enabled when dualhead is active
- * or you may get corruption bands
- */
- if (pRADEONEnt->Controller[0]->enabled &&
- pRADEONEnt->Controller[1]->enabled) {
- avivo_lock_cursor(pRADEONEnt->pCrtc[0], TRUE);
- avivo_setup_cursor(pRADEONEnt->pCrtc[0], TRUE);
- avivo_lock_cursor(pRADEONEnt->pCrtc[0], FALSE);
-
- avivo_lock_cursor(pRADEONEnt->pCrtc[1], TRUE);
- avivo_setup_cursor(pRADEONEnt->pCrtc[1], TRUE);
- avivo_lock_cursor(pRADEONEnt->pCrtc[1], FALSE);
- } else {
- avivo_lock_cursor(crtc, TRUE);
- avivo_setup_cursor(crtc, TRUE);
- avivo_lock_cursor(crtc, FALSE);
- }
+ avivo_lock_cursor(crtc, TRUE);
+ avivo_setup_cursor(crtc, TRUE);
+ avivo_lock_cursor(crtc, FALSE);
} else {
switch (crtc_id) {
case 0:
@@ -172,6 +156,7 @@ radeon_crtc_show_cursor (xf86CrtcPtr crtc)
OUTREGP(RADEON_MM_DATA, RADEON_CRTC_CUR_EN | 2 << 20,
~(RADEON_CRTC_CUR_EN | RADEON_CRTC_CUR_MODE_MASK));
}
+ radeon_crtc->cursor_enabled = TRUE;
}
void
@@ -185,6 +170,12 @@ radeon_crtc_hide_cursor (xf86CrtcPtr crtc)
if (IS_AVIVO_VARIANT) {
avivo_lock_cursor(crtc, TRUE);
+ /* set size to zero as proper size will get set in
+ * set_cursor_postion(). This will prevent the cursor
+ * from showing up even if it's enabled to work-around
+ * corruption issues.
+ */
+ OUTREG(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset, 0);
avivo_setup_cursor(crtc, FALSE);
avivo_lock_cursor(crtc, FALSE);
} else {
@@ -201,6 +192,7 @@ radeon_crtc_hide_cursor (xf86CrtcPtr crtc)
OUTREGP(RADEON_MM_DATA, 0, ~RADEON_CRTC_CUR_EN);
}
+ radeon_crtc->cursor_enabled = FALSE;
}
void
@@ -255,6 +247,22 @@ radeon_crtc_set_cursor_position (xf86CrtcPtr crtc, int x,
int y)
}
if (w <= 0)
w = 1;
+
+ /* both cursors should be enabled when dualhead is active
+ * or you may get corruption bands
+ */
+ if (!pRADEONEnt->Controller[0]->cursor_enabled) {
+ avivo_lock_cursor(pRADEONEnt->pCrtc[0], TRUE);
+ avivo_setup_cursor(pRADEONEnt->pCrtc[0], TRUE);
+ avivo_lock_cursor(pRADEONEnt->pCrtc[0], FALSE);
+ pRADEONEnt->Controller[0]->cursor_enabled = TRUE;
+ }
+ if (!pRADEONEnt->Controller[1]->cursor_enabled) {
+ avivo_lock_cursor(pRADEONEnt->pCrtc[1], TRUE);
+ avivo_setup_cursor(pRADEONEnt->pCrtc[1], TRUE);
+ avivo_lock_cursor(pRADEONEnt->pCrtc[1], FALSE);
+ pRADEONEnt->Controller[1]->cursor_enabled = TRUE;
+ }
}
avivo_lock_cursor(crtc, TRUE);
diff --git a/src/radeon_probe.h b/src/radeon_probe.h
index 3e4f47c..dbccd85 100644
--- a/src/radeon_probe.h
+++ b/src/radeon_probe.h
@@ -159,6 +159,7 @@ typedef struct _RADEONCrtcPrivateRec {
int can_tile;
Bool enabled;
Bool initialized;
+ Bool cursor_enabled;
} RADEONCrtcPrivateRec, *RADEONCrtcPrivatePtr;
typedef struct _radeon_encoder {
commit 666b0ff9f7fd216f7c31315b284c4bf389a51007
Author: Alex Deucher <alexdeuc...@gmail.com>
Date: Wed Apr 29 01:05:31 2009 -0400
R6xx/r7xx: fix CURSOR_SWAPPING_* macros
r6xx/r7xx have different swapper regs
diff --git a/src/radeon_cursor.c b/src/radeon_cursor.c
index ae9c346..ba2d6ae 100644
--- a/src/radeon_cursor.c
+++ b/src/radeon_cursor.c
@@ -73,14 +73,17 @@
#define CURSOR_SWAPPING_DECL_MMIO unsigned char *RADEONMMIO = info->MMIO;
#define CURSOR_SWAPPING_START() \
do { \
+ if (info->ChipFamily < CHIP_FAMILY_R600) \
OUTREG(RADEON_SURFACE_CNTL, \
(info->ModeReg->surface_cntl | \
RADEON_NONSURF_AP0_SWP_32BPP | RADEON_NONSURF_AP1_SWP_32BPP) & \
~(RADEON_NONSURF_AP0_SWP_16BPP | RADEON_NONSURF_AP1_SWP_16BPP)); \
} while (0)
-#define CURSOR_SWAPPING_END() (OUTREG(RADEON_SURFACE_CNTL, \
- info->ModeReg->surface_cntl))
-
+#define CURSOR_SWAPPING_END() \
+ do { \
+ if (info->ChipFamily < CHIP_FAMILY_R600) \
+ OUTREG(RADEON_SURFACE_CNTL, info->ModeReg->surface_cntl); \
+ } while (0)
#else
#define CURSOR_SWAPPING_DECL_MMIO
commit 998fd24417d1e86ad70e15a2f55bb81320b28987
Author: Alex Deucher <alexdeuc...@gmail.com>
Date: Tue Apr 28 19:28:25 2009 -0400
AVIVO: fix cursor corruption/flickering issues
When both crtcs are enabled, both cursors need to be enabled
or you get corruption bands.
Thanks to Yang Zhao for figuring this out.
diff --git a/src/radeon_cursor.c b/src/radeon_cursor.c
index bc9cf19..ae9c346 100644
--- a/src/radeon_cursor.c
+++ b/src/radeon_cursor.c
@@ -135,12 +135,25 @@ radeon_crtc_show_cursor (xf86CrtcPtr crtc)
unsigned char *RADEONMMIO = info->MMIO;
if (IS_AVIVO_VARIANT) {
- avivo_lock_cursor(crtc, TRUE);
- OUTREG(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset,
- INREG(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset)
- | AVIVO_D1CURSOR_EN);
- avivo_setup_cursor(crtc, TRUE);
- avivo_lock_cursor(crtc, FALSE);
+ RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
+
+ /* both cursors should be enabled when dualhead is active
+ * or you may get corruption bands
+ */
+ if (pRADEONEnt->Controller[0]->enabled &&
+ pRADEONEnt->Controller[1]->enabled) {
+ avivo_lock_cursor(pRADEONEnt->pCrtc[0], TRUE);
+ avivo_setup_cursor(pRADEONEnt->pCrtc[0], TRUE);
--
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