ChangeLog | 152 ++++++++++++++++++++++++++++++++++++++
debian/changelog | 7 +
man/radeon.man | 1
src/ati_pciids_gen.h | 1
src/atipciids.h | 3
src/atombios_output.c | 50 +++++++++++-
src/pcidb/ati_pciids.csv | 1
src/radeon.h | 11 +-
src/radeon_atombios.c | 25 +++++-
src/radeon_bios.c | 62 +++++----------
src/radeon_chipinfo_gen.h | 1
src/radeon_chipset_gen.h | 1
src/radeon_crtc.c | 9 ++
src/radeon_cursor.c | 4 -
src/radeon_dri.c | 83 ++++++++++++++++++--
src/radeon_driver.c | 28 ++++---
src/radeon_exa_render.c | 6 +
src/radeon_output.c | 39 ++++++++-
src/radeon_pci_chipset_gen.h | 1
src/radeon_pci_device_match_gen.h | 1
src/radeon_probe.h | 3
src/radeon_textured_video.c | 8 --
22 files changed, 409 insertions(+), 88 deletions(-)
New commits:
commit 863102938ed430f4e4f4dd28036cd669722774f1
Author: Brice Goglin <[EMAIL PROTECTED]>
Date: Sat Nov 29 10:52:43 2008 +0100
Prepare changelog for upload
diff --git a/debian/changelog b/debian/changelog
index baaebb7..7c77737 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,9 +1,9 @@
-xserver-xorg-video-ati (1:6.9.0+git20081129.783cdb73-1) UNRELEASED; urgency=low
+xserver-xorg-video-ati (1:6.9.0+git20081129.783cdb73-1) experimental;
urgency=low
* Pull upstream snapshot, up to commit 783cdb73.
+ Add AGPMode quirk table, closes: #461144, #462590, #467460.
- -- Brice Goglin <[EMAIL PROTECTED]> Sat, 29 Nov 2008 10:50:18 +0100
+ -- Brice Goglin <[EMAIL PROTECTED]> Sat, 29 Nov 2008 10:52:27 +0100
xserver-xorg-video-ati (1:6.9.0+git20081012.c0e6cb6d-1) experimental;
urgency=low
commit 1c2b3c94fa1ba1d193c6f4ec269ea6bf6ada2217
Author: Brice Goglin <[EMAIL PROTECTED]>
Date: Sat Nov 29 10:52:11 2008 +0100
Pull upstream snapshot, up to commit 783cdb73
diff --git a/ChangeLog b/ChangeLog
index b935b07..4c4427d 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,155 @@
+commit 783cdb7374941bb1d2b63eea375fbf2f1b808cc3
+Author: Dave Airlie <[EMAIL PROTECTED]>
+Date: Thu Nov 27 15:29:06 2008 +1000
+
+ r100/r200: EXA misrenders dst == a8 + dst alpha use.
+
+ Fedora BZ#469556
+
+ I've played with various dst and texture formats and rewritten large
+ parts of this to no avail, so I'm punting for now.
+
+commit 2d7cfc421713286edd5121b56999246f9ae70286
+Author: Eygene Ryabinkin <[EMAIL PROTECTED]>
+Date: Tue Nov 25 13:25:33 2008 -0500
+
+ Catch unsubstituted macro for PCI region base access
+
+ also fix up some warnings.
+
+commit af7690b9c300d37c3a0c51e27e0ad2ca009224a2
+Author: Benjamin Herrenschmidt <[EMAIL PROTECTED]>
+Date: Tue Nov 25 02:57:30 2008 -0500
+
+ [PATCH] radeon: Fix PCI usage of 32-bit driver on 64-bit platform
+
+ The radeon driver is storing PCI addresses in unsigned long's which
+ won't work well on 32-bit platforms with 64-bit physical address space
+ such as PowerPC 4xx. This fixes it by using unsigned long long instead.
+
+commit 065938617c0feab17f4274a5350de02a692ba065
+Author: Ramon van der Stelt <[EMAIL PROTECTED]>
+Date: Tue Nov 25 02:23:46 2008 -0500
+
+ Interlaced mode fixes
+
+ see bug 12626
+
+commit 36a7dc6ea1e1929e986ab1159497c71521cb2f10
+Author: Bryce Harrington <[EMAIL PROTECTED]>
+Date: Tue Nov 25 01:04:37 2008 -0500
+
+ Additional AGP quirks
+
+ bug 18693
+
+commit 2acb8e4ed220fccb21b22a53c5142ab3a35d32ef
+Author: Alex Deucher <[EMAIL PROTECTED]>
+Date: Tue Nov 25 15:07:09 2008 +1000
+
+ radeon: fixup shared DDC lines for some rv610 cards.
+
+ Some cards share DDC between a HDMI and VGA output, and expect the
+ driver to use load detect or EDID to figure it out.
+
+ airlied- shipped in RHEL5
+
+ Signed-off-by: Dave Airlie <[EMAIL PROTECTED]>
+
+commit b01e35168de40d192fd7a9ce6884b9c7419afbd4
+Author: Alex Deucher <[EMAIL PROTECTED]>
+Date: Mon Nov 24 21:06:42 2008 -0500
+
+ Fix up posted logic
+
+ noticed by benh on IRC
+
+commit d7a03e93372b17d642b42f5490464616ae7c99c1
+Author: Alex Deucher <[EMAIL PROTECTED]>
+Date: Mon Nov 24 15:52:05 2008 -0500
+
+ Get hardcoded edid from the bios for servers that support it
+
+ should fix bug 11300
+
+commit 3858e31fa9d77d52a5cabb02f53f06385eab40f7
+Author: Alex Deucher <[EMAIL PROTECTED]>
+Date: Mon Nov 24 14:39:41 2008 -0500
+
+ Don't support rotation is accel is not available
+
+ Fixes bug 18068
+
+commit 3d27876d91ef69d71f17b6cf8c07c26bf12857b4
+Author: Dave Airlie <[EMAIL PROTECTED]>
+Date: Mon Nov 10 15:47:13 2008 +1000
+
+ radeon: always align dstPitch to 64 bytes for textured video
+
+ bz# 18454
+
+commit 6c8b352264540ccc4622a7c0b704ce452dcd707d
+Author: Dave Airlie <[EMAIL PROTECTED]>
+Date: Wed Oct 29 15:53:57 2008 +1000
+
+ pciid: add HD3300 - 790GX chipset.
+
+ RH BZ (#466706)
+
+commit 902eaf768142c6c7dcc487e10775027b84cd1f9a
+Author: Alex Deucher <[EMAIL PROTECTED]>
+Date: Thu Nov 6 15:46:43 2008 -0500
+
+ Check for LVDS on all IGP chips
+
+ - fixes bug 18395
+
+commit 44abaa0ea8e5e3bbe833fa73e6d011618bb6d7e7
+Author: Adam Jackson <[EMAIL PROTECTED]>
+Date: Mon Nov 3 15:09:28 2008 -0500
+
+ Fix HDMI output setup on DIG1/DIG2.
+
+ The only reliable way to detect an HDMI sink is to check for the
+ appropriate EDID extension block, so this will only work right on
+ servers with xf86DoEEDID(). RANDR 1.2 will call this internally for
+ us if it exists, but pre-1.6 servers are out of luck.
+
+commit 937b7ac2a259cf504a19dcf62a58b1db1afb8eb9
+Author: Bryce Harrington <[EMAIL PROTECTED]>
+Date: Wed Oct 29 01:31:50 2008 -0400
+
+ Add AGP quirk table
+
+ - set known good default agp modes for problematic chip/bridge combos
+ - should fix bug 17360, others
+
+commit 67bc2ae7f227a2afedc8e699cf0458fa7960f301
+Author: Julien Cristau <[EMAIL PROTECTED]>
+Date: Sun Oct 26 16:05:04 2008 +0100
+
+ Bug#7148: Fix manpage formatting
+
+commit 98fdd78a1229584b922f816f331a45bfc178c961
+Author: Dave Airlie <[EMAIL PROTECTED]>
+Date: Tue Oct 21 18:36:22 2008 +1000
+
+ atombios: oops typo
+
+commit 763dff6c117a10b6a57ba1854c5b798359789e44
+Author: Dave Airlie <[EMAIL PROTECTED]>
+Date: Tue Oct 21 18:35:44 2008 +1000
+
+ atombios: set missing pixel clock
+
+commit 435cf7da68186f2601c4b888296117d4f652c625
+Author: Alex Deucher <[EMAIL PROTECTED]>
+Date: Wed Oct 15 10:52:14 2008 -0400
+
+ Add LCD dithering quirk for macbook pro
+
+ fixes bug 17897.
+
commit c0e6cb6d0eeef8f2ea60d840e1cd668fa92cd7f9
Author: Alex Deucher <[EMAIL PROTECTED]>
Date: Fri Oct 10 11:09:27 2008 -0400
diff --git a/debian/changelog b/debian/changelog
index 2716030..baaebb7 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,3 +1,10 @@
+xserver-xorg-video-ati (1:6.9.0+git20081129.783cdb73-1) UNRELEASED; urgency=low
+
+ * Pull upstream snapshot, up to commit 783cdb73.
+ + Add AGPMode quirk table, closes: #461144, #462590, #467460.
+
+ -- Brice Goglin <[EMAIL PROTECTED]> Sat, 29 Nov 2008 10:50:18 +0100
+
xserver-xorg-video-ati (1:6.9.0+git20081012.c0e6cb6d-1) experimental;
urgency=low
* Pull upstream snapshot, up to commit c0e6cb6d, closes: 500903.
commit 783cdb7374941bb1d2b63eea375fbf2f1b808cc3
Author: Dave Airlie <[EMAIL PROTECTED]>
Date: Thu Nov 27 15:29:06 2008 +1000
r100/r200: EXA misrenders dst == a8 + dst alpha use.
Fedora BZ#469556
I've played with various dst and texture formats and rewritten large
parts of this to no avail, so I'm punting for now.
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
index 97199ae..e5cc196 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
@@ -533,6 +533,9 @@ static Bool FUNC_NAME(R100PrepareComposite)(int op,
if (!RADEONGetDestFormat(pDstPicture, &dst_format))
return FALSE;
+ if (pDstPicture->format == PICT_a8 && RadeonBlendOp[op].dst_alpha)
+ RADEON_FALLBACK("Can't dst alpha blend A8\n");
+
if (pMask)
info->accel_state->has_mask = TRUE;
else
@@ -833,6 +836,9 @@ static Bool FUNC_NAME(R200PrepareComposite)(int op,
PicturePtr pSrcPicture,
if (!RADEONGetDestFormat(pDstPicture, &dst_format))
return FALSE;
+ if (pDstPicture->format == PICT_a8 && RadeonBlendOp[op].dst_alpha)
+ RADEON_FALLBACK("Can't dst alpha blend A8\n");
+
if (pMask)
info->accel_state->has_mask = TRUE;
else
commit 2d7cfc421713286edd5121b56999246f9ae70286
Author: Eygene Ryabinkin <[EMAIL PROTECTED]>
Date: Tue Nov 25 13:25:33 2008 -0500
Catch unsubstituted macro for PCI region base access
also fix up some warnings.
diff --git a/src/radeon_dri.c b/src/radeon_dri.c
index 960d784..f1a780d 100644
--- a/src/radeon_dri.c
+++ b/src/radeon_dri.c
@@ -925,7 +925,8 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr
pScreen)
}
xf86DrvMsg(pScreen->myNum, X_INFO,
"[agp] %d kB allocated with handle 0x%08x\n",
- info->dri->gartSize*1024, info->dri->agpMemHandle);
+ info->dri->gartSize*1024,
+ (unsigned int)info->dri->agpMemHandle);
if (drmAgpBind(info->dri->drmFD,
info->dri->agpMemHandle, info->dri->gartOffset) < 0) {
@@ -942,7 +943,8 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr
pScreen)
return FALSE;
}
xf86DrvMsg(pScreen->myNum, X_INFO,
- "[agp] ring handle = 0x%08x\n", info->dri->ringHandle);
+ "[agp] ring handle = 0x%08x\n",
+ (unsigned int)info->dri->ringHandle);
if (drmMap(info->dri->drmFD, info->dri->ringHandle, info->dri->ringMapSize,
&info->dri->ring) < 0) {
@@ -961,7 +963,7 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr
pScreen)
}
xf86DrvMsg(pScreen->myNum, X_INFO,
"[agp] ring read ptr handle = 0x%08x\n",
- info->dri->ringReadPtrHandle);
+ (unsigned int)info->dri->ringReadPtrHandle);
if (drmMap(info->dri->drmFD, info->dri->ringReadPtrHandle,
info->dri->ringReadMapSize,
&info->dri->ringReadPtr) < 0) {
@@ -981,7 +983,7 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info, ScreenPtr
pScreen)
}
xf86DrvMsg(pScreen->myNum, X_INFO,
"[agp] vertex/indirect buffers handle = 0x%08x\n",
- info->dri->bufHandle);
+ (unsigned int)info->dri->bufHandle);
if (drmMap(info->dri->drmFD, info->dri->bufHandle, info->dri->bufMapSize,
&info->dri->buf) < 0) {
@@ -1001,7 +1003,7 @@ static Bool RADEONDRIAgpInit(RADEONInfoPtr info,
ScreenPtr pScreen)
}
xf86DrvMsg(pScreen->myNum, X_INFO,
"[agp] GART texture map handle = 0x%08x\n",
- info->dri->gartTexHandle);
+ (unsigned int)info->dri->gartTexHandle);
if (drmMap(info->dri->drmFD, info->dri->gartTexHandle,
info->dri->gartTexMapSize,
&info->dri->gartTex) < 0) {
@@ -1034,7 +1036,8 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info,
ScreenPtr pScreen)
}
xf86DrvMsg(pScreen->myNum, X_INFO,
"[pci] %d kB allocated with handle 0x%08x\n",
- info->dri->gartSize*1024, info->dri->pciMemHandle);
+ info->dri->gartSize*1024,
+ (unsigned int)info->dri->pciMemHandle);
RADEONDRIInitGARTValues(info);
@@ -1045,7 +1048,8 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info,
ScreenPtr pScreen)
return FALSE;
}
xf86DrvMsg(pScreen->myNum, X_INFO,
- "[pci] ring handle = 0x%08x\n", info->dri->ringHandle);
+ "[pci] ring handle = 0x%08x\n",
+ (unsigned int)info->dri->ringHandle);
if (drmMap(info->dri->drmFD, info->dri->ringHandle, info->dri->ringMapSize,
&info->dri->ring) < 0) {
@@ -1067,7 +1071,7 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info,
ScreenPtr pScreen)
}
xf86DrvMsg(pScreen->myNum, X_INFO,
"[pci] ring read ptr handle = 0x%08x\n",
- info->dri->ringReadPtrHandle);
+ (unsigned int)info->dri->ringReadPtrHandle);
if (drmMap(info->dri->drmFD, info->dri->ringReadPtrHandle,
info->dri->ringReadMapSize,
&info->dri->ringReadPtr) < 0) {
@@ -1090,7 +1094,7 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info,
ScreenPtr pScreen)
}
xf86DrvMsg(pScreen->myNum, X_INFO,
"[pci] vertex/indirect buffers handle = 0x%08x\n",
- info->dri->bufHandle);
+ (unsigned int)info->dri->bufHandle);
if (drmMap(info->dri->drmFD, info->dri->bufHandle, info->dri->bufMapSize,
&info->dri->buf) < 0) {
@@ -1113,7 +1117,7 @@ static Bool RADEONDRIPciInit(RADEONInfoPtr info,
ScreenPtr pScreen)
}
xf86DrvMsg(pScreen->myNum, X_INFO,
"[pci] GART texture map handle = 0x%08x\n",
- info->dri->gartTexHandle);
+ (unsigned int)info->dri->gartTexHandle);
if (drmMap(info->dri->drmFD, info->dri->gartTexHandle,
info->dri->gartTexMapSize,
&info->dri->gartTex) < 0) {
@@ -1140,7 +1144,8 @@ static Bool RADEONDRIMapInit(RADEONInfoPtr info,
ScreenPtr pScreen)
return FALSE;
}
xf86DrvMsg(pScreen->myNum, X_INFO,
- "[drm] register handle = 0x%08x\n", info->dri->registerHandle);
+ "[drm] register handle = 0x%08x\n",
+ (unsigned int)info->dri->registerHandle);
return TRUE;
}
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index d670ab5..a888436 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -1774,14 +1774,14 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn)
if (dev->BiosBase) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"BIOS address override, using 0x%08lx instead of 0x%08lx\n",
- dev->BiosBase,
- info->BIOSAddr);
+ (unsigned long)dev->BiosBase,
+ (unsigned long)info->BIOSAddr);
info->BIOSAddr = dev->BiosBase;
from = X_CONFIG;
}
if (info->BIOSAddr) {
xf86DrvMsg(pScrn->scrnIndex, from,
- "BIOS at 0x%08lx\n", info->BIOSAddr);
+ "BIOS at 0x%08lx\n", (unsigned long)info->BIOSAddr);
}
#endif
@@ -2750,7 +2750,8 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
info->MMIOAddr = PCI_REGION_BASE(info->PciInfo, 2, REGION_MEM) & ~0xffULL;
info->MMIOSize = PCI_REGION_SIZE(info->PciInfo, 2);
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "TOTO SAYS %016llx\n",
- (unsigned long long)info->PciInfo->regions[2].base_addr);
+ (unsigned long long)PCI_REGION_BASE(info->PciInfo,
+ 2, REGION_MEM));
if (info->pEnt->device->IOBase) {
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
"MMIO address override, using 0x%08lx instead of
0x%016llx\n",
commit af7690b9c300d37c3a0c51e27e0ad2ca009224a2
Author: Benjamin Herrenschmidt <[EMAIL PROTECTED]>
Date: Tue Nov 25 02:57:30 2008 -0500
[PATCH] radeon: Fix PCI usage of 32-bit driver on 64-bit platform
The radeon driver is storing PCI addresses in unsigned long's which
won't work well on 32-bit platforms with 64-bit physical address space
such as PowerPC 4xx. This fixes it by using unsigned long long instead.
diff --git a/src/radeon.h b/src/radeon.h
index 13dc15b..605b057 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -648,9 +648,9 @@ typedef struct {
RADEONChipFamily ChipFamily;
RADEONErrata ChipErrata;
- unsigned long LinearAddr; /* Frame buffer physical address */
- unsigned long MMIOAddr; /* MMIO region physical address */
- unsigned long BIOSAddr; /* BIOS physical address */
+ unsigned long long LinearAddr; /* Frame buffer physical address
*/
+ unsigned long long MMIOAddr; /* MMIO region physical address
*/
+ unsigned long long BIOSAddr; /* BIOS physical address
*/
uint32_t fbLocation;
uint32_t gartLocation;
uint32_t mc_fb_location;
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 6164417..d670ab5 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -429,7 +429,7 @@ static Bool RADEONMapFB(ScrnInfoPtr pScrn)
RADEONInfoPtr info = RADEONPTR(pScrn);
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "Map: 0x%08lx, 0x%08lx\n", info->LinearAddr,
info->FbMapSize);
+ "Map: 0x%016llx, 0x%08lx\n", info->LinearAddr,
info->FbMapSize);
#ifndef XSERVER_LIBPCIACCESS
@@ -1750,11 +1750,11 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn)
}
from = X_PROBED;
- info->LinearAddr = PCI_REGION_BASE(info->PciInfo, 0, REGION_MEM) &
~0x1ffffffUL;
+ info->LinearAddr = PCI_REGION_BASE(info->PciInfo, 0, REGION_MEM) &
~0x1ffffffULL;
pScrn->memPhysBase = info->LinearAddr;
if (dev->MemBase) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "Linear address override, using 0x%016lx instead of
0x%016lx\n",
+ "Linear address override, using 0x%016lx instead of
0x%016llx\n",
dev->MemBase,
info->LinearAddr);
info->LinearAddr = dev->MemBase;
@@ -1765,7 +1765,7 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn)
return FALSE;
}
xf86DrvMsg(pScrn->scrnIndex, from,
- "Linear framebuffer at 0x%016lx\n", info->LinearAddr);
+ "Linear framebuffer at 0x%016llx\n", info->LinearAddr);
#ifndef XSERVER_LIBPCIACCESS
/* BIOS */
@@ -2747,11 +2747,13 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
info->PciTag = pciTag(PCI_DEV_BUS(info->PciInfo),
PCI_DEV_DEV(info->PciInfo),
PCI_DEV_FUNC(info->PciInfo));
- info->MMIOAddr = PCI_REGION_BASE(info->PciInfo, 2, REGION_MEM) & ~0xffUL;
+ info->MMIOAddr = PCI_REGION_BASE(info->PciInfo, 2, REGION_MEM) & ~0xffULL;
info->MMIOSize = PCI_REGION_SIZE(info->PciInfo, 2);
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "TOTO SAYS %016llx\n",
+ (unsigned long long)info->PciInfo->regions[2].base_addr);
if (info->pEnt->device->IOBase) {
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG,
- "MMIO address override, using 0x%08lx instead of 0x%08lx\n",
+ "MMIO address override, using 0x%08lx instead of
0x%016llx\n",
info->pEnt->device->IOBase,
info->MMIOAddr);
info->MMIOAddr = info->pEnt->device->IOBase;
@@ -2760,7 +2762,7 @@ Bool RADEONPreInit(ScrnInfoPtr pScrn, int flags)
goto fail1;
}
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "MMIO registers at 0x%016lx: size %ldKB\n", info->MMIOAddr,
info->MMIOSize / 1024);
+ "MMIO registers at 0x%016llx: size %ldKB\n", info->MMIOAddr,
info->MMIOSize / 1024);
if(!RADEONMapMMIO(pScrn)) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
commit 065938617c0feab17f4274a5350de02a692ba065
Author: Ramon van der Stelt <[EMAIL PROTECTED]>
Date: Tue Nov 25 02:23:46 2008 -0500
Interlaced mode fixes
see bug 12626
diff --git a/src/radeon_cursor.c b/src/radeon_cursor.c
index 08bfddf..0fcdcf0 100644
--- a/src/radeon_cursor.c
+++ b/src/radeon_cursor.c
@@ -221,9 +221,7 @@ radeon_crtc_set_cursor_position (xf86CrtcPtr crtc, int x,
int y)
OUTREG(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16)
| yorigin);
avivo_lock_cursor(crtc, FALSE);
} else {
- if (mode->Flags & V_INTERLACE)
- y /= 2;
- else if (mode->Flags & V_DBLSCAN)
+ if (mode->Flags & V_DBLSCAN)
y *= 2;
if (crtc_id == 0) {
diff --git a/src/radeon_output.c b/src/radeon_output.c
index 0ac19e7..035f2b8 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -477,6 +477,12 @@ radeon_mode_fixup(xf86OutputPtr output, DisplayModePtr
mode,
radeon_output->Flags &= ~RADEON_USE_RMX;
+ /*
+ * Refresh the Crtc values without INTERLACE_HALVE_V
+ * Should we use output->scrn->adjustFlags like xf86RandRModeConvert()
does?
+ */
+ xf86SetModeCrtc(adjusted_mode, 0);
+
/* decide if we are using RMX */
if ((radeon_output->MonType == MT_LCD || radeon_output->MonType == MT_DFP)
&& radeon_output->rmx_type != RMX_OFF) {
@@ -536,7 +542,7 @@ radeon_mode_fixup(xf86OutputPtr output, DisplayModePtr mode,
if (IS_AVIVO_VARIANT) {
/* hw bug */
if ((mode->Flags & V_INTERLACE)
- && (mode->CrtcVSyncStart < (mode->CrtcVDisplay + 2)))
+ && (adjusted_mode->CrtcVSyncStart < (adjusted_mode->CrtcVDisplay +
2)))
adjusted_mode->CrtcVSyncStart = adjusted_mode->CrtcVDisplay + 2;
}
commit 36a7dc6ea1e1929e986ab1159497c71521cb2f10
Author: Bryce Harrington <[EMAIL PROTECTED]>
Date: Tue Nov 25 01:04:37 2008 -0500
Additional AGP quirks
bug 18693
diff --git a/src/radeon_dri.c b/src/radeon_dri.c
index cb7df2c..960d784 100644
--- a/src/radeon_dri.c
+++ b/src/radeon_dri.c
@@ -744,10 +744,16 @@ static radeon_agpmode_quirk radeon_agpmode_quirk_list[] =
{
{ PCI_VENDOR_INTEL,0x3575, PCI_VENDOR_ATI,0x4c59,
PCI_VENDOR_DELL,0x00e3, 2 },
/* Intel 82852/82855 host bridge / Mobility 9600 M10 RV350 Needs AGPMode 1
(deb #467460) */
{ PCI_VENDOR_INTEL,0x3580, PCI_VENDOR_ATI,0x4e50, 0x1025,0x0061, 1 },
+ /* Intel 82852/82855 host bridge / Mobility 9600 M10 RV350 Needs AGPMode 1
(lp #141551) */
+ { PCI_VENDOR_INTEL,0x3580, PCI_VENDOR_ATI,0x4e50, 0x1043,0x1942, 1 },
+ /* Intel 82852/82855 host bridge / Mobility FireGL 9000 R250 Needs AGPMode
1 (lp #296617) */
+ { PCI_VENDOR_INTEL,0x3580, PCI_VENDOR_ATI,0x4c66, 0x1028,0x0149, 1 },
/* ASRock K7VT4A+ AGP 8x / ATI Radeon 9250 AGP Needs AGPMode 4 (LP:
#133192) */
{ 0x1849,0x3189, PCI_VENDOR_ATI,0x5960, 0x1787, 0x5960,
4},
+ /* VIA VT8363 Host Bridge / R200 QL [Radeon 8500] Needs AGPMode 2 (lp
#141551) */
+ { 0x1106,0x0305, PCI_VENDOR_ATI,0x514c, 0x1002,0x013a,
2 },
/* VIA VT8377 Host Bridge / R200 QM [Radeon 9100] Needs AGPMode 4 (deb
#461144) */
{ 0x1106,0x3189, PCI_VENDOR_ATI,0x514d, 0x174b,0x7149,
4 },
commit 2acb8e4ed220fccb21b22a53c5142ab3a35d32ef
Author: Alex Deucher <[EMAIL PROTECTED]>
Date: Tue Nov 25 15:07:09 2008 +1000
radeon: fixup shared DDC lines for some rv610 cards.
Some cards share DDC between a HDMI and VGA output, and expect the
driver to use load detect or EDID to figure it out.
airlied- shipped in RHEL5
Signed-off-by: Dave Airlie <[EMAIL PROTECTED]>
diff --git a/src/radeon_atombios.c b/src/radeon_atombios.c
index 851014b..3dfca17 100644
--- a/src/radeon_atombios.c
+++ b/src/radeon_atombios.c
@@ -1509,8 +1509,11 @@ RADEONLookupGPIOLineForDDC(ScrnInfoPtr pScrn, uint8_t id)
static RADEONI2CBusRec
rhdAtomParseI2CRecord(ScrnInfoPtr pScrn, atomBiosHandlePtr handle,
- ATOM_I2C_RECORD *Record)
+ ATOM_I2C_RECORD *Record, int i)
{
+ RADEONInfoPtr info = RADEONPTR (pScrn);
+
+ info->BiosConnector[i].i2c_line_mux = Record->sucI2cId.bfI2C_LineMux;
return RADEONLookupGPIOLineForDDC(pScrn, Record->sucI2cId.bfI2C_LineMux);
}
@@ -1664,7 +1667,7 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr
pScrn)
switch (Record->ucRecordType) {
case ATOM_I2C_RECORD_TYPE:
info->BiosConnector[i].ddc_i2c =
rhdAtomParseI2CRecord(pScrn, info->atomBIOS,
-
(ATOM_I2C_RECORD *)Record);
+
(ATOM_I2C_RECORD *)Record, i);
break;
case ATOM_HPD_INT_RECORD_TYPE:
break;
@@ -1676,6 +1679,20 @@ RADEONGetATOMConnectorInfoFromBIOSObject (ScrnInfoPtr
pScrn)
((char *)Record + Record->ucRecordSize);
}
}
+
+ for (i = 0; i < ATOM_MAX_SUPPORTED_DEVICE; i++) {
+ if (info->BiosConnector[i].valid) {
+ for (j = 0; j < ATOM_MAX_SUPPORTED_DEVICE; j++) {
+ if (info->BiosConnector[j].valid && (i != j) ) {
+ if (info->BiosConnector[i].i2c_line_mux ==
info->BiosConnector[j].i2c_line_mux) {
+ info->BiosConnector[i].shared_ddc = TRUE;
+ info->BiosConnector[j].shared_ddc = TRUE;
+ }
+ }
+ }
+ }
+ }
+
return TRUE;
}
@@ -1929,6 +1946,7 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable
(ScrnInfoPtr pScrn)
#endif
info->BiosConnector[i].valid = TRUE;
+ info->BiosConnector[i].shared_ddc = FALSE;
info->BiosConnector[i].output_id = ci.sucI2cId.sbfAccess.bfI2C_LineMux;
info->BiosConnector[i].devices = (1 << i);
info->BiosConnector[i].ConnectorType =
ci.sucConnectorInfo.sbfAccess.bfConnectorType;
@@ -2028,6 +2046,9 @@ RADEONGetATOMConnectorInfoFromBIOSConnectorTable
(ScrnInfoPtr pScrn)
info->BiosConnector[j].DACType =
info->BiosConnector[i].DACType;
info->BiosConnector[j].devices |=
info->BiosConnector[i].devices;
info->BiosConnector[i].valid = FALSE;
+ } else {
+ info->BiosConnector[i].shared_ddc = TRUE;
+ info->BiosConnector[j].shared_ddc = TRUE;
}
/* other possible combos? */
}
diff --git a/src/radeon_output.c b/src/radeon_output.c
index bff65ad..0ac19e7 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -243,8 +243,6 @@ radeon_ddc_connected(xf86OutputPtr output)
}
}
if (MonInfo) {
- if (!xf86ReturnOptValBool(info->Options, OPTION_IGNORE_EDID, FALSE))
- xf86OutputSetEDID(output, MonInfo);
if (radeon_output->type == OUTPUT_LVDS)
MonType = MT_LCD;
else if (radeon_output->type == OUTPUT_DVI_D)
@@ -258,6 +256,24 @@ radeon_ddc_connected(xf86OutputPtr output)
MonType = MT_DFP;
else
MonType = MT_CRT;
+
+ if (radeon_output->shared_ddc) {
+ if (radeon_output->type == OUTPUT_VGA) {
+ if (MonInfo->rawData[0x14] & 0x80) /* if it's digital and VGA */
+ MonType = MT_NONE;
+ else
+ MonType = MT_CRT;
+ } else {
+ if (MonInfo->rawData[0x14] & 0x80) /* if it's digital and
DVI/HDMI/etc. */
+ MonType = MT_DFP;
+ else
+ MonType = MT_NONE;
+ }
+ }
+
+ if (MonType != MT_NONE)
+ if (!xf86ReturnOptValBool(info->Options, OPTION_IGNORE_EDID, FALSE))
+ xf86OutputSetEDID(output, MonInfo);
} else
MonType = MT_NONE;
@@ -2667,6 +2683,7 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn)
*/
for (i = 0; i < RADEON_MAX_BIOS_CONNECTOR; i++) {
info->BiosConnector[i].valid = FALSE;
+ info->BiosConnector[i].shared_ddc = FALSE;
info->BiosConnector[i].ddc_i2c.valid = FALSE;
info->BiosConnector[i].DACType = DAC_NONE;
info->BiosConnector[i].TMDSType = TMDS_NONE;
@@ -2790,6 +2807,7 @@ Bool RADEONSetupConnectors(ScrnInfoPtr pScrn)
radeon_output->output_id = info->BiosConnector[i].output_id;
radeon_output->ddc_i2c = info->BiosConnector[i].ddc_i2c;
radeon_output->igp_lane_info = info->BiosConnector[i].igp_lane_info;
+ radeon_output->shared_ddc = info->BiosConnector[i].shared_ddc;
if (radeon_output->ConnectorType == CONNECTOR_DVI_D)
radeon_output->DACType = DAC_NONE;
diff --git a/src/radeon_probe.h b/src/radeon_probe.h
index c14241e..a971a31 100644
--- a/src/radeon_probe.h
+++ b/src/radeon_probe.h
@@ -208,6 +208,8 @@ typedef struct {
int hpd_mask;
RADEONI2CBusRec ddc_i2c;
int igp_lane_info;
+ Bool shared_ddc;
+ int i2c_line_mux;
} RADEONBIOSConnector;
typedef struct _RADEONOutputPrivateRec {
@@ -267,6 +269,7 @@ typedef struct _RADEONOutputPrivateRec {
int output_id;
int devices;
Bool enabled;
+ Bool shared_ddc;
} RADEONOutputPrivateRec, *RADEONOutputPrivatePtr;
struct avivo_pll_state {
commit b01e35168de40d192fd7a9ce6884b9c7419afbd4
Author: Alex Deucher <[EMAIL PROTECTED]>
Date: Mon Nov 24 21:06:42 2008 -0500
Fix up posted logic
noticed by benh on IRC
diff --git a/src/radeon_bios.c b/src/radeon_bios.c
index 1b85e8d..3e3613a 100644
--- a/src/radeon_bios.c
+++ b/src/radeon_bios.c
@@ -98,7 +98,7 @@ radeon_read_bios(ScrnInfoPtr pScrn)
}
static Bool
-radeon_read_unposted_bios(ScrnInfoPtr pScrn)
+radeon_read_disabled_bios(ScrnInfoPtr pScrn)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
@@ -293,7 +293,6 @@ RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr
pInt10)
RADEONInfoPtr info = RADEONPTR(pScrn);
int tmp;
unsigned short dptr;
- Bool posted = TRUE;
#ifdef XSERVER_LIBPCIACCESS
int size = info->PciInfo->rom_size > RADEON_VBIOS_SIZE ?
info->PciInfo->rom_size : RADEON_VBIOS_SIZE;
@@ -310,10 +309,8 @@ RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr
pInt10)
info->BIOSAddr = pInt10->BIOSseg << 4;
(void)memcpy(info->VBIOS, xf86int10Addr(pInt10, info->BIOSAddr),
RADEON_VBIOS_SIZE);
- } else if (!radeon_read_bios(pScrn)) {
- (void)radeon_read_unposted_bios(pScrn);
- posted = FALSE;
- }
+ } else if (!radeon_read_bios(pScrn))
+ (void)radeon_read_disabled_bios(pScrn);
}
if (info->VBIOS[0] != 0x55 || info->VBIOS[1] != 0xaa) {
@@ -407,17 +404,14 @@ RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr
pInt10)
* so let's work around this for now by only POSTing if none of the
* CRTCs are enabled
*/
- if ((!posted) && info->VBIOS) {
- posted = radeon_card_posted(pScrn);
- }
-
- if ((!posted) && info->VBIOS) {
+ if ((!radeon_card_posted(pScrn)) && info->VBIOS) {
if (info->IsAtomBios) {
if (!rhdAtomASICInit(info->atomBIOS))
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"%s: AsicInit failed.\n",__func__);
} else {
#if 0
+ /* FIX ME */
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Attempting to POST via legacy
BIOS tables\n");
RADEONGetBIOSInitTableOffsets(pScrn);
RADEONPostCardFromBIOSTables(pScrn);
commit d7a03e93372b17d642b42f5490464616ae7c99c1
Author: Alex Deucher <[EMAIL PROTECTED]>
Date: Mon Nov 24 15:52:05 2008 -0500
Get hardcoded edid from the bios for servers that support it
should fix bug 11300
diff --git a/src/radeon.h b/src/radeon.h
index f7ae1a8..13dc15b 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -836,6 +836,9 @@ typedef struct {
Bool r600_shadow_fb;
void *fb_shadow;
+ /* some server chips have a hardcoded edid in the bios so that they work
with KVMs */
+ Bool get_hardcoded_edid_from_bios;
+
} RADEONInfoRec, *RADEONInfoPtr;
#define RADEONWaitForFifo(pScrn, entries) \
@@ -926,7 +929,7 @@ extern Bool RADEONGetClockInfoFromBIOS(ScrnInfoPtr pScrn);
extern Bool RADEONGetConnectorInfoFromBIOS(ScrnInfoPtr pScrn);
extern Bool RADEONGetDAC2InfoFromBIOS(xf86OutputPtr output);
extern Bool RADEONGetExtTMDSInfoFromBIOS(xf86OutputPtr output);
-extern Bool RADEONGetHardCodedEDIDFromBIOS(xf86OutputPtr output);
+extern xf86MonPtr RADEONGetHardCodedEDIDFromBIOS(xf86OutputPtr output);
extern Bool RADEONGetBIOSInitTableOffsets(ScrnInfoPtr pScrn);
extern Bool RADEONGetLVDSInfoFromBIOS(xf86OutputPtr output);
extern Bool RADEONGetTMDSInfoFromBIOS(xf86OutputPtr output);
diff --git a/src/radeon_bios.c b/src/radeon_bios.c
index 89c816c..1b85e8d 100644
--- a/src/radeon_bios.c
+++ b/src/radeon_bios.c
@@ -1053,39 +1053,27 @@ Bool RADEONGetLVDSInfoFromBIOS (xf86OutputPtr output)
return TRUE;
}
-Bool RADEONGetHardCodedEDIDFromBIOS (xf86OutputPtr output)
+xf86MonPtr RADEONGetHardCodedEDIDFromBIOS (xf86OutputPtr output)
{
ScrnInfoPtr pScrn = output->scrn;
- RADEONInfoPtr info = RADEONPTR(pScrn);
- RADEONOutputPrivatePtr radeon_output = output->driver_private;
+ RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned long tmp;
- char EDID[256];
+ unsigned char edid[256];
+ xf86MonPtr mon = NULL;
- if (!info->VBIOS) return FALSE;
+ if (!info->VBIOS)
+ return mon;
- if (info->IsAtomBios) {
- /* Not yet */
- return FALSE;
- } else {
- if (!(tmp = RADEON_BIOS16(info->ROMHeaderStart + 0x4c))) {
- return FALSE;
+ if (!info->IsAtomBios) {
+ tmp = RADEON_BIOS16(info->ROMHeaderStart + 0x4c);
+ if (tmp) {
+ memcpy(edid, (unsigned char*)(info->VBIOS + tmp), 256);
+ if (edid[1] == 0xff)
+ mon = xf86InterpretEDID(output->scrn->scrnIndex, edid);
}
-
- memcpy(EDID, (char*)(info->VBIOS + tmp), 256);
-
- radeon_output->DotClock = (*(uint16_t*)(EDID+54)) * 10;
- radeon_output->PanelXRes = (*(uint8_t*)(EDID+56)) +
((*(uint8_t*)(EDID+58))>>4)*256;
- radeon_output->HBlank = (*(uint8_t*)(EDID+57)) +
((*(uint8_t*)(EDID+58)) & 0xf)*256;
- radeon_output->HOverPlus = (*(uint8_t*)(EDID+62)) +
((*(uint8_t*)(EDID+65)>>6)*256);
- radeon_output->HSyncWidth = (*(uint8_t*)(EDID+63)) +
(((*(uint8_t*)(EDID+65)>>4) & 3)*256);
- radeon_output->PanelYRes = (*(uint8_t*)(EDID+59)) +
((*(uint8_t*)(EDID+61))>>4)*256;
- radeon_output->VBlank = ((*(uint8_t*)(EDID+60)) +
((*(uint8_t*)(EDID+61)) & 0xf)*256);
- radeon_output->VOverPlus = (((*(uint8_t*)(EDID+64))>>4) +
(((*(uint8_t*)(EDID+65)>>2) & 3)*16));
- radeon_output->VSyncWidth = (((*(uint8_t*)(EDID+64)) & 0xf) +
((*(uint8_t*)(EDID+65)) & 3)*256);
- radeon_output->Flags = V_NHSYNC | V_NVSYNC;
/**(uint8_t*)(EDID+71);*/
- xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Hardcoded EDID data will be used
for TMDS panel\n");
}
- return TRUE;
+
+ return mon;
}
Bool RADEONGetTMDSInfoFromBIOS (xf86OutputPtr output)
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index c759bd6..6164417 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -1688,6 +1688,7 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn)
info->IsDellServer = FALSE;
info->HasSingleDAC = FALSE;
info->InternalTVOut = TRUE;
+ info->get_hardcoded_edid_from_bios = FALSE;
for (i = 0; i < sizeof(RADEONCards) / sizeof(RADEONCardInfo); i++) {
if (info->Chipset == RADEONCards[i].pci_device_id) {
@@ -1705,6 +1706,10 @@ static Bool RADEONPreInitChipType(ScrnInfoPtr pScrn)
switch (info->Chipset) {
case PCI_CHIP_RN50_515E: /* RN50 is based on the RV100 but 3D isn't
guaranteed to work. YMMV. */
case PCI_CHIP_RN50_5969:
+ /* Some Sun servers have a hardcoded edid so KVMs work properly */
+ if ((PCI_SUB_VENDOR_ID(info->PciInfo) == 0x108e) &&
+ (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x4133))
+ info->get_hardcoded_edid_from_bios = TRUE;
case PCI_CHIP_RV100_QY:
case PCI_CHIP_RV100_QZ:
/* DELL triple-head configuration. */
diff --git a/src/radeon_output.c b/src/radeon_output.c
index 8c794fb..bff65ad 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -229,7 +229,14 @@ radeon_ddc_connected(xf86OutputPtr output)
(radeon_output->ddc_i2c.mask_clk_reg == RADEON_GPIO_VGA_DDC) &&
info->IsAtomBios)
MonInfo = radeon_atom_get_edid(output);
- else {
+ else if (info->get_hardcoded_edid_from_bios) {
+ MonInfo = RADEONGetHardCodedEDIDFromBIOS(output);
+ if (MonInfo == NULL) {
+ RADEONI2CDoLock(output, TRUE);
+ MonInfo = xf86OutputGetEDID(output, radeon_output->pI2CBus);
+ RADEONI2CDoLock(output, FALSE);
+ }
+ } else {
RADEONI2CDoLock(output, TRUE);
MonInfo = xf86OutputGetEDID(output, radeon_output->pI2CBus);
RADEONI2CDoLock(output, FALSE);
commit 3858e31fa9d77d52a5cabb02f53f06385eab40f7
Author: Alex Deucher <[EMAIL PROTECTED]>
Date: Mon Nov 24 14:39:41 2008 -0500
Don't support rotation is accel is not available
Fixes bug 18068
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index 9040bae..d764782 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -472,7 +472,7 @@ radeon_crtc_shadow_destroy(xf86CrtcPtr crtc, PixmapPtr
rotate_pixmap, void *data
}
-static const xf86CrtcFuncsRec radeon_crtc_funcs = {
+static xf86CrtcFuncsRec radeon_crtc_funcs = {
.dpms = radeon_crtc_dpms,
.save = NULL, /* XXX */
.restore = NULL, /* XXX */
@@ -536,6 +536,13 @@ Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask)
RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
RADEONInfoPtr info = RADEONPTR(pScrn);
+ if ((info->ChipFamily < CHIP_FAMILY_R600) &&
+ (!xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE))) {
+ radeon_crtc_funcs.shadow_create = radeon_crtc_shadow_create;
+ radeon_crtc_funcs.shadow_allocate = radeon_crtc_shadow_allocate;
+ radeon_crtc_funcs.shadow_destroy = radeon_crtc_shadow_destroy;
+ }
+
if (mask & 1) {
if (pRADEONEnt->Controller[0])
return TRUE;
commit 3d27876d91ef69d71f17b6cf8c07c26bf12857b4
Author: Dave Airlie <[EMAIL PROTECTED]>
Date: Mon Nov 10 15:47:13 2008 +1000
radeon: always align dstPitch to 64 bytes for textured video
bz# 18454
diff --git a/src/radeon_textured_video.c b/src/radeon_textured_video.c
index c185b46..35b332b 100644
--- a/src/radeon_textured_video.c
+++ b/src/radeon_textured_video.c
@@ -188,13 +188,7 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
break;
}
-#ifdef XF86DRI
- if (info->directRenderingEnabled && info->DMAForXv)
- /* The upload blit only supports multiples of 64 bytes */
- dstPitch = (dstPitch + 63) & ~63;
- else
-#endif
- dstPitch = (dstPitch + 15) & ~15;
+ dstPitch = (dstPitch + 63) & ~63;
if (pPriv->video_memory != NULL && size != pPriv->size) {
radeon_legacy_free_memory(pScrn, pPriv->video_memory);
commit 6c8b352264540ccc4622a7c0b704ce452dcd707d
Author: Dave Airlie <[EMAIL PROTECTED]>
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