src/AtomBios/CD_Operations.c | 61 ++++---
src/AtomBios/Decoder.c | 108 +++++++------
src/AtomBios/hwserv_drv.c | 14 +
src/AtomBios/includes/CD_Common_Types.h | 12 +
src/AtomBios/includes/CD_Definitions.h | 3
src/AtomBios/includes/CD_Structs.h | 24 ++-
src/AtomBios/includes/Decoder.h | 24 ++-
src/AtomBios/includes/atombios.h | 24 ++-
src/ati_pciids_gen.h | 2
src/atombios_crtc.c | 37 +++-
src/atombios_output.c | 30 +--
src/legacy_crtc.c | 255 ++++++++++++++------------------
src/legacy_output.c | 31 +--
src/pcidb/ati_pciids.csv | 2
src/radeon.h | 32 +++-
src/radeon_atombios.c | 54 ++++--
src/radeon_atomwrapper.c | 1
src/radeon_bios.c | 101 ++++++++----
src/radeon_chipinfo_gen.h | 2
src/radeon_chipset_gen.h | 2
src/radeon_commonfuncs.c | 9 -
src/radeon_crtc.c | 38 ++++
src/radeon_cursor.c | 16 +-
src/radeon_driver.c | 139 ++++++++++++-----
src/radeon_exa.c | 6
src/radeon_macros.h | 26 ---
src/radeon_output.c | 11 +
src/radeon_pci_chipset_gen.h | 2
src/radeon_pci_device_match_gen.h | 2
src/radeon_probe.h | 2
src/radeon_reg.h | 24 ++-
src/radeon_textured_videofuncs.c | 7
32 files changed, 687 insertions(+), 414 deletions(-)
New commits:
commit 6c23ba42869a36d4a9c82ea8ba36e1098c461756
Author: Alex Deucher <[EMAIL PROTECTED]>
Date: Fri Jul 11 19:05:00 2008 -0400
R300: NUM_FPU adjustments for VAP_CNTL
(cherry picked from commit ab14f725676e4d4e45278c64b03fe2d328a3e439)
diff --git a/src/radeon_commonfuncs.c b/src/radeon_commonfuncs.c
index 58fe306..d0c5229 100644
--- a/src/radeon_commonfuncs.c
+++ b/src/radeon_commonfuncs.c
@@ -158,13 +158,14 @@ static void FUNC_NAME(RADEONInit3DEngine)(ScrnInfoPtr
pScrn)
if (info->ChipFamily == CHIP_FAMILY_RV515)
vap_cntl |= (2 << R300_PVS_NUM_FPUS_SHIFT);
else if ((info->ChipFamily == CHIP_FAMILY_RV530) ||
- (info->ChipFamily == CHIP_FAMILY_RV560))
+ (info->ChipFamily == CHIP_FAMILY_RV560) ||
+ (info->ChipFamily == CHIP_FAMILY_RV570))
vap_cntl |= (5 << R300_PVS_NUM_FPUS_SHIFT);
- else if (info->ChipFamily == CHIP_FAMILY_R420)
+ else if ((info->ChipFamily == CHIP_FAMILY_RV410) ||
+ (info->ChipFamily == CHIP_FAMILY_R420))
vap_cntl |= (6 << R300_PVS_NUM_FPUS_SHIFT);
else if ((info->ChipFamily == CHIP_FAMILY_R520) ||
- (info->ChipFamily == CHIP_FAMILY_R580) ||
- (info->ChipFamily == CHIP_FAMILY_RV570))
+ (info->ChipFamily == CHIP_FAMILY_R580))
vap_cntl |= (8 << R300_PVS_NUM_FPUS_SHIFT);
else
vap_cntl |= (4 << R300_PVS_NUM_FPUS_SHIFT);
commit 42aa10126169368845948e8669d74e08550568bc
Author: Alex Deucher <[EMAIL PROTECTED]>
Date: Mon Jul 28 17:12:41 2008 -0400
Fix error in driver connector table for powerbook w/ vga
(cherry picked from commit 0a505297f09aefb1b4432176a263bfdf6f256f77)
diff --git a/src/radeon_output.c b/src/radeon_output.c
index b725e0a..b22442c 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -2308,7 +2308,7 @@ static Bool RADEONSetupAppleConnectors(ScrnInfoPtr pScrn)
info->BiosConnector[0].ddc_i2c =
legacy_setup_i2c_bus(RADEON_GPIO_DVI_DDC);
info->BiosConnector[0].DACType = DAC_NONE;
info->BiosConnector[0].TMDSType = TMDS_NONE;
- info->BiosConnector[0].ConnectorType = CONNECTOR_VGA;
+ info->BiosConnector[0].ConnectorType = CONNECTOR_LVDS;
info->BiosConnector[0].valid = TRUE;
info->BiosConnector[1].ddc_i2c =
legacy_setup_i2c_bus(RADEON_GPIO_VGA_DDC);
commit 674f167876a99ca2171f51a6d42f4d994dd73820
Author: Alex Deucher <[EMAIL PROTECTED]>
Date: Mon Jul 28 11:09:10 2008 -0400
Add quirk for oem x300 card
- debian bug 492457
(cherry picked from commit d5799ac53c3e1b2ca1da97780b171a44060c3aad)
diff --git a/src/radeon_bios.c b/src/radeon_bios.c
index 35e6960..adedeb3 100644
--- a/src/radeon_bios.c
+++ b/src/radeon_bios.c
@@ -481,6 +481,16 @@ static void RADEONApplyLegacyQuirks(ScrnInfoPtr pScrn, int
index)
}
}
+ /* X300 card with extra non-existent DVI port */
+ if (info->Chipset == PCI_CHIP_RV370_5B60 &&
+ PCI_SUB_VENDOR_ID(info->PciInfo) == 0x17af &&
+ PCI_SUB_DEVICE_ID(info->PciInfo) == 0x201e &&
+ index == 2) {
+ if (info->BiosConnector[index].ConnectorType == CONNECTOR_DVI_I) {
+ info->BiosConnector[index].valid = FALSE;
+ }
+ }
+
}
static Bool RADEONGetLegacyConnectorInfoFromBIOS (ScrnInfoPtr pScrn)
commit efbc15c5f470f941727b1a0acdc2c9b1719df245
Author: Alex Deucher <[EMAIL PROTECTED]>
Date: Mon Jul 21 13:47:09 2008 -0400
Interlaced mode fixups for AVIVO chips
(cherry picked from commit b0378bb145c8a915c943bef7d17f2cdecfccc891)
diff --git a/src/atombios_crtc.c b/src/atombios_crtc.c
index 02478b1..06efe5c 100644
--- a/src/atombios_crtc.c
+++ b/src/atombios_crtc.c
@@ -490,6 +490,12 @@ atombios_crtc_mode_set(xf86CrtcPtr crtc,
/* unlock the mode regs */
OUTREG(AVIVO_D1SCL_UPDATE + radeon_crtc->crtc_offset, 0);
+ if (adjusted_mode->Flags & V_INTERLACE)
+ OUTREG(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
+ AVIVO_D1MODE_INTERLEAVE_EN);
+ else
+ OUTREG(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
+ 0);
}
atombios_crtc_set_pll(crtc, adjusted_mode, pll_flags);
diff --git a/src/radeon_cursor.c b/src/radeon_cursor.c
index d480416..13c2b9c 100644
--- a/src/radeon_cursor.c
+++ b/src/radeon_cursor.c
@@ -209,11 +209,6 @@ radeon_crtc_set_cursor_position (xf86CrtcPtr crtc, int x,
int y)
if (xorigin >= CURSOR_WIDTH) xorigin = CURSOR_WIDTH - 1;
if (yorigin >= CURSOR_HEIGHT) yorigin = CURSOR_HEIGHT - 1;
- if (mode->Flags & V_INTERLACE)
- y /= 2;
- else if (mode->Flags & V_DBLSCAN)
- y *= 2;
-
if (IS_AVIVO_VARIANT) {
/* avivo cursor spans the full fb width */
if (crtc->rotatedData == NULL) {
@@ -226,6 +221,11 @@ radeon_crtc_set_cursor_position (xf86CrtcPtr crtc, int x,
int y)
OUTREG(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16)
| yorigin);
avivo_lock_cursor(crtc, FALSE);
} else {
+ if (mode->Flags & V_INTERLACE)
+ y /= 2;
+ else if (mode->Flags & V_DBLSCAN)
+ y *= 2;
+
if (crtc_id == 0) {
OUTREG(RADEON_CUR_HORZ_VERT_OFF, (RADEON_CUR_LOCK
| (xorigin << 16)
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index bb154de..e067cb7 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -4239,6 +4239,7 @@ avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save)
state->grph1.desktop_height = INREG(AVIVO_D1MODE_DESKTOP_HEIGHT);
state->grph1.viewport_start = INREG(AVIVO_D1MODE_VIEWPORT_START);
state->grph1.viewport_size = INREG(AVIVO_D1MODE_VIEWPORT_SIZE);
+ state->grph1.mode_data_format = INREG(AVIVO_D1MODE_DATA_FORMAT);
state->crtc2.pll_source = INREG(AVIVO_PCLK_CRTC2_CNTL);
@@ -4279,6 +4280,7 @@ avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save)
state->grph2.desktop_height = INREG(AVIVO_D2MODE_DESKTOP_HEIGHT);
state->grph2.viewport_start = INREG(AVIVO_D2MODE_VIEWPORT_START);
state->grph2.viewport_size = INREG(AVIVO_D2MODE_VIEWPORT_SIZE);
+ state->grph2.mode_data_format = INREG(AVIVO_D2MODE_DATA_FORMAT);
if (IS_DCE3_VARIANT) {
/* save DVOA regs */
@@ -4536,12 +4538,14 @@ avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore)
OUTREG(AVIVO_D1MODE_DESKTOP_HEIGHT, state->grph1.desktop_height);
OUTREG(AVIVO_D1MODE_VIEWPORT_START, state->grph1.viewport_start);
OUTREG(AVIVO_D1MODE_VIEWPORT_SIZE, state->grph1.viewport_size);
+ OUTREG(AVIVO_D1MODE_DATA_FORMAT, state->grph1.mode_data_format);
OUTREG(AVIVO_D1SCL_UPDATE, 0);
OUTREG(AVIVO_D2SCL_UPDATE, AVIVO_D1SCL_UPDATE_LOCK);
OUTREG(AVIVO_D2MODE_DESKTOP_HEIGHT, state->grph2.desktop_height);
OUTREG(AVIVO_D2MODE_VIEWPORT_START, state->grph2.viewport_start);
OUTREG(AVIVO_D2MODE_VIEWPORT_SIZE, state->grph2.viewport_size);
+ OUTREG(AVIVO_D2MODE_DATA_FORMAT, state->grph2.mode_data_format);
OUTREG(AVIVO_D2SCL_UPDATE, 0);
/* Set the PLL */
diff --git a/src/radeon_output.c b/src/radeon_output.c
index ade0b00..b725e0a 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -580,6 +580,13 @@ radeon_mode_fixup(xf86OutputPtr output, DisplayModePtr
mode,
}
}
+ if (IS_AVIVO_VARIANT) {
+ /* hw bug */
+ if ((mode->Flags & V_INTERLACE)
+ && (mode->CrtcVSyncStart < (mode->CrtcVDisplay + 2)))
+ adjusted_mode->CrtcVSyncStart = adjusted_mode->CrtcVDisplay + 2;
+ }
+
return TRUE;
}
diff --git a/src/radeon_probe.h b/src/radeon_probe.h
index 2837671..35d622d 100644
--- a/src/radeon_probe.h
+++ b/src/radeon_probe.h
@@ -313,6 +313,7 @@ struct avivo_grph_state {
uint32_t desktop_height;
uint32_t viewport_start;
uint32_t viewport_size;
+ uint32_t mode_data_format;
};
struct avivo_state
diff --git a/src/radeon_reg.h b/src/radeon_reg.h
index dd47dc4..3b3a8e5 100644
--- a/src/radeon_reg.h
+++ b/src/radeon_reg.h
@@ -3602,6 +3602,8 @@
#define AVIVO_DC_LUTA_WHITE_OFFSET_GREEN 0x64d4
#define AVIVO_DC_LUTA_WHITE_OFFSET_RED 0x64d8
+#define AVIVO_D1MODE_DATA_FORMAT 0x6528
+# define AVIVO_D1MODE_INTERLEAVE_EN (1 << 0)
#define AVIVO_D1MODE_DESKTOP_HEIGHT 0x652c
#define AVIVO_D1MODE_VIEWPORT_START 0x6580
#define AVIVO_D1MODE_VIEWPORT_SIZE 0x6584
@@ -3654,6 +3656,7 @@
#define AVIVO_D2CUR_SIZE 0x6c10
#define AVIVO_D2CUR_POSITION 0x6c14
+#define AVIVO_D2MODE_DATA_FORMAT 0x6d28
#define AVIVO_D2MODE_DESKTOP_HEIGHT 0x6d2c
#define AVIVO_D2MODE_VIEWPORT_START 0x6d80
#define AVIVO_D2MODE_VIEWPORT_SIZE 0x6d84
commit cc94ae803a9d8a30d4eae8615d788033c8a23bb8
Author: Alex Deucher <[EMAIL PROTECTED]>
Date: Mon Jul 21 10:36:48 2008 -0400
Clear display priority bits before resetting them
(cherry picked from commit c18fad622a3c4f9572051120d83af68b625b5686)
diff --git a/src/legacy_crtc.c b/src/legacy_crtc.c
index e5561e8..f7216f9 100644
--- a/src/legacy_crtc.c
+++ b/src/legacy_crtc.c
@@ -1369,6 +1369,8 @@ RADEONInitDispBandwidthLegacy(ScrnInfoPtr pScrn,
*/
if ((info->DispPriority == 2) && IS_R300_VARIANT) {
uint32_t mc_init_misc_lat_timer = INREG(R300_MC_INIT_MISC_LAT_TIMER);
+ mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK <<
R300_MC_DISP1R_INIT_LAT_SHIFT);
+ mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK <<
R300_MC_DISP0R_INIT_LAT_SHIFT);
if (pRADEONEnt->pCrtc[1]->enabled)
mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT); /*
display 1 */
if (pRADEONEnt->pCrtc[0]->enabled)
@@ -1376,7 +1378,6 @@ RADEONInitDispBandwidthLegacy(ScrnInfoPtr pScrn,
OUTREG(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
}
-
/* R420 and RV410 family not supported yet */
if (info->ChipFamily == CHIP_FAMILY_R420 || info->ChipFamily ==
CHIP_FAMILY_RV410) return;
diff --git a/src/radeon_reg.h b/src/radeon_reg.h
index 3967f95..dd47dc4 100644
--- a/src/radeon_reg.h
+++ b/src/radeon_reg.h
@@ -1033,7 +1033,9 @@
#define RADEON_NB_TOM 0x15c
#define R300_MC_INIT_MISC_LAT_TIMER 0x180
# define R300_MC_DISP0R_INIT_LAT_SHIFT 8
+# define R300_MC_DISP0R_INIT_LAT_MASK 0xf
# define R300_MC_DISP1R_INIT_LAT_SHIFT 12
+# define R300_MC_DISP1R_INIT_LAT_MASK 0xf
#define RADEON_MCLK_CNTL 0x0012 /* PLL */
# define RADEON_FORCEON_MCLKA (1 << 16)
# define RADEON_FORCEON_MCLKB (1 << 17)
commit b92f15495e40f86abd295393745af94c377a32c9
Author: Alex Deucher <[EMAIL PROTECTED]>
Date: Mon Jul 21 10:30:41 2008 -0400
Clean up legacy display watermark setup
- makes crtc1 and crtc2 watermark setup independant.
- fixes the case where only crtc2 is active
(cherry picked from commit dc231ff8e063313d2bcf5acccad67a9f8a7e3314)
diff --git a/src/legacy_crtc.c b/src/legacy_crtc.c
index 3df61a7..e5561e8 100644
--- a/src/legacy_crtc.c
+++ b/src/legacy_crtc.c
@@ -1327,9 +1327,12 @@ radeon_update_tv_routing(ScrnInfoPtr pScrn,
RADEONSavePtr restore)
}
/* Calculate display buffer watermark to prevent buffer underflow */
-static void
-RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr info, int
pixel_bytes2, DisplayModePtr mode1, DisplayModePtr mode2)
+void
+RADEONInitDispBandwidthLegacy(ScrnInfoPtr pScrn,
+ DisplayModePtr mode1, int pixel_bytes1,
+ DisplayModePtr mode2, int pixel_bytes2)
{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
@@ -1352,10 +1355,10 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn,
RADEONInfoPtr info, int pixel_bytes2
float min_mem_eff = 0.8;
float sclk_eff, sclk_delay;
float mc_latency_mclk, mc_latency_sclk, cur_latency_mclk, cur_latency_sclk;
- float disp_latency, disp_latency_overhead, disp_drain_rate,
disp_drain_rate2;
+ float disp_latency, disp_latency_overhead, disp_drain_rate = 0,
disp_drain_rate2;
float pix_clk, pix_clk2; /* in MHz */
int cur_size = 16; /* in octawords */
- int critical_point, critical_point2;
+ int critical_point = 0, critical_point2;
int stop_req, max_stop_req;
float read_return_rate, time_disp1_drop_priority;
@@ -1366,11 +1369,10 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn,
RADEONInfoPtr info, int pixel_bytes2
*/
if ((info->DispPriority == 2) && IS_R300_VARIANT) {
uint32_t mc_init_misc_lat_timer = INREG(R300_MC_INIT_MISC_LAT_TIMER);
- if (pRADEONEnt->pCrtc[1]->enabled) {
- mc_init_misc_lat_timer |= 0x1100; /* display 0 and 1 */
- } else {
- mc_init_misc_lat_timer |= 0x0100; /* display 0 only */
- }
+ if (pRADEONEnt->pCrtc[1]->enabled)
+ mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT); /*
display 1 */
+ if (pRADEONEnt->pCrtc[0]->enabled)
+ mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT); /*
display 0 */
OUTREG(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
}
@@ -1383,15 +1385,17 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn,
RADEONInfoPtr info, int pixel_bytes2
*/
mem_bw = info->mclk * (info->RamWidth / 8) * (info->IsDDR ? 2 : 1);
- pix_clk = mode1->Clock/1000.0;
- if (mode2)
+ pix_clk = 0;
+ pix_clk2 = 0;
+ peak_disp_bw = 0;
+ if (mode1) {
+ pix_clk = mode1->Clock/1000.0;
+ peak_disp_bw += (pix_clk * pixel_bytes1);
+ }
+ if (mode2) {
pix_clk2 = mode2->Clock/1000.0;
- else
- pix_clk2 = 0;
-
- peak_disp_bw = (pix_clk * info->CurrentLayout.pixel_bytes);
- if (pixel_bytes2)
- peak_disp_bw += (pix_clk2 * pixel_bytes2);
+ peak_disp_bw += (pix_clk2 * pixel_bytes2);
+ }
if (peak_disp_bw >= mem_bw * min_mem_eff) {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
@@ -1399,20 +1403,6 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn,
RADEONInfoPtr info, int pixel_bytes2
"If you have flickering problem, try to lower resolution,
refresh rate, or color depth\n");
}
- /* CRTC1
- Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
- GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
- */
- stop_req = mode1->HDisplay * info->CurrentLayout.pixel_bytes / 16;
-
- /* setup Max GRPH_STOP_REQ default value */
- if (IS_RV100_VARIANT)
- max_stop_req = 0x5c;
- else
- max_stop_req = 0x7c;
- if (stop_req > max_stop_req)
- stop_req = max_stop_req;
-
/* Get values from the EXT_MEM_CNTL register...converting its contents. */
temp = INREG(RADEON_MEM_TIMING_CNTL);
if ((info->ChipFamily == CHIP_FAMILY_RV100) || info->IsIGP) { /* RV100,
M6, IGPs */
@@ -1435,9 +1425,8 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr
info, int pixel_bytes2
}
if (IS_R300_VARIANT) {
-
/* on the R300, Tcas is included in Trbs.
- */
+ */
temp = INREG(RADEON_MEM_CNTL);
data = (R300_MEM_NUM_CHANNELS_MASK & temp);
if (data == 1) {
@@ -1473,7 +1462,8 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn, RADEONInfoPtr
info, int pixel_bytes2
sclk_eff = info->sclk;
}
- /* Find the memory controller latency for the display client.
+ /*
+ Find the memory controller latency for the display client.
*/
if (IS_R300_VARIANT) {
/*not enough for R350 ???*/
@@ -1527,89 +1517,107 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn,
RADEONInfoPtr info, int pixel_bytes2
mc_latency_sclk = mc_latency_sclk + disp_latency_overhead +
cur_latency_sclk;
disp_latency = MAX(mc_latency_mclk, mc_latency_sclk);
- /*
- Find the drain rate of the display buffer.
- */
- disp_drain_rate = pix_clk / (16.0/info->CurrentLayout.pixel_bytes);
- if (pixel_bytes2)
- disp_drain_rate2 = pix_clk2 / (16.0/pixel_bytes2);
+ /* setup Max GRPH_STOP_REQ default value */
+ if (IS_RV100_VARIANT)
+ max_stop_req = 0x5c;
else
- disp_drain_rate2 = 0;
+ max_stop_req = 0x7c;
- /*
- Find the critical point of the display buffer.
- */
- critical_point= (uint32_t)(disp_drain_rate * disp_latency + 0.5);
+ if (mode1) {
+ /* CRTC1
+ Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
+ GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
+ */
+ stop_req = mode1->HDisplay * pixel_bytes1 / 16;
- /* ???? */
- /*
- temp = (info->SavedReg.grph_buffer_cntl & RADEON_GRPH_CRITICAL_POINT_MASK)
>> RADEON_GRPH_CRITICAL_POINT_SHIFT;
- if (critical_point < temp) critical_point = temp;
- */
- if (info->DispPriority == 2) {
- critical_point = 0;
- }
+ if (stop_req > max_stop_req)
+ stop_req = max_stop_req;
- /*
- The critical point should never be above max_stop_req-4. Setting
- GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
- */
- if (max_stop_req - critical_point < 4) critical_point = 0;
+ /*
+ Find the drain rate of the display buffer.
+ */
+ disp_drain_rate = pix_clk / (16.0/pixel_bytes1);
- if (critical_point == 0 && mode2 && info->ChipFamily == CHIP_FAMILY_R300) {
- /* some R300 cards have problem with this set to 0, when CRTC2 is
enabled.*/
- critical_point = 0x10;
- }
+ /*
+ Find the critical point of the display buffer.
+ */
+ critical_point= (uint32_t)(disp_drain_rate * disp_latency + 0.5);
- temp = info->SavedReg->grph_buffer_cntl;
- temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
- temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
- temp &= ~(RADEON_GRPH_START_REQ_MASK);
- if ((info->ChipFamily == CHIP_FAMILY_R350) &&
- (stop_req > 0x15)) {
- stop_req -= 0x10;
- }
- temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
+ /* ???? */
+ /*
+ temp = (info->SavedReg.grph_buffer_cntl &
RADEON_GRPH_CRITICAL_POINT_MASK) >> RADEON_GRPH_CRITICAL_POINT_SHIFT;
+ if (critical_point < temp) critical_point = temp;
+ */
+ if (info->DispPriority == 2) {
+ critical_point = 0;
+ }
- temp |= RADEON_GRPH_BUFFER_SIZE;
- temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
- RADEON_GRPH_CRITICAL_AT_SOF |
- RADEON_GRPH_STOP_CNTL);
- /*
- Write the result into the register.
- */
- OUTREG(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK)
|
- (critical_point <<
RADEON_GRPH_CRITICAL_POINT_SHIFT)));
+ /*
+ The critical point should never be above max_stop_req-4. Setting
+ GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
+ */
+ if (max_stop_req - critical_point < 4) critical_point = 0;
+
+ if (critical_point == 0 && mode2 && info->ChipFamily ==
CHIP_FAMILY_R300) {
+ /* some R300 cards have problem with this set to 0, when CRTC2 is
enabled.*/
+ critical_point = 0x10;
+ }
+
+ temp = info->SavedReg->grph_buffer_cntl;
+ temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
+ temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
+ temp &= ~(RADEON_GRPH_START_REQ_MASK);
+ if ((info->ChipFamily == CHIP_FAMILY_R350) &&
+ (stop_req > 0x15)) {
+ stop_req -= 0x10;
+ }
+ temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
+
+ temp |= RADEON_GRPH_BUFFER_SIZE;
+ temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
+ RADEON_GRPH_CRITICAL_AT_SOF |
+ RADEON_GRPH_STOP_CNTL);
+ /*
+ Write the result into the register.
+ */
+ OUTREG(RADEON_GRPH_BUFFER_CNTL, ((temp &
~RADEON_GRPH_CRITICAL_POINT_MASK) |
+ (critical_point <<
RADEON_GRPH_CRITICAL_POINT_SHIFT)));
#if 0
- if ((info->ChipFamily == CHIP_FAMILY_RS400) ||
- (info->ChipFamily == CHIP_FAMILY_RS480)) {
- /* attempt to program RS400 disp regs correctly ??? */
- temp = info->SavedReg->disp1_req_cntl1;
- temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
- RS400_DISP1_STOP_REQ_LEVEL_MASK);
- OUTREG(RS400_DISP1_REQ_CNTL1, (temp |
- (critical_point <<
RS400_DISP1_START_REQ_LEVEL_SHIFT) |
- (critical_point <<
RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
- temp = info->SavedReg->dmif_mem_cntl1;
- temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
- RS400_DISP1_CRITICAL_POINT_STOP_MASK);
- OUTREG(RS400_DMIF_MEM_CNTL1, (temp |
- (critical_point <<
RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
- (critical_point <<
RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
- }
+ if ((info->ChipFamily == CHIP_FAMILY_RS400) ||
+ (info->ChipFamily == CHIP_FAMILY_RS480)) {
+ /* attempt to program RS400 disp regs correctly ??? */
+ temp = info->SavedReg->disp1_req_cntl1;
+ temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
+ RS400_DISP1_STOP_REQ_LEVEL_MASK);
+ OUTREG(RS400_DISP1_REQ_CNTL1, (temp |
+ (critical_point <<
RS400_DISP1_START_REQ_LEVEL_SHIFT) |
+ (critical_point <<
RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
+ temp = info->SavedReg->dmif_mem_cntl1;
+ temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
+ RS400_DISP1_CRITICAL_POINT_STOP_MASK);
+ OUTREG(RS400_DMIF_MEM_CNTL1, (temp |
+ (critical_point <<
RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
+ (critical_point <<
RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
+ }
#endif
- xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
- "GRPH_BUFFER_CNTL from %x to %x\n",
- (unsigned int)info->SavedReg->grph_buffer_cntl,
- (unsigned int)INREG(RADEON_GRPH_BUFFER_CNTL));
+ xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, RADEON_LOGLEVEL_DEBUG,
+ "GRPH_BUFFER_CNTL from %x to %x\n",
+ (unsigned int)info->SavedReg->grph_buffer_cntl,
+ (unsigned int)INREG(RADEON_GRPH_BUFFER_CNTL));
+ }
if (mode2) {
stop_req = mode2->HDisplay * pixel_bytes2 / 16;
if (stop_req > max_stop_req) stop_req = max_stop_req;
+ /*
+ Find the drain rate of the display buffer.
+ */
+ disp_drain_rate2 = pix_clk2 / (16.0/pixel_bytes2);
+
temp = info->SavedReg->grph2_buffer_cntl;
temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
@@ -1629,7 +1637,10 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn,
RADEONInfoPtr info, int pixel_bytes2
critical_point2 = 0;
else {
read_return_rate = MIN(info->sclk,
info->mclk*(info->RamWidth*(info->IsDDR+1)/128));
- time_disp1_drop_priority = critical_point / (read_return_rate -
disp_drain_rate);
+ if (mode1)
+ time_disp1_drop_priority = critical_point / (read_return_rate -
disp_drain_rate);
+ else
+ time_disp1_drop_priority = 0;
critical_point2 = (uint32_t)((disp_latency +
time_disp1_drop_priority +
disp_latency) * disp_drain_rate2 + 0.5);
@@ -1681,45 +1692,6 @@ RADEONInitDispBandwidth2(ScrnInfoPtr pScrn,
RADEONInfoPtr info, int pixel_bytes2
}
void
-RADEONInitDispBandwidth(ScrnInfoPtr pScrn)
-{
- RADEONInfoPtr info = RADEONPTR(pScrn);
- xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
- DisplayModePtr mode1, mode2;
- int pixel_bytes2 = 0;
-
- if (info->IsPrimary || info->IsSecondary)
- mode1 = &xf86_config->crtc[0]->mode;
- else
- mode1 = info->CurrentLayout.mode;
- mode2 = NULL;
- pixel_bytes2 = info->CurrentLayout.pixel_bytes;
-
- if (xf86_config->num_crtc == 2) {
- pixel_bytes2 = 0;
- mode2 = NULL;
-
- if (xf86_config->crtc[1]->enabled && xf86_config->crtc[0]->enabled) {
- pixel_bytes2 = info->CurrentLayout.pixel_bytes;
- mode1 = &xf86_config->crtc[0]->mode;
- mode2 = &xf86_config->crtc[1]->mode;
- } else if (xf86_config->crtc[0]->enabled) {
- mode1 = &xf86_config->crtc[0]->mode;
- } else if (xf86_config->crtc[1]->enabled) {
- mode1 = &xf86_config->crtc[1]->mode;
- } else
- return;
- } else {
- if (xf86_config->crtc[0]->enabled)
- mode1 = &xf86_config->crtc[0]->mode;
- else
- return;
- }
-
- RADEONInitDispBandwidth2(pScrn, info, pixel_bytes2, mode1, mode2);
-}
-
-void
legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
DisplayModePtr adjusted_mode, int x, int y)
{
diff --git a/src/radeon.h b/src/radeon.h
index 0b8df3d..f68fa0f 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -817,7 +817,6 @@ do {
\
extern void legacy_crtc_dpms(xf86CrtcPtr crtc, int mode);
extern void legacy_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
DisplayModePtr adjusted_mode, int x, int y);
-extern void RADEONInitDispBandwidth(ScrnInfoPtr pScrn);
extern void RADEONRestoreCommonRegisters(ScrnInfoPtr pScrn,
RADEONSavePtr restore);
extern void RADEONRestoreCrtcRegisters(ScrnInfoPtr pScrn,
@@ -924,6 +923,7 @@ extern DisplayModePtr RADEONCrtcFindClosestMode(xf86CrtcPtr
crtc,
DisplayModePtr pMode);
extern void RADEONUnblank(ScrnInfoPtr pScrn);
extern Bool RADEONSetTiling(ScrnInfoPtr pScrn);
+extern void RADEONInitDispBandwidth(ScrnInfoPtr pScrn);
/* radeon_cursor.c */
extern Bool RADEONCursorInit(ScreenPtr pScreen);
diff --git a/src/radeon_crtc.c b/src/radeon_crtc.c
index c63b650..9e5f672 100644
--- a/src/radeon_crtc.c
+++ b/src/radeon_crtc.c
@@ -58,6 +58,10 @@ extern void atombios_crtc_mode_set(xf86CrtcPtr crtc,
DisplayModePtr adjusted_mode,
int x, int y);
extern void atombios_crtc_dpms(xf86CrtcPtr crtc, int mode);
+extern void
+RADEONInitDispBandwidthLegacy(ScrnInfoPtr pScrn,
+ DisplayModePtr mode1, int pixel_bytes1,
+ DisplayModePtr mode2, int pixel_bytes2);
void
radeon_crtc_dpms(xf86CrtcPtr crtc, int mode)
@@ -567,6 +571,40 @@ static const xf86CrtcFuncsRec radeon_crtc_funcs = {
.destroy = NULL, /* XXX */
};
+void
+RADEONInitDispBandwidth(ScrnInfoPtr pScrn)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+ xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
+ DisplayModePtr mode1 = NULL, mode2 = NULL;
+ int pixel_bytes1 = info->CurrentLayout.pixel_bytes;
+ int pixel_bytes2 = info->CurrentLayout.pixel_bytes;
+
+ if (xf86_config->num_crtc == 2) {
+ if (xf86_config->crtc[1]->enabled &&
+ xf86_config->crtc[0]->enabled) {
+ mode1 = &xf86_config->crtc[0]->mode;
+ mode2 = &xf86_config->crtc[1]->mode;
+ } else if (xf86_config->crtc[0]->enabled) {
+ mode1 = &xf86_config->crtc[0]->mode;
+ } else if (xf86_config->crtc[1]->enabled) {
+ mode2 = &xf86_config->crtc[1]->mode;
+ } else
+ return;
+ } else {
+ if (info->IsPrimary)
+ mode1 = &xf86_config->crtc[0]->mode;
+ else if (info->IsSecondary)
+ mode2 = &xf86_config->crtc[0]->mode;
+ else if (xf86_config->crtc[0]->enabled)
+ mode1 = &xf86_config->crtc[0]->mode;
+ else
+ return;
+ }
+
+ RADEONInitDispBandwidthLegacy(pScrn, mode1, pixel_bytes1, mode2,
pixel_bytes2);
+}
+
Bool RADEONAllocateControllers(ScrnInfoPtr pScrn, int mask)
{
RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
diff --git a/src/radeon_reg.h b/src/radeon_reg.h
index 936f8fa..3967f95 100644
--- a/src/radeon_reg.h
+++ b/src/radeon_reg.h
@@ -1032,6 +1032,8 @@
#define RADEON_OV0_BASE_ADDR 0x43c
#define RADEON_NB_TOM 0x15c
#define R300_MC_INIT_MISC_LAT_TIMER 0x180
+# define R300_MC_DISP0R_INIT_LAT_SHIFT 8
+# define R300_MC_DISP1R_INIT_LAT_SHIFT 12
#define RADEON_MCLK_CNTL 0x0012 /* PLL */
# define RADEON_FORCEON_MCLKA (1 << 16)
# define RADEON_FORCEON_MCLKB (1 << 17)
@@ -3431,12 +3433,12 @@
#define RS600_MC_STATUS 0x0
#define RS600_MC_STATUS_IDLE (1 << 0)
-#define AVIVO_MC_INDEX 0x0070
-#define R520_MC_STATUS 0x00
-#define R520_MC_STATUS_IDLE (1<<1)
-#define RV515_MC_STATUS 0x08
-#define RV515_MC_STATUS_IDLE (1<<4)
-#define AVIVO_MC_DATA 0x0074
+#define AVIVO_MC_INDEX 0x0070
+#define R520_MC_STATUS 0x00
+# define R520_MC_STATUS_IDLE (1 << 1)
+#define RV515_MC_STATUS 0x08
+# define RV515_MC_STATUS_IDLE (1 << 4)
+#define AVIVO_MC_DATA 0x0074
#define RV515_MC_FB_LOCATION 0x1
#define RV515_MC_AGP_LOCATION 0x2
@@ -3598,7 +3600,6 @@
#define AVIVO_DC_LUTA_WHITE_OFFSET_GREEN 0x64d4
#define AVIVO_DC_LUTA_WHITE_OFFSET_RED 0x64d8
-
#define AVIVO_D1MODE_DESKTOP_HEIGHT 0x652c
#define AVIVO_D1MODE_VIEWPORT_START 0x6580
#define AVIVO_D1MODE_VIEWPORT_SIZE 0x6584
commit e96ae005ee43fd51b93fbfb981301a8c4fce0e56
Author: Alex Deucher <[EMAIL PROTECTED]>
Date: Sat Jul 19 11:34:16 2008 -0400
Add oem quirk for external tmds setup on Dell Inspiron 8600
Noticed by fnord42 on IRC.
(cherry picked from commit ecb6347a3d7071890600c98c2addef3a8ca260ee)
diff --git a/src/legacy_output.c b/src/legacy_output.c
index 4df81ab..ccf59ba 100644
--- a/src/legacy_output.c
+++ b/src/legacy_output.c
@@ -48,6 +48,8 @@
#include "radeon_tv.h"
#include "radeon_atombios.h"
+#include "ati_pciids_gen.h"
+
static RADEONMonitorType radeon_detect_tv(ScrnInfoPtr pScrn);
static RADEONMonitorType radeon_detect_primary_dac(ScrnInfoPtr pScrn, Bool
color);
static RADEONMonitorType radeon_detect_tv_dac(ScrnInfoPtr pScrn, Bool color);
@@ -1017,9 +1019,14 @@ RADEONInitFP2Registers(xf86OutputPtr output,
RADEONSavePtr save,
RADEON_FP2_DVO_RATE_SEL_SDR);
- /* XXX: these may be oem specific */
+ /* XXX: these are oem specific */
if (IS_R300_VARIANT) {
- save->fp2_gen_cntl |= RADEON_FP2_PAD_FLOP_EN |
R300_FP2_DVO_CLOCK_MODE_SINGLE;
+ if ((info->Chipset == PCI_CHIP_RV350_NP) &&
+ (PCI_SUB_VENDOR_ID(info->PciInfo) == 0x1028) &&
+ (PCI_SUB_DEVICE_ID(info->PciInfo) == 0x2001))
+ save->fp2_gen_cntl |= R300_FP2_DVO_CLOCK_MODE_SINGLE; /* Dell
Inspiron 8600 */
+ else
+ save->fp2_gen_cntl |= RADEON_FP2_PAD_FLOP_EN |
R300_FP2_DVO_CLOCK_MODE_SINGLE;
#if 0
if (mode->Clock > 165000)
save->fp2_gen_cntl |= R300_FP2_DVO_DUAL_CHANNEL_EN;
commit c4619531386d7e2959676b9fda565b755c113cd3
Author: Benjamin Herrenschmidt <[EMAIL PROTECTED]>
Date: Thu Jul 17 14:37:05 2008 +1000
Fix console switch on R500
This patch fixes the console switch for me on R5xx.
There are two aspects to it:
- Fix the ordering of avivo_restore() to better match what's
happening in the driver & ATOM, properly locking/unlocking and
only enabling the CRTCs after everything has been properly
programmed.
- Don't ASIC_INIT if the card has any CRTC enabled. This is the
best I came up with for avoiding spurrious ASIC_INIT on cards that
-are- POSTed but don't have the BIOS coming from c0000 on x86. The
problem with spurrious ASIC_INIT is that we do it before we do
RADEONSave(), so that screws up the console switch.
Note that I think we also should save/restore the palette, I don't think
we do. right now, it's a minor issue for me because I fixed offb to be
able to set it on AVIVO's but it might still have to be done in the long
run.
Tested with a VGA analog setup on DACA and a DVI setup on TMDS 0. I
haven't tested any other combo but that should get us going.
Cheers,
Ben.
Signed-off-by: Dave Airlie <[EMAIL PROTECTED]>
(cherry picked from commit df53d12a06fad41f00cff849458cb358ab5e2098)
diff --git a/src/radeon_bios.c b/src/radeon_bios.c
index 51484ac..35e6960 100644
--- a/src/radeon_bios.c
+++ b/src/radeon_bios.c
@@ -382,6 +382,26 @@ RADEONGetBIOSInfo(ScrnInfoPtr pScrn, xf86Int10InfoPtr
pInt10)
info->MasterDataStart = RADEON_BIOS16 (info->ROMHeaderStart + 32);
}
+ /* We are a bit too quick at using this "unposted" to re-post the
+ * card. This causes some problems with VT switch on some machines,
+ * so let's work around this for now by only POSTing if none of the
+ * CRTCs are enabled
+ */
+ if (unposted && info->VBIOS) {
+ unsigned char *RADEONMMIO = info->MMIO;
+ uint32_t reg;
+
+ if (IS_AVIVO_VARIANT) {
+ reg = INREG(AVIVO_D1CRTC_CONTROL) |
INREG(AVIVO_D2CRTC_CONTROL);
+ if (reg & AVIVO_CRTC_EN)
+ unposted = FALSE;
+ } else {
+ reg = INREG(RADEON_CRTC_GEN_CNTL) |
INREG(RADEON_CRTC2_GEN_CNTL);
+ if (reg & RADEON_CRTC_EN)
+ unposted = FALSE;
+ }
+ }
+
if (unposted && info->VBIOS) {
if (info->IsAtomBios) {
if (!rhdAtomASICInit(info->atomBIOS))
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 041faa1..bb154de 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -4236,6 +4236,7 @@ avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save)
state->grph1.x_end = INREG(AVIVO_D1GRPH_X_END);
state->grph1.y_end = INREG(AVIVO_D1GRPH_Y_END);
+ state->grph1.desktop_height = INREG(AVIVO_D1MODE_DESKTOP_HEIGHT);
state->grph1.viewport_start = INREG(AVIVO_D1MODE_VIEWPORT_START);
state->grph1.viewport_size = INREG(AVIVO_D1MODE_VIEWPORT_SIZE);
@@ -4275,6 +4276,7 @@ avivo_save(ScrnInfoPtr pScrn, RADEONSavePtr save)
state->grph2.x_end = INREG(AVIVO_D2GRPH_X_END);
state->grph2.y_end = INREG(AVIVO_D2GRPH_Y_END);
+ state->grph2.desktop_height = INREG(AVIVO_D2MODE_DESKTOP_HEIGHT);
state->grph2.viewport_start = INREG(AVIVO_D2MODE_VIEWPORT_START);
state->grph2.viewport_size = INREG(AVIVO_D2MODE_VIEWPORT_SIZE);
@@ -4480,14 +4482,69 @@ avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore)
struct avivo_state *state = &restore->avivo;
int i, j;
- // OUTMC(pScrn, AVIVO_MC_MEMORY_MAP, state->mc_memory_map);
- // OUTREG(AVIVO_VGA_MEMORY_BASE, state->vga_memory_base);
- // OUTREG(AVIVO_VGA_FB_START, state->vga_fb_start);
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO, "avivo_restore !\n");
+
+ /* Disable VGA control for now.. maybe needs to be changed */
+ OUTREG(AVIVO_D1VGA_CONTROL, 0);
+ OUTREG(AVIVO_D2VGA_CONTROL, 0);
+
+ /* Disable CRTCs */
+ OUTREG(AVIVO_D1CRTC_CONTROL,
+ (INREG(AVIVO_D1CRTC_CONTROL) & ~0x300) | 0x01000000);
+ OUTREG(AVIVO_D2CRTC_CONTROL,
+ (INREG(AVIVO_D2CRTC_CONTROL) & ~0x300) | 0x01000000);
+ OUTREG(AVIVO_D1CRTC_CONTROL,
+ INREG(AVIVO_D1CRTC_CONTROL) & ~0x1);
+ OUTREG(AVIVO_D2CRTC_CONTROL,
+ INREG(AVIVO_D2CRTC_CONTROL) & ~0x1);
+ OUTREG(AVIVO_D1CRTC_CONTROL,
+ INREG(AVIVO_D1CRTC_CONTROL) | 0x100);
+ OUTREG(AVIVO_D2CRTC_CONTROL,
+ INREG(AVIVO_D2CRTC_CONTROL) | 0x100);
+
+ /* Lock graph registers */
+ OUTREG(AVIVO_D1GRPH_UPDATE, AVIVO_D1GRPH_UPDATE_LOCK);
+ OUTREG(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS, state->grph1.prim_surf_addr);
+ OUTREG(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS, state->grph1.sec_surf_addr);
+ OUTREG(AVIVO_D1GRPH_CONTROL, state->grph1.control);
+ OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_X, state->grph1.x_offset);
+ OUTREG(AVIVO_D1GRPH_SURFACE_OFFSET_Y, state->grph1.y_offset);
+ OUTREG(AVIVO_D1GRPH_X_START, state->grph1.x_start);
+ OUTREG(AVIVO_D1GRPH_Y_START, state->grph1.y_start);
+ OUTREG(AVIVO_D1GRPH_X_END, state->grph1.x_end);
+ OUTREG(AVIVO_D1GRPH_Y_END, state->grph1.y_end);
+ OUTREG(AVIVO_D1GRPH_PITCH, state->grph1.pitch);
+ OUTREG(AVIVO_D1GRPH_ENABLE, state->grph1.enable);
+ OUTREG(AVIVO_D1GRPH_UPDATE, 0);
+ OUTREG(AVIVO_D2GRPH_UPDATE, AVIVO_D1GRPH_UPDATE_LOCK);
+ OUTREG(AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS, state->grph2.prim_surf_addr);
+ OUTREG(AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS, state->grph2.sec_surf_addr);
+ OUTREG(AVIVO_D2GRPH_CONTROL, state->grph2.control);
+ OUTREG(AVIVO_D2GRPH_SURFACE_OFFSET_X, state->grph2.x_offset);
+ OUTREG(AVIVO_D2GRPH_SURFACE_OFFSET_Y, state->grph2.y_offset);
+ OUTREG(AVIVO_D2GRPH_X_START, state->grph2.x_start);
+ OUTREG(AVIVO_D2GRPH_Y_START, state->grph2.y_start);
+ OUTREG(AVIVO_D2GRPH_X_END, state->grph2.x_end);
+ OUTREG(AVIVO_D2GRPH_Y_END, state->grph2.y_end);
+ OUTREG(AVIVO_D2GRPH_PITCH, state->grph2.pitch);
+ OUTREG(AVIVO_D2GRPH_ENABLE, state->grph2.enable);
+ OUTREG(AVIVO_D2GRPH_UPDATE, 0);
- OUTREG(AVIVO_DC_CRTC_MASTER_EN, state->crtc_master_en);
- OUTREG(AVIVO_DC_CRTC_TV_CONTROL, state->crtc_tv_control);
+ /* Whack some mode regs too */
+ OUTREG(AVIVO_D1SCL_UPDATE, AVIVO_D1SCL_UPDATE_LOCK);
+ OUTREG(AVIVO_D1MODE_DESKTOP_HEIGHT, state->grph1.desktop_height);
+ OUTREG(AVIVO_D1MODE_VIEWPORT_START, state->grph1.viewport_start);
+ OUTREG(AVIVO_D1MODE_VIEWPORT_SIZE, state->grph1.viewport_size);
+ OUTREG(AVIVO_D1SCL_UPDATE, 0);
+
+ OUTREG(AVIVO_D2SCL_UPDATE, AVIVO_D1SCL_UPDATE_LOCK);
+ OUTREG(AVIVO_D2MODE_DESKTOP_HEIGHT, state->grph2.desktop_height);
+ OUTREG(AVIVO_D2MODE_VIEWPORT_START, state->grph2.viewport_start);
+ OUTREG(AVIVO_D2MODE_VIEWPORT_SIZE, state->grph2.viewport_size);
+ OUTREG(AVIVO_D2SCL_UPDATE, 0);
+ /* Set the PLL */
OUTREG(AVIVO_EXT1_PPLL_REF_DIV_SRC, state->pll1.ref_div_src);
OUTREG(AVIVO_EXT1_PPLL_REF_DIV, state->pll1.ref_div);
OUTREG(AVIVO_EXT1_PPLL_FB_DIV, state->pll1.fb_div);
@@ -4507,7 +4564,9 @@ avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore)
OUTREG(AVIVO_P2PLL_INT_SS_CNTL, state->pll2.int_ss_cntl);
OUTREG(AVIVO_PCLK_CRTC1_CNTL, state->crtc1.pll_source);
+ OUTREG(AVIVO_PCLK_CRTC2_CNTL, state->crtc2.pll_source);
+ /* Set the CRTC */
OUTREG(AVIVO_D1CRTC_H_TOTAL, state->crtc1.h_total);
OUTREG(AVIVO_D1CRTC_H_BLANK_START_END, state->crtc1.h_blank_start_end);
OUTREG(AVIVO_D1CRTC_H_SYNC_A, state->crtc1.h_sync_a);
@@ -4522,29 +4581,12 @@ avivo_restore(ScrnInfoPtr pScrn, RADEONSavePtr restore)
OUTREG(AVIVO_D1CRTC_V_SYNC_B, state->crtc1.v_sync_b);
OUTREG(AVIVO_D1CRTC_V_SYNC_B_CNTL, state->crtc1.v_sync_b_cntl);
- OUTREG(AVIVO_D1CRTC_CONTROL, state->crtc1.control);
- OUTREG(AVIVO_D1CRTC_BLANK_CONTROL, state->crtc1.blank_control);
OUTREG(AVIVO_D1CRTC_INTERLACE_CONTROL, state->crtc1.interlace_control);
OUTREG(AVIVO_D1CRTC_STEREO_CONTROL, state->crtc1.stereo_control);
OUTREG(AVIVO_D1CUR_CONTROL, state->crtc1.cursor_control);
- OUTREG(AVIVO_D1GRPH_ENABLE, state->grph1.enable);
- OUTREG(AVIVO_D1GRPH_CONTROL, state->grph1.control);
- OUTREG(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS, state->grph1.prim_surf_addr);
--
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