Author: branden
Date: 2004-04-21 11:41:55 -0500 (Wed, 21 Apr 2004)
New Revision: 1294
Modified:
trunk/debian/changelog
trunk/debian/patches/025_fix_dri_resume.diff
Log:
Re-christen next release as 4.3.0.dfsg.1, which uses a regenerated
.orig.tar.gz (maintained outside SVN). (Closes: #242865)
Update patch #025 to stop patching one of the files removed due to #242865.
Modified: trunk/debian/changelog
===================================================================
--- trunk/debian/changelog 2004-04-21 16:35:44 UTC (rev 1293)
+++ trunk/debian/changelog 2004-04-21 16:41:55 UTC (rev 1294)
@@ -1,5 +1,21 @@
-xfree86 (4.3.0-8) unstable; urgency=low
+xfree86 (4.3.0.dfsg.1-1) unstable; urgency=low
+ Changes by Branden Robinson:
+
+ * Re-generate .orig tar archive to eliminate files containing object code
+ with no corresponding source (none of which are actually needed or used by
+ XFree86 at build or run time). Add these files to the prune-non-free
+ script. Document these DFSG violations in copyright file. Update patch
+ #025 to stop patching one of the affected files (part of the kernel DRM
+ sources, so again, it's not used by XFree86 as built by Debian). Thanks
+ to Nathanael Nerode for his assistance with this issue. (Closes: #242865)
+
+ * The tar achive within the .orig tar archive (stored this way due to the
+ requirements of dbs) has been re-packed using gzip instead of bzip2. This
+ increases the size of the .orig tar archive by 10MB (a 21% increase), but
+ speeds unpacking of the stored tar achive from 2m49s to 39s on a 400MHz
+ PowerPC 740 (G3) processor with 512MB of RAM.
+
* Add FAQ entry about the <LSGT> key problem. Edit news item about the
<LSGT> problem to tidy up the wording a little and direct people to the
FAQ for more information.
@@ -265,15 +281,11 @@
* Rewrite prune-non-free script, and move it to debian/scripts directory.
- * Add files containing object code with no corresponding source to
- prune-non-free, and document DFSG violation in copyright file (see
- #242865; thanks, Nathanael Nerode).
-
* Fix typo in example XKB option in Danish translation of
xserver-xfree86/config/inputdevice/keyboard/options template (thanks,
Denis Barbier).
- -- Branden Robinson <[EMAIL PROTECTED]> Tue, 20 Apr 2004 22:38:29 -0500
+ -- Branden Robinson <[EMAIL PROTECTED]> Wed, 21 Apr 2004 03:21:33 -0500
xfree86 (4.3.0-7) unstable; urgency=medium
Modified: trunk/debian/patches/025_fix_dri_resume.diff
===================================================================
--- trunk/debian/patches/025_fix_dri_resume.diff 2004-04-21 16:35:44 UTC
(rev 1293)
+++ trunk/debian/patches/025_fix_dri_resume.diff 2004-04-21 16:41:55 UTC
(rev 1294)
@@ -185,203 +185,6 @@
[DRM_IOCTL_NR(DRM_IOCTL_RADEON_RESET)] = { radeon_engine_reset, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_RADEON_FULLSCREEN)] = { radeon_fullscreen, 1, 0 }, \
[DRM_IOCTL_NR(DRM_IOCTL_RADEON_SWAP)] = { radeon_cp_swap, 1, 0 }, \
---- xc/programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon_cp.c
2003/02/04 01:48:38 1.5
-+++ xc/programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon_cp.c
2003/02/07 23:56:53
-@@ -1283,6 +1283,177 @@
- return 0;
- }
-
-+/* This code will reinit the Radeon CP hardware after a resume from disc.
-+ * AFAIK, it would be very difficult to pickle the state at suspend time, so
-+ * here we make sure that all Radeon hardware initialisation is re-done
without
-+ * affecting running applications. This function is called
radeon_do_resume_cp()
-+ * as it was derived from radeon_init_cp, where most of the initialisation
takes
-+ * place during DRI init.
-+ *
-+ * This patch is NOT to be confused with my and Michel Daenzer's earlier DRI
-+ * reinit work, which de- and re-initialised the complete DRI at every VT
-+ * switch.
-+ *
-+ * Charl P. Botha <http://cpbotha.net>
-+ */
-+static int radeon_do_resume_cp( drm_device_t *dev)
-+{
-+ drm_radeon_private_t *dev_priv;
-+ u32 tmp;
-+ DRM_DEBUG( "\n" );
-+
-+ DRM_DEBUG("Starting radeon_do_resume_cp()\n");
-+
-+ /* get the existing dev_private */
-+ dev_priv = dev->dev_private;
-+
-+#if !defined(PCIGART_ENABLED)
-+ /* PCI support is not 100% working, so we disable it here.
-+ */
-+ if ( dev_priv->is_pci ) {
-+ DRM_ERROR( "PCI GART not yet supported for Radeon!\n" );
-+ radeon_do_cleanup_cp(dev);
-+ return DRM_ERR(EINVAL);
-+ }
-+#endif
-+
-+ if ( dev_priv->is_pci && !dev->sg ) {
-+ DRM_ERROR( "PCI GART memory not allocated!\n" );
-+ radeon_do_cleanup_cp(dev);
-+ return DRM_ERR(EINVAL);
-+ }
-+
-+ if ( dev_priv->usec_timeout < 1 ||
-+ dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT ) {
-+ DRM_DEBUG( "TIMEOUT problem!\n" );
-+ radeon_do_cleanup_cp(dev);
-+ return DRM_ERR(EINVAL);
-+ }
-+
-+ if ( ( dev_priv->cp_mode != RADEON_CSQ_PRIBM_INDDIS ) &&
-+ ( dev_priv->cp_mode != RADEON_CSQ_PRIBM_INDBM ) ) {
-+ DRM_DEBUG( "BAD cp_mode (%x)!\n", dev_priv->cp_mode );
-+ radeon_do_cleanup_cp(dev);
-+ return DRM_ERR(EINVAL);
-+ }
-+
-+ if(!dev_priv->sarea) {
-+ DRM_ERROR("could not find sarea!\n");
-+ radeon_do_cleanup_cp(dev);
-+ return DRM_ERR(EINVAL);
-+ }
-+
-+ if(!dev_priv->fb) {
-+ DRM_ERROR("could not find framebuffer!\n");
-+ radeon_do_cleanup_cp(dev);
-+ return DRM_ERR(EINVAL);
-+ }
-+
-+ if(!dev_priv->mmio) {
-+ DRM_ERROR("could not find mmio region!\n");
-+ radeon_do_cleanup_cp(dev);
-+ return DRM_ERR(EINVAL);
-+ }
-+
-+ if(!dev_priv->cp_ring) {
-+ DRM_ERROR("could not find cp ring region!\n");
-+ radeon_do_cleanup_cp(dev);
-+ return DRM_ERR(EINVAL);
-+ }
-+
-+ if(!dev_priv->ring_rptr) {
-+ DRM_ERROR("could not find ring read pointer!\n");
-+ radeon_do_cleanup_cp(dev);
-+ return DRM_ERR(EINVAL);
-+ }
-+
-+ if(!dev_priv->buffers) {
-+ DRM_ERROR("could not find dma buffer region!\n");
-+ radeon_do_cleanup_cp(dev);
-+ return DRM_ERR(EINVAL);
-+ }
-+
-+ if ( !dev_priv->is_pci ) {
-+ if(!dev_priv->agp_textures) {
-+ DRM_ERROR("could not find agp texture region!\n");
-+ radeon_do_cleanup_cp(dev);
-+ return DRM_ERR(EINVAL);
-+ }
-+ }
-+
-+ if ( !dev_priv->is_pci ) {
-+ if(!dev_priv->cp_ring->handle ||
-+ !dev_priv->ring_rptr->handle ||
-+ !dev_priv->buffers->handle) {
-+ DRM_ERROR("could not find ioremap agp regions!\n");
-+ radeon_do_cleanup_cp(dev);
-+ return DRM_ERR(EINVAL);
-+ }
-+ } else {
-+ DRM_DEBUG( "dev_priv->cp_ring->handle %p\n",
-+ dev_priv->cp_ring->handle );
-+ DRM_DEBUG( "dev_priv->ring_rptr->handle %p\n",
-+ dev_priv->ring_rptr->handle );
-+ DRM_DEBUG( "dev_priv->buffers->handle %p\n",
-+ dev_priv->buffers->handle );
-+ }
-+
-+
-+ DRM_DEBUG( "dev_priv->agp_size %d\n",
-+ dev_priv->agp_size );
-+ DRM_DEBUG( "dev_priv->agp_vm_start 0x%x\n",
-+ dev_priv->agp_vm_start );
-+ DRM_DEBUG( "dev_priv->agp_buffers_offset 0x%lx\n",
-+ dev_priv->agp_buffers_offset );
-+
-+#if __REALLY_HAVE_SG
-+ if ( dev_priv->is_pci ) {
-+ /* I'm not so sure about this ati_picgart_init after at
resume-time... */
-+ if (!DRM(ati_pcigart_init)( dev, &dev_priv->phys_pci_gart,
-+ &dev_priv->bus_pci_gart)) {
-+ DRM_ERROR( "failed to init PCI GART!\n" );
-+ radeon_do_cleanup_cp(dev);
-+ return DRM_ERR(ENOMEM);
-+ }
-+
-+ tmp = RADEON_READ( RADEON_AIC_CNTL )
-+ | RADEON_PCIGART_TRANSLATE_EN;
-+ RADEON_WRITE( RADEON_AIC_CNTL, tmp );
-+
-+ /* set PCI GART page-table base address
-+ */
-+ RADEON_WRITE( RADEON_AIC_PT_BASE, dev_priv->bus_pci_gart );
-+
-+ /* set address range for PCI address translate
-+ */
-+ RADEON_WRITE( RADEON_AIC_LO_ADDR, dev_priv->agp_vm_start );
-+ RADEON_WRITE( RADEON_AIC_HI_ADDR, dev_priv->agp_vm_start
-+ + dev_priv->agp_size - 1);
-+
-+ /* Turn off AGP aperture -- is this required for PCIGART?
-+ */
-+ RADEON_WRITE( RADEON_MC_AGP_LOCATION, 0xffffffc0 ); /* ?? */
-+ RADEON_WRITE( RADEON_AGP_COMMAND, 0 ); /* clear AGP_COMMAND */
-+ } else {
-+#endif /* __REALLY_HAVE_SG */
-+ /* Turn off PCI GART
-+ */
-+ tmp = RADEON_READ( RADEON_AIC_CNTL )
-+ & ~RADEON_PCIGART_TRANSLATE_EN;
-+ RADEON_WRITE( RADEON_AIC_CNTL, tmp );
-+#if __REALLY_HAVE_SG
-+ }
-+#endif /* __REALLY_HAVE_SG */
-+
-+ radeon_cp_load_microcode( dev_priv );
-+ radeon_cp_init_ring_buffer( dev, dev_priv );
-+
-+ radeon_do_engine_reset( dev );
-+
-+ return 0;
-+}
-+
-+
- int radeon_cp_init( DRM_IOCTL_ARGS )
- {
- DRM_DEVICE;
-@@ -1402,6 +1573,16 @@
-
- return radeon_do_cp_idle( dev_priv );
- }
-+
-+/* Added by Charl P. Botha to call radeon_do_resume_cp().
-+ */
-+int radeon_cp_resume( DRM_IOCTL_ARGS )
-+{
-+ DRM_DEVICE;
-+
-+ return radeon_do_resume_cp(dev);
-+}
-+
-
- int radeon_engine_reset( DRM_IOCTL_ARGS )
- {
--- xc/programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon_drm.h
2003/02/04 03:02:00 1.2
+++ xc/programs/Xserver/hw/xfree86/os-support/shared/drm/kernel/radeon_drm.h
2003/02/07 23:56:53
@@ -391,6 +391,8 @@
