I did a simple-minded port of the milky screen patch by Hui Yu that I
found at:
http://marc.theaimsgroup.com/?l=xfree86&m=105582853120655&w=2
I think it includes the following issues from what google has been able
to find:
274. Do not drop H&V sync during screen blanking for Radeon
(Bugzilla #320, Michael Breuer, Hui [EMAIL PROTECTED]).
273. Let out-of-limit pixel clocks only use the frequency below pll output
lower limit for Radeons (Bugzilla #262, John Vickers, Hui [EMAIL
PROTECTED]).
272. Add support for Radeon cards with DAC/TMDS wire up in different ways
from what the driver was originally programmed to; includes support
for dual DVI cards (Hui [EMAIL PROTECTED]).
271. Add Radeon DPMS handling for flat panels (Bugzilla #26, Hui [EMAIL
PROTECTED]).
270. Decreased the retry loops in DDC probing so that Radeon startup
time won't be too long in the worst case (Hui [EMAIL PROTECTED]).
269. Fix Radeon Asic bug in RMX unit of IGP chips (Hui [EMAIL PROTECTED]).
268. Fix Radeon register initialization for RGB offset to fix the
"milky-screen" problem (Bugzilla #351, Hui [EMAIL PROTECTED]).
267. Add support for new Radeon chips: R350(9800), RV350(9600,M10),
RS250(IGP7000), RS300(IGP9000), RV280(9200) (Hui [EMAIL PROTECTED]).
I have no idea if it works on any other card but mine, but it did fix my
problem. I would have liked to separate out just the milky screen fix,
but I have no idea where to start.
Wish I had seen the sw_cursor fix as that is a lot less work. Haven't
tried it to see if it works for me yet.
Here is the patch in case anyone is interested but if sw_cursor works,
that's a much safer fix.
Jon
diff -urN xc.orig/programs/Xserver/hw/xfree86/common/xf86PciInfo.h xc/programs/Xserver/hw/xfree86/common/xf86PciInfo.h
--- xc.orig/programs/Xserver/hw/xfree86/common/xf86PciInfo.h 2004-04-03 15:35:30.000000000 -0500
+++ xc/programs/Xserver/hw/xfree86/common/xf86PciInfo.h 2004-04-03 15:44:03.000000000 -0500
@@ -93,10 +93,20 @@
#define PCI_CHIP_R300_AE 0x4145
#define PCI_CHIP_R300_AF 0x4146
#define PCI_CHIP_R300_AG 0x4147
+#define PCI_CHIP_R350_AH 0x4148
+#define PCI_CHIP_R350_AI 0x4149
+#define PCI_CHIP_R350_AJ 0x414A
+#define PCI_CHIP_R350_AK 0x414B
+#define PCI_CHIP_RV350_AP 0x4150
+#define PCI_CHIP_RV350_AR 0x4152
#define PCI_CHIP_MACH32 0x4158
+#define PCI_CHIP_RS250_4237 0x4237
#define PCI_CHIP_R200_BB 0x4242
+#define PCI_CHIP_RS100_4336 0x4336
+#define PCI_CHIP_RS200_4337 0x4337
#define PCI_CHIP_MACH64CT 0x4354
#define PCI_CHIP_MACH64CX 0x4358
+#define PCI_CHIP_RS250_4437 0x4437
#define PCI_CHIP_MACH64ET 0x4554
#define PCI_CHIP_MACH64GB 0x4742
#define PCI_CHIP_MACH64GD 0x4744
@@ -146,6 +156,11 @@
#define PCI_CHIP_R300_NE 0x4E45
#define PCI_CHIP_R300_NF 0x4E46
#define PCI_CHIP_R300_NG 0x4E47
+#define PCI_CHIP_R350_NH 0x4E48
+#define PCI_CHIP_R350_NI 0x4E49
+#define PCI_CHIP_R350_NJ 0x4E4A
+#define PCI_CHIP_R350_NK 0x4E4B
+#define PCI_CHIP_RV350_NP 0x4E50
#define PCI_CHIP_RAGE128PA 0x5041
#define PCI_CHIP_RAGE128PB 0x5042
#define PCI_CHIP_RAGE128PC 0x5043
@@ -217,6 +232,10 @@
#define PCI_CHIP_MACH64VT 0x5654
#define PCI_CHIP_MACH64VU 0x5655
#define PCI_CHIP_MACH64VV 0x5656
+#define PCI_CHIP_RS300_5834 0x5834
+#define PCI_CHIP_RS300_5835 0x5835
+#define PCI_CHIP_RS300_5836 0x5836
+#define PCI_CHIP_RS300_5837 0x5837
#define PCI_CHIP_RV280_5960 0x5960
#define PCI_CHIP_RV280_5961 0x5961
#define PCI_CHIP_RV280_5962 0x5962
diff -urN xc.orig/programs/Xserver/hw/xfree86/drivers/ati/atichip.c xc/programs/Xserver/hw/xfree86/drivers/ati/atichip.c
--- xc.orig/programs/Xserver/hw/xfree86/drivers/ati/atichip.c 2004-04-03 15:35:30.000000000 -0500
+++ xc/programs/Xserver/hw/xfree86/drivers/ati/atichip.c 2004-04-03 15:44:03.000000000 -0500
@@ -84,17 +84,23 @@
"ATI Rage 128 Mobility M3",
"ATI Rage 128 Mobility M4",
"ATI unknown Rage 128"
- "ATI Radeon",
- "ATI Radeon VE",
+ "ATI Radeon 7200",
+ "ATI Radeon 7000 (VE)",
"ATI Radeon Mobility M6",
"ATI Radeon IGP320",
- "ATI Radeon Mobility M7",
"ATI Radeon IGP330/340/350",
- "ATI Radeon 8500",
+ "ATI Radeon 7000 IGP",
"ATI Radeon 7500",
+ "ATI Radeon Mobility M7",
+ "ATI Radeon 8500/9100",
"ATI Radeon 9000",
"ATI Radeon Mobility M9",
- "ATI Radeon 9700",
+ "ATI Radeon 9000 IGP",
+ "ATI Radeon 9200",
+ "ATI Radeon Mobility M9+",
+ "ATI Radeon 9700/9500",
+ "ATI Radeon 9600",
+ "ATI Radeon 9800",
"ATI Rage HDTV"
};
@@ -639,6 +645,10 @@
case NewChipID('C', '7'):
return ATI_CHIP_RS200;
+ case NewChipID('D', '7'):
+ case NewChipID('B', '7'):
+ return ATI_CHIP_RS250;
+
case NewChipID('L', 'W'):
case NewChipID('L', 'X'):
return ATI_CHIP_RADEONMOBILITY7;
@@ -675,6 +685,10 @@
case NewChipID('L', 'g'):
return ATI_CHIP_RADEONMOBILITY9;
+ case NewChipID('X', '4'):
+ case NewChipID('X', '5'):
+ return ATI_CHIP_RS300;
+
case NewChipID('Y', '\''):
case NewChipID('Y', 'a'):
case NewChipID('Y', 'b'):
@@ -695,6 +709,16 @@
case NewChipID('N', 'G'):
return ATI_CHIP_R300;
+ case NewChipID('A', 'K'):
+ case NewChipID('N', 'H'):
+ case NewChipID('N', 'K'):
+ return ATI_CHIP_R350;
+
+ case NewChipID('N', 'P'):
+ case NewChipID('A', 'P'):
+ case NewChipID('A', 'R'):
+ return ATI_CHIP_RV350;
+
case NewChipID('H', 'D'):
return ATI_CHIP_HDTV;
diff -urN xc.orig/programs/Xserver/hw/xfree86/drivers/ati/atichip.h xc/programs/Xserver/hw/xfree86/drivers/ati/atichip.h
--- xc.orig/programs/Xserver/hw/xfree86/drivers/ati/atichip.h 2004-04-03 15:35:29.000000000 -0500
+++ xc/programs/Xserver/hw/xfree86/drivers/ati/atichip.h 2004-04-03 15:44:03.000000000 -0500
@@ -90,15 +90,19 @@
ATI_CHIP_RADEONVE, /* Radeon VE */
ATI_CHIP_RADEONMOBILITY6, /* Radeon M6 */
ATI_CHIP_RS100, /* IGP320 */
- ATI_CHIP_RADEONMOBILITY7, /* Radeon M7 */
ATI_CHIP_RS200, /* IGP340 */
- ATI_CHIP_R200, /* R200 */
+ ATI_CHIP_RS250, /* Radoen 7000 IGP */
ATI_CHIP_RV200, /* RV200 */
+ ATI_CHIP_RADEONMOBILITY7, /* Radeon M7 */
+ ATI_CHIP_R200, /* R200 */
ATI_CHIP_RV250, /* RV250 */
ATI_CHIP_RADEONMOBILITY9, /* Radeon M9 */
+ ATI_CHIP_RS300, /* Radoen 9000 IGP */
ATI_CHIP_RV280, /* RV250 */
ATI_CHIP_RADEONMOBILITY9PLUS, /* Radeon M9+ */
ATI_CHIP_R300, /* R300 */
+ ATI_CHIP_RV350, /* RV350 */
+ ATI_CHIP_R350, /* R350 */
ATI_CHIP_HDTV /* HDTV */
} ATIChipType;
diff -urN xc.orig/programs/Xserver/hw/xfree86/drivers/ati/atiprobe.c xc/programs/Xserver/hw/xfree86/drivers/ati/atiprobe.c
--- xc.orig/programs/Xserver/hw/xfree86/drivers/ati/atiprobe.c 2004-04-03 15:35:29.000000000 -0500
+++ xc/programs/Xserver/hw/xfree86/drivers/ati/atiprobe.c 2004-04-03 15:44:03.000000000 -0500
@@ -1733,14 +1733,18 @@
case ATI_CHIP_RADEONMOBILITY6:
case ATI_CHIP_RS100:
case ATI_CHIP_RS200:
+ case ATI_CHIP_RS250:
case ATI_CHIP_RADEONMOBILITY7:
case ATI_CHIP_R200:
case ATI_CHIP_RV200:
case ATI_CHIP_RV250:
case ATI_CHIP_RADEONMOBILITY9:
+ case ATI_CHIP_RS300:
case ATI_CHIP_RV280:
case ATI_CHIP_RADEONMOBILITY9PLUS:
case ATI_CHIP_R300:
+ case ATI_CHIP_RV350:
+ case ATI_CHIP_R350:
DoRadeon = TRUE;
continue;
diff -urN xc.orig/programs/Xserver/hw/xfree86/drivers/ati/radeon.h xc/programs/Xserver/hw/xfree86/drivers/ati/radeon.h
--- xc.orig/programs/Xserver/hw/xfree86/drivers/ati/radeon.h 2004-04-03 15:35:29.000000000 -0500
+++ xc/programs/Xserver/hw/xfree86/drivers/ati/radeon.h 2004-04-03 15:44:03.000000000 -0500
@@ -142,6 +142,7 @@
CARD32 crtc_offset;
CARD32 crtc_offset_cntl;
CARD32 crtc_pitch;
+ CARD32 disp_merge_cntl;
/* CRTC2 registers */
CARD32 crtc2_gen_cntl;
@@ -149,6 +150,7 @@
CARD32 dac2_cntl;
CARD32 disp_output_cntl;
CARD32 disp_hw_debug;
+ CARD32 disp2_merge_cntl;
CARD32 crtc2_h_total_disp;
CARD32 crtc2_h_sync_strt_wid;
CARD32 crtc2_v_total_disp;
@@ -246,21 +248,18 @@
typedef enum {
CHIP_FAMILY_UNKNOW,
CHIP_FAMILY_LEGACY,
- CHIP_FAMILY_R128,
- CHIP_FAMILY_M3,
CHIP_FAMILY_RADEON,
- CHIP_FAMILY_VE,
- CHIP_FAMILY_M6,
+ CHIP_FAMILY_RV100,
CHIP_FAMILY_RS100, /* U1 (IGP320M) or A3 (IGP320)*/
CHIP_FAMILY_RV200,
- CHIP_FAMILY_M7,
- CHIP_FAMILY_RS200, /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350) */
+ CHIP_FAMILY_RS200, /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350), RS250 (IGP 7000) */
CHIP_FAMILY_R200,
CHIP_FAMILY_RV250,
- CHIP_FAMILY_M9,
+ CHIP_FAMILY_RS300, /* Radeon 9000 IGP */
CHIP_FAMILY_RV280,
- CHIP_FAMILY_M9PLUS,
- CHIP_FAMILY_R300
+ CHIP_FAMILY_R300,
+ CHIP_FAMILY_R350,
+ CHIP_FAMILY_RV350
} RADEONChipFamily;
typedef struct {
@@ -291,6 +290,7 @@
RADEONConnectorType ConnectorType;
Bool HasCRTC2; /* All cards except original Radeon */
Bool IsMobility; /* Mobile chips for laptops */
+ Bool IsIGP; /* IGP chips */
Bool IsSecondary; /* Second Screen */
Bool IsSwitching; /* Flag for switching mode */
Bool Clone; /* Force second head to clone primary*/
diff -urN xc.orig/programs/Xserver/hw/xfree86/drivers/ati/radeon.man xc/programs/Xserver/hw/xfree86/drivers/ati/radeon.man
--- xc.orig/programs/Xserver/hw/xfree86/drivers/ati/radeon.man 2004-04-03 15:35:29.000000000 -0500
+++ xc/programs/Xserver/hw/xfree86/drivers/ati/radeon.man 2004-04-03 15:44:03.000000000 -0500
@@ -16,7 +16,7 @@
is a XFree86 driver for ATI RADEON based video cards. It contains
full support for 8, 15, 16 and 24 bit pixel depths, dual-head setup,
flat panel, hardware 2D acceleration, hardware 3D acceleration
-(except R300 cards), hardware cursor, XV extension, Xinerama extension.
+(except R300 and IGP series cards), hardware cursor, XV extension, Xinerama extension.
.SH SUPPORTED HARDWARE
The
.B radeon
@@ -29,13 +29,16 @@
Radeon 7000(VE), M6
.TP 12
.B RS100
-Radeon IGP320(M)
+Radeon IGP320(M) (2D only)
.TP 12
.B RV200
Radeon 7500, M7
.TP 12
.B RS200
-Radeon IGP330(M)/IGP340(M)
+Radeon IGP330(M)/IGP340(M) (2D only)
+.TP 12
+.B RS250
+Radeon Mobility 7000 IGP (2D only)
.TP 12
.B R200
Radeon 8500, 9100, FireGL 8800/8700
@@ -43,11 +46,20 @@
.B RV250
Radeon 9000, M9
.TP 12
-.B R280
-Radeon 9200
+.B RS300
+Radeon 9000 IGP (2D only)
+.TP 12
+.B RV280
+Radeon 9200, M9+
.TP 12
.B R300
-Radeon 9700PRO/9700/9500PRO/9500, FireGL X1/Z1
+Radeon 9700PRO/9700/9500PRO/9500, FireGL X1/Z1 (2D only)
+.TP 12
+.B R350
+Radeon 9800PRO (2D only)
+.TP 12
+.B RV350
+Radeon 9600PRO/9600, M10 (2D only)
.SH CONFIGURATION DETAILS
Please refer to XF86Config(__filemansuffix__) for general configuration
diff -urN xc.orig/programs/Xserver/hw/xfree86/drivers/ati/radeon_accel.c xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_accel.c
--- xc.orig/programs/Xserver/hw/xfree86/drivers/ati/radeon_accel.c 2004-04-03 15:35:29.000000000 -0500
+++ xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_accel.c 2004-04-03 15:44:03.000000000 -0500
@@ -207,7 +207,9 @@
host_path_cntl = INREG(RADEON_HOST_PATH_CNTL);
rbbm_soft_reset = INREG(RADEON_RBBM_SOFT_RESET);
- if (info->ChipFamily == CHIP_FAMILY_R300) {
+ if ((info->ChipFamily == CHIP_FAMILY_R300) ||
+ (info->ChipFamily == CHIP_FAMILY_R350) ||
+ (info->ChipFamily == CHIP_FAMILY_RV350)) {
CARD32 tmp;
OUTREG(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
@@ -243,7 +245,9 @@
INREG(RADEON_HOST_PATH_CNTL);
OUTREG(RADEON_HOST_PATH_CNTL, host_path_cntl);
- if (info->ChipFamily != CHIP_FAMILY_R300)
+ if ((info->ChipFamily != CHIP_FAMILY_R300) &&
+ (info->ChipFamily != CHIP_FAMILY_R350) &&
+ (info->ChipFamily != CHIP_FAMILY_RV350))
OUTREG(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
OUTREG(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
@@ -271,7 +275,9 @@
*/
/* Turn of all automatic flushing - we'll do it all */
- if (info->ChipFamily != CHIP_FAMILY_R300)
+ if ((info->ChipFamily != CHIP_FAMILY_R300) &&
+ (info->ChipFamily != CHIP_FAMILY_R350) &&
+ (info->ChipFamily != CHIP_FAMILY_RV350))
OUTREG(RADEON_RB2D_DSTCACHE_MODE, 0);
pitch64 = ((pScrn->displayWidth * (pScrn->bitsPerPixel / 8) + 0x3f)) >> 6;
diff -urN xc.orig/programs/Xserver/hw/xfree86/drivers/ati/radeon_dri.c xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_dri.c
--- xc.orig/programs/Xserver/hw/xfree86/drivers/ati/radeon_dri.c 2004-04-03 15:35:30.000000000 -0500
+++ xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_dri.c 2004-04-03 15:44:03.000000000 -0500
@@ -718,13 +718,6 @@
if ((vendor == PCI_VENDOR_AMD) &&
(device == PCI_CHIP_AMD761)) {
- /* The combination of 761 with MOBILITY chips will lockup the
- * system; however, currently there is no such a product on the
- * market, so this is not yet a problem.
- */
- if ((info->ChipFamily == CHIP_FAMILY_M6) ||
- (info->ChipFamily == CHIP_FAMILY_M7))
- return FALSE;
/* Disable fast write for AMD 761 chipset, since they cause
* lockups when enabled.
@@ -1000,7 +993,9 @@
memset(&drmInfo, 0, sizeof(drmRadeonInit));
- if ( info->ChipFamily >= CHIP_FAMILY_R200 )
+ if ((info->ChipFamily == CHIP_FAMILY_R200) ||
+ (info->ChipFamily == CHIP_FAMILY_RV250) ||
+ (info->ChipFamily == CHIP_FAMILY_RV280) )
drmInfo.func = DRM_RADEON_INIT_R200_CP;
else
drmInfo.func = DRM_RADEON_INIT_CP;
@@ -1220,6 +1215,9 @@
if ( info->ChipFamily >= CHIP_FAMILY_R200 )
pDRIInfo->clientDriverName = R200_DRIVER_NAME;
+ else if ((info->ChipFamily == CHIP_FAMILY_RV250) ||
+ (info->ChipFamily == CHIP_FAMILY_RV280))
+ pDRIInfo->clientDriverName = RV250_DRIVER_NAME;
else
pDRIInfo->clientDriverName = RADEON_DRIVER_NAME;
@@ -1343,7 +1341,9 @@
if (version) {
int req_minor, req_patch;
- if ( info->ChipFamily >= CHIP_FAMILY_R200 ) {
+ if ((info->ChipFamily == CHIP_FAMILY_R200) ||
+ (info->ChipFamily == CHIP_FAMILY_RV250) ||
+ (info->ChipFamily == CHIP_FAMILY_RV280)) {
req_minor = 5;
req_patch = 0;
} else {
diff -urN xc.orig/programs/Xserver/hw/xfree86/drivers/ati/radeon_driver.c xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_driver.c
--- xc.orig/programs/Xserver/hw/xfree86/drivers/ati/radeon_driver.c 2004-04-03 15:35:30.000000000 -0500
+++ xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_driver.c 2004-04-03 15:44:03.000000000 -0500
@@ -876,7 +876,7 @@
OUTREG(info->DDCReg,
INREG(info->DDCReg) & ~(RADEON_GPIO_EN_1));
- for (i = 0; i < 10; i++) {
+ for (i = 0; i < 3; i++) {
usleep(15000);
if (INREG(info->DDCReg) & RADEON_GPIO_Y_1)
break;
@@ -900,7 +900,7 @@
usleep(15000);
OUTREG(info->DDCReg,
INREG(info->DDCReg) & ~(RADEON_GPIO_EN_1));
- for (i = 0; i < 50; i++) {
+ for (i = 0; i < 5; i++) {
usleep(15000);
if (INREG(info->DDCReg) & RADEON_GPIO_Y_1)
break;
@@ -973,7 +973,8 @@
ulData |= (RADEON_DAC_FORCE_BLANK_OFF_EN
|RADEON_DAC_FORCE_DATA_EN
|RADEON_DAC_FORCE_DATA_SEL_MASK);
- if (info->ChipFamily == CHIP_FAMILY_RV250)
+ if ((info->ChipFamily == CHIP_FAMILY_RV250) ||
+ (info->ChipFamily == CHIP_FAMILY_RV280))
ulData |= (0x01b6 << RADEON_DAC_FORCE_DATA_SHIFT);
else
ulData |= (0x01ac << RADEON_DAC_FORCE_DATA_SHIFT);
@@ -1128,7 +1129,9 @@
| RADEON_RED_MX_FORCE_DAC_DATA
| RADEON_GRN_MX_FORCE_DAC_DATA
| RADEON_BLU_MX_FORCE_DAC_DATA);
- if(info->ChipFamily == CHIP_FAMILY_R300)
+ if ((info->ChipFamily == CHIP_FAMILY_R300) ||
+ (info->ChipFamily == CHIP_FAMILY_R350) ||
+ (info->ChipFamily == CHIP_FAMILY_RV350))
ulData |= 0x180 << RADEON_TV_FORCE_DAC_DATA_SHIFT;
else
ulData |= 0x1f5 << RADEON_TV_FORCE_DAC_DATA_SHIFT;
@@ -1925,28 +1928,38 @@
info->HasCRTC2 = TRUE;
info->IsMobility = FALSE;
+ info->IsIGP = FALSE;
switch (info->Chipset) {
case PCI_CHIP_RADEON_LY:
case PCI_CHIP_RADEON_LZ:
info->IsMobility = TRUE;
- info->ChipFamily = CHIP_FAMILY_M6;
+ info->ChipFamily = CHIP_FAMILY_RV100;
break;
case PCI_CHIP_RV100_QY:
case PCI_CHIP_RV100_QZ:
- info->ChipFamily = CHIP_FAMILY_VE;
+ info->ChipFamily = CHIP_FAMILY_RV100;
break;
case PCI_CHIP_RS100_4336:
info->IsMobility = TRUE;
case PCI_CHIP_RS100_4136:
info->ChipFamily = CHIP_FAMILY_RS100;
+ info->IsIGP = TRUE;
break;
case PCI_CHIP_RS200_4337:
info->IsMobility = TRUE;
case PCI_CHIP_RS200_4137:
info->ChipFamily = CHIP_FAMILY_RS200;
+ info->IsIGP = TRUE;
+ break;
+
+ case PCI_CHIP_RS250_4437:
+ info->IsMobility = TRUE;
+ case PCI_CHIP_RS250_4237:
+ info->ChipFamily = CHIP_FAMILY_RS200;
+ info->IsIGP = TRUE;
break;
case PCI_CHIP_R200_BB:
@@ -1974,7 +1987,7 @@
case PCI_CHIP_RADEON_LW:
case PCI_CHIP_RADEON_LX:
info->IsMobility = TRUE;
- info->ChipFamily = CHIP_FAMILY_M7;
+ info->ChipFamily = CHIP_FAMILY_RV200;
break;
case PCI_CHIP_RV250_Id:
@@ -1989,7 +2002,14 @@
case PCI_CHIP_RV250_Lf:
case PCI_CHIP_RV250_Lg:
info->IsMobility = TRUE;
- info->ChipFamily = CHIP_FAMILY_M9;
+ info->ChipFamily = CHIP_FAMILY_RV250;
+ break;
+
+ case PCI_CHIP_RS300_5835:
+ info->IsMobility = TRUE;
+ case PCI_CHIP_RS300_5834:
+ info->ChipFamily = CHIP_FAMILY_RS300;
+ info->IsIGP = TRUE;
break;
case PCI_CHIP_RV280_5C61:
@@ -2008,7 +2028,7 @@
case PCI_CHIP_RV280_596A:
case PCI_CHIP_RV280_596B:
info->IsMobility = TRUE;
- info->ChipFamily = CHIP_FAMILY_M9PLUS;
+ info->ChipFamily = CHIP_FAMILY_RV280;
break;
case PCI_CHIP_R300_AD:
@@ -2022,6 +2042,19 @@
info->ChipFamily = CHIP_FAMILY_R300;
break;
+ case PCI_CHIP_RV350_NP:
+ info->IsMobility = TRUE;
+ case PCI_CHIP_RV350_AP:
+ case PCI_CHIP_RV350_AR:
+ info->ChipFamily = CHIP_FAMILY_RV350;
+ break;
+
+ case PCI_CHIP_R350_AK:
+ case PCI_CHIP_R350_NH:
+ case PCI_CHIP_R350_NK:
+ info->ChipFamily = CHIP_FAMILY_R350;
+ break;
+
default:
/* Original Radeon/7200 */
info->ChipFamily = CHIP_FAMILY_RADEON;
@@ -2089,7 +2122,8 @@
if (info->FBDev)
pScrn->videoRam = fbdevHWGetVidmem(pScrn) / 1024;
else if ((info->ChipFamily == CHIP_FAMILY_RS100) ||
- (info->ChipFamily == CHIP_FAMILY_RS200)) {
+ (info->ChipFamily == CHIP_FAMILY_RS200) ||
+ (info->ChipFamily == CHIP_FAMILY_RS300)) {
CARD32 tom = INREG(RADEON_NB_TOM);
pScrn->videoRam = (((tom >> 16) -
(tom & 0xffff) + 1) << 6);
@@ -2102,6 +2136,16 @@
*/
OUTREG(RADEON_GRPH2_BUFFER_CNTL,
INREG(RADEON_GRPH2_BUFFER_CNTL) & ~0x7f0000);
+
+ if ((info->ChipFamily == CHIP_FAMILY_RS100) ||
+ (info->ChipFamily == CHIP_FAMILY_RS200)) {
+ /* This is to workaround the asic bug for RMX, some versions
+ of BIOS dosen't have this register initialized correctly.
+ */
+ OUTREGP(RADEON_CRTC_MORE_CNTL, RADEON_CRTC_H_CUTOFF_ACTIVE_EN,
+ ~RADEON_CRTC_H_CUTOFF_ACTIVE_EN);
+ }
+
}
else
pScrn->videoRam = INREG(RADEON_CONFIG_MEMSIZE) / 1024;
@@ -4177,12 +4221,15 @@
info->CurrentLayout.pixel_bytes * 3 + 1023) / 1024);
info->directRenderingEnabled = FALSE;
} else if ((info->ChipFamily == CHIP_FAMILY_RS100) ||
- (info->ChipFamily == CHIP_FAMILY_RS200)) {
+ (info->ChipFamily == CHIP_FAMILY_RS200) ||
+ (info->ChipFamily == CHIP_FAMILY_RS300)) {
info->directRenderingEnabled = FALSE;
xf86DrvMsg(scrnIndex, X_WARNING,
"Direct rendering not yet supported on "
- "IGP320/330/340/350 integrated chips\n");
- } else if (info->ChipFamily >= CHIP_FAMILY_R300) {
+ "IGP320/330/340/350, 7000, 9000 integrated chips\n");
+ } else if ((info->ChipFamily == CHIP_FAMILY_R300) ||
+ (info->ChipFamily == CHIP_FAMILY_R350) ||
+ (info->ChipFamily == CHIP_FAMILY_RV350)) {
info->directRenderingEnabled = FALSE;
xf86DrvMsg(scrnIndex, X_WARNING,
"Direct rendering not yet supported on "
@@ -4660,7 +4707,9 @@
if (info->HasCRTC2 &&
!info->IsSwitching &&
info->ChipFamily != CHIP_FAMILY_R200 &&
- info->ChipFamily != CHIP_FAMILY_R300) {
+ info->ChipFamily != CHIP_FAMILY_R300 &&
+ info->ChipFamily != CHIP_FAMILY_R350 &&
+ info->ChipFamily != CHIP_FAMILY_RV350) {
CARD32 tmp;
RADEONEntPtr pRADEONEnt = RADEONEntPriv(pScrn);
@@ -4724,6 +4773,7 @@
OUTREG(RADEON_CRTC_OFFSET, restore->crtc_offset);
OUTREG(RADEON_CRTC_OFFSET_CNTL, restore->crtc_offset_cntl);
OUTREG(RADEON_CRTC_PITCH, restore->crtc_pitch);
+ OUTREG(RADEON_DISP_MERGE_CNTL, restore->disp_merge_cntl);
}
/* Write CRTC2 registers */
@@ -4741,8 +4791,10 @@
OUTREG(RADEON_DAC_CNTL2, restore->dac2_cntl);
- if (info->ChipFamily == CHIP_FAMILY_R200 ||
- info->ChipFamily == CHIP_FAMILY_R300) {
+ if ((info->ChipFamily == CHIP_FAMILY_R200) ||
+ (info->ChipFamily == CHIP_FAMILY_R300) ||
+ (info->ChipFamily == CHIP_FAMILY_R350) ||
+ (info->ChipFamily == CHIP_FAMILY_RV350)) {
OUTREG(RADEON_DISP_OUTPUT_CNTL, restore->disp_output_cntl);
} else {
OUTREG(RADEON_DISP_HW_DEBUG, restore->disp_hw_debug);
@@ -4756,6 +4808,7 @@
OUTREG(RADEON_CRTC2_OFFSET, restore->crtc2_offset);
OUTREG(RADEON_CRTC2_OFFSET_CNTL, restore->crtc2_offset_cntl);
OUTREG(RADEON_CRTC2_PITCH, restore->crtc2_pitch);
+ OUTREG(RADEON_DISP2_MERGE_CNTL, restore->disp2_merge_cntl);
if (info->DisplayType == MT_DFP || info->CloneType == MT_DFP) {
OUTREG(RADEON_FP_H2_SYNC_STRT_WID, restore->fp2_h_sync_strt_wid);
@@ -4794,9 +4847,18 @@
INREG(RADEON_GRPH_BUFFER_CNTL) & ~0x7f0000);
if (info->DisplayType != MT_DFP) {
-
+ unsigned long tmpPixclksCntl = INPLL(pScrn, RADEON_PIXCLKS_CNTL);
OUTREG(RADEON_BIOS_5_SCRATCH, restore->bios_5_scratch);
+ if (info->IsMobility || info->IsIGP) {
+ /* Asic bug, when turning off LVDS_ON, we have to make sure
+ RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off
+ */
+ if (!(restore->lvds_gen_cntl & RADEON_LVDS_ON)) {
+ OUTPLLP(pScrn, RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
+ }
+ }
+
tmp = INREG(RADEON_LVDS_GEN_CNTL);
if ((tmp & (RADEON_LVDS_ON | RADEON_LVDS_BLON)) ==
(restore->lvds_gen_cntl & (RADEON_LVDS_ON | RADEON_LVDS_BLON))) {
@@ -4812,6 +4874,12 @@
OUTREG(RADEON_LVDS_GEN_CNTL, restore->lvds_gen_cntl);
}
}
+
+ if (info->IsMobility || info->IsIGP) {
+ if (!(restore->lvds_gen_cntl & RADEON_LVDS_ON)) {
+ OUTPLL(RADEON_PIXCLKS_CNTL, tmpPixclksCntl);
+ }
+ }
}
}
@@ -4874,7 +4942,7 @@
RADEONInfoPtr info = RADEONPTR(pScrn);
unsigned char *RADEONMMIO = info->MMIO;
- if (info->ChipFamily < CHIP_FAMILY_R300) {
+ if (info->IsMobility) {
/* A temporal workaround for the occational blanking on certain laptop panels.
This appears to related to the PLL divider registers (fail to lock?).
It occurs even when all dividers are the same with their old settings.
@@ -4903,7 +4971,9 @@
RADEON_PLL_DIV_SEL,
~(RADEON_PLL_DIV_SEL));
- if (info->ChipFamily == CHIP_FAMILY_R300) {
+ if ((info->ChipFamily == CHIP_FAMILY_R300) ||
+ (info->ChipFamily == CHIP_FAMILY_R350) ||
+ (info->ChipFamily == CHIP_FAMILY_RV350)) {
if (restore->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
/* When restoring console mode, use saved PPLL_REF_DIV
* setting.
@@ -5178,6 +5248,7 @@
save->crtc_offset = INREG(RADEON_CRTC_OFFSET);
save->crtc_offset_cntl = INREG(RADEON_CRTC_OFFSET_CNTL);
save->crtc_pitch = INREG(RADEON_CRTC_PITCH);
+ save->disp_merge_cntl = INREG(RADEON_DISP_MERGE_CNTL);
}
/* Read flat panel registers */
@@ -5222,7 +5293,7 @@
save->fp2_h_sync_strt_wid = INREG (RADEON_FP_H2_SYNC_STRT_WID);
save->fp2_v_sync_strt_wid = INREG (RADEON_FP_V2_SYNC_STRT_WID);
save->fp2_gen_cntl = INREG (RADEON_FP2_GEN_CNTL);
-
+ save->disp2_merge_cntl = INREG(RADEON_DISP2_MERGE_CNTL);
}
/* Read PLL registers */
@@ -5293,10 +5364,7 @@
RADEONSaveCommonRegisters(pScrn, save);
RADEONSaveCrtcRegisters(pScrn, save);
- if ((info->DisplayType == MT_DFP) ||
- (info->DisplayType == MT_LCD)) {
- RADEONSaveFPRegisters(pScrn, save);
- }
+ RADEONSaveFPRegisters(pScrn, save);
if (info->Clone) {
RADEONSaveCrtc2Registers(pScrn, save);
@@ -5579,6 +5647,8 @@
save->crtc_pitch |= save->crtc_pitch << 16;
save->surface_cntl = 0;
+ save->disp_merge_cntl = info->SavedReg.disp_merge_cntl;
+ save->disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
#if X_BYTE_ORDER == X_BIG_ENDIAN
switch (pScrn->bitsPerPixel) {
@@ -5646,7 +5716,9 @@
save->crtc_ext_cntl |= RADEON_CRTC_CRT_ON;
save->dac2_cntl = info->SavedReg.dac2_cntl;
if (info->ChipFamily == CHIP_FAMILY_R200 ||
- info->ChipFamily == CHIP_FAMILY_R300) {
+ info->ChipFamily == CHIP_FAMILY_R300 ||
+ info->ChipFamily == CHIP_FAMILY_R350 ||
+ info->ChipFamily == CHIP_FAMILY_RV350) {
save->disp_output_cntl =
((info->SavedReg.disp_output_cntl
& ~(CARD32)RADEON_DISP_DAC_SOURCE_MASK)
@@ -5709,6 +5781,8 @@
((pScrn->bitsPerPixel * 8) -1)) /
(pScrn->bitsPerPixel * 8));
save->crtc2_pitch |= save->crtc2_pitch << 16;
+ save->disp2_merge_cntl = info->SavedReg.disp2_merge_cntl;
+ save->disp2_merge_cntl &= ~(RADEON_DISP2_RGB_OFFSET_EN);
if (info->DisplayType == MT_DFP || info->CloneType == MT_DFP) {
save->crtc2_gen_cntl = (RADEON_CRTC2_EN | (format << 8));
@@ -5776,14 +5850,9 @@
save->lvds_pll_cntl = orig->lvds_pll_cntl;
save->tmds_pll_cntl = orig->tmds_pll_cntl;
save->tmds_transmitter_cntl= orig->tmds_transmitter_cntl;
- /* Try to turn panel off.
- * LCD off still has some problem:
- * In principle, turning LVDS_ON off should do it. But it causes
- * blooming on some panels, not sure why. Here just a workaround
- * for blanking it, also may not work on certain panels
- */
- save->lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_DISPLAY_DIS | (1 << 23));
- save->lvds_gen_cntl &= ~(RADEON_LVDS_BLON);
+
+ save->lvds_gen_cntl |= ( RADEON_LVDS_DISPLAY_DIS | (1 << 23));
+ save->lvds_gen_cntl &= ~(RADEON_LVDS_BLON | RADEON_LVDS_ON);
save->fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
return;
@@ -5869,7 +5938,9 @@
/* This is needed for some panel at high resolution (>=1600x1200)
*/
if ((save->dot_clock_freq > 15000) &&
- (info->ChipFamily != CHIP_FAMILY_R300))
+ (info->ChipFamily != CHIP_FAMILY_R300) &&
+ (info->ChipFamily != CHIP_FAMILY_R350) &&
+ (info->ChipFamily != CHIP_FAMILY_RV350))
save->tmds_pll_cntl = 0xA3F;
else
save->tmds_pll_cntl = orig->tmds_pll_cntl;
@@ -5889,8 +5960,8 @@
/* Turning off LVDS_ON seems to make panel white blooming.
* For now we just turn off display data ???
*/
- save->lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_DISPLAY_DIS);
- save->lvds_gen_cntl &= ~(RADEON_LVDS_BLON);
+ save->lvds_gen_cntl |= (RADEON_LVDS_DISPLAY_DIS);
+ save->lvds_gen_cntl &= ~(RADEON_LVDS_BLON | RADEON_LVDS_ON);
} else if (info->DisplayType == MT_DFP)
save->fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
@@ -5912,12 +5983,18 @@
} else if (info->DisplayType == MT_DFP) {
/* This is needed for some panel at high resolution (>=1600x1200)
*/
- if ((save->dot_clock_freq > 15000) && (info->ChipFamily != CHIP_FAMILY_R300))
+ if ((save->dot_clock_freq > 15000) &&
+ (info->ChipFamily != CHIP_FAMILY_R300) &&
+ (info->ChipFamily != CHIP_FAMILY_R350) &&
+ (info->ChipFamily != CHIP_FAMILY_RV350))
save->tmds_pll_cntl = 0xA3F;
save->tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLRST);
- if ((info->ChipFamily == CHIP_FAMILY_R300) || (info->ChipFamily == CHIP_FAMILY_R200) || !info->HasCRTC2)
- save->tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN);
+ if ((info->ChipFamily == CHIP_FAMILY_R300) ||
+ (info->ChipFamily == CHIP_FAMILY_R350) ||
+ (info->ChipFamily == CHIP_FAMILY_RV350) ||
+ (info->ChipFamily == CHIP_FAMILY_R200) || !info->HasCRTC2)
+ save->tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN);
else /* weird, RV chips got this bit reversed? */
save->tmds_transmitter_cntl |= (RADEON_TMDS_TRANSMITTER_PLLEN);
@@ -6590,6 +6667,62 @@
}
break;
}
+
+ if (PowerManagementMode == DPMSModeOn) {
+ if (info->IsSecondary) {
+ if (info->DisplayType == MT_DFP) {
+ OUTREGP (RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_BLANK_EN);
+ OUTREGP (RADEON_FP2_GEN_CNTL, RADEON_FP2_ON, ~RADEON_FP2_ON);
+ }
+ } else {
+ if ((info->Clone) && (info->CloneType == MT_DFP)) {
+ OUTREGP (RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_BLANK_EN);
+ OUTREGP (RADEON_FP2_GEN_CNTL, RADEON_FP2_ON, ~RADEON_FP2_ON);
+ }
+ if (info->DisplayType == MT_DFP) {
+ OUTREGP (RADEON_FP_GEN_CNTL, (RADEON_FP_FPON | RADEON_FP_TMDS_EN),
+ ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN));
+ } else if (info->DisplayType == MT_LCD) {
+
+ OUTREGP (RADEON_LVDS_GEN_CNTL, RADEON_LVDS_BLON, ~RADEON_LVDS_BLON);
+ usleep (info->PanelPwrDly * 1000);
+ OUTREGP (RADEON_LVDS_GEN_CNTL, RADEON_LVDS_ON, ~RADEON_LVDS_ON);
+ }
+ }
+ } else if ((PowerManagementMode == DPMSModeOff) ||
+ (PowerManagementMode == DPMSModeSuspend) ||
+ (PowerManagementMode == DPMSModeStandby)) {
+ if (info->IsSecondary) {
+ if (info->DisplayType == MT_DFP) {
+ OUTREGP (RADEON_FP2_GEN_CNTL, RADEON_FP2_BLANK_EN, ~RADEON_FP2_BLANK_EN);
+ OUTREGP (RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_ON);
+ }
+ } else {
+ if ((info->Clone) && (info->CloneType == MT_DFP)) {
+ OUTREGP (RADEON_FP2_GEN_CNTL, RADEON_FP2_BLANK_EN, ~RADEON_FP2_BLANK_EN);
+ OUTREGP (RADEON_FP2_GEN_CNTL, 0, ~RADEON_FP2_ON);
+ }
+ if (info->DisplayType == MT_DFP) {
+ OUTREGP (RADEON_FP_GEN_CNTL, 0, ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN));
+ } else if (info->DisplayType == MT_LCD) {
+ unsigned long tmpPixclksCntl = INPLL(pScrn, RADEON_PIXCLKS_CNTL);
+
+ if (info->IsMobility || info->IsIGP) {
+ /* Asic bug, when turning off LVDS_ON, we have to make sure
+ RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off
+ */
+ OUTPLLP(pScrn, RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
+ }
+
+ OUTREGP (RADEON_LVDS_GEN_CNTL, 0,
+ ~(RADEON_LVDS_BLON | RADEON_LVDS_ON));
+
+ if (info->IsMobility || info->IsIGP) {
+ OUTPLL(RADEON_PIXCLKS_CNTL, tmpPixclksCntl);
+ }
+ }
+ }
+ }
}
#ifdef XF86DRI
diff -urN xc.orig/programs/Xserver/hw/xfree86/drivers/ati/radeon_probe.c xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_probe.c
--- xc.orig/programs/Xserver/hw/xfree86/drivers/ati/radeon_probe.c 2004-04-03 15:35:30.000000000 -0500
+++ xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_probe.c 2004-04-03 15:44:03.000000000 -0500
@@ -88,6 +88,8 @@
{ PCI_CHIP_RS100_4336, "ATI Radeon IGP320M (U1) 4336" },
{ PCI_CHIP_RS200_4137, "ATI Radeon IGP330/340/350 (A4) 4137" },
{ PCI_CHIP_RS200_4337, "ATI Radeon IGP330M/340M/350M (U2) 4337" },
+ { PCI_CHIP_RS250_4237, "ATI Radeon 7000 IGP (A4+) 4237" },
+ { PCI_CHIP_RS250_4437, "ATI Radeon Mobility 7000 IGP 4437" },
{ PCI_CHIP_R200_QH, "ATI FireGL 8700/8800 QH (AGP)" },
{ PCI_CHIP_R200_QI, "ATI Radeon 8500 QI (AGP)" },
{ PCI_CHIP_R200_QJ, "ATI Radeon 8500 QJ (AGP)" },
@@ -112,6 +114,8 @@
{ PCI_CHIP_RV250_Le, "ATI Radeon Mobility M9 Le (AGP)" },
{ PCI_CHIP_RV250_Lf, "ATI Radeon Mobility M9 Lf (AGP)" },
{ PCI_CHIP_RV250_Lg, "ATI Radeon Mobility M9 Lg (AGP)" },
+ { PCI_CHIP_RS300_5834, "ATI Radeon 9000 IGP (A5) 5834" },
+ { PCI_CHIP_RS300_5835, "ATI Radeon Mobility 9000 IGP (U3) 5835" },
{ PCI_CHIP_RV280_5960, "ATI Radeon 9200 5960 (AGP)" },
{ PCI_CHIP_RV280_5961, "ATI Radeon 9200 5961 (AGP)" },
{ PCI_CHIP_RV280_5962, "ATI Radeon 9200 5962 (AGP)" },
@@ -131,6 +135,12 @@
{ PCI_CHIP_R300_NE, "ATI Radeon 9700/9500Pro NE (AGP)" },
{ PCI_CHIP_R300_NF, "ATI Radeon 9700 NF (AGP)" },
{ PCI_CHIP_R300_NG, "ATI FireGL X1 NG (AGP)" },
+ { PCI_CHIP_RV350_AP, "ATI Radeon 9600 AP (AGP)" },
+ { PCI_CHIP_RV350_AR, "ATI Radeon 9600PRO AR (AGP)" },
+ { PCI_CHIP_RV350_NP, "ATI Radeon Mobility M10 NP (AGP)" },
+ { PCI_CHIP_R350_AK, "ATI FireGL (R350) AK (AGP)" },
+ { PCI_CHIP_R350_NH, "ATI Radeon 9800 NH (AGP)" },
+ { PCI_CHIP_R350_NK, "ATI FireGL (R350) NL (AGP)" },
{ -1, NULL }
};
@@ -149,6 +159,8 @@
{ PCI_CHIP_RS100_4336, PCI_CHIP_RS100_4336, RES_SHARED_VGA },
{ PCI_CHIP_RS200_4137, PCI_CHIP_RS200_4137, RES_SHARED_VGA },
{ PCI_CHIP_RS200_4337, PCI_CHIP_RS200_4337, RES_SHARED_VGA },
+ { PCI_CHIP_RS250_4237, PCI_CHIP_RS250_4237, RES_SHARED_VGA },
+ { PCI_CHIP_RS250_4437, PCI_CHIP_RS250_4437, RES_SHARED_VGA },
{ PCI_CHIP_R200_QH, PCI_CHIP_R200_QH, RES_SHARED_VGA },
{ PCI_CHIP_R200_QI, PCI_CHIP_R200_QI, RES_SHARED_VGA },
{ PCI_CHIP_R200_QJ, PCI_CHIP_R200_QJ, RES_SHARED_VGA },
@@ -173,6 +185,8 @@
{ PCI_CHIP_RV250_Le, PCI_CHIP_RV250_Le, RES_SHARED_VGA },
{ PCI_CHIP_RV250_Lf, PCI_CHIP_RV250_Lf, RES_SHARED_VGA },
{ PCI_CHIP_RV250_Lg, PCI_CHIP_RV250_Lg, RES_SHARED_VGA },
+ { PCI_CHIP_RS300_5834, PCI_CHIP_RS300_5834, RES_SHARED_VGA },
+ { PCI_CHIP_RS300_5835, PCI_CHIP_RS300_5835, RES_SHARED_VGA },
{ PCI_CHIP_RV280_5960, PCI_CHIP_RV280_5960, RES_SHARED_VGA },
{ PCI_CHIP_RV280_5961, PCI_CHIP_RV280_5961, RES_SHARED_VGA },
{ PCI_CHIP_RV280_5962, PCI_CHIP_RV280_5962, RES_SHARED_VGA },
@@ -192,6 +206,12 @@
{ PCI_CHIP_R300_NE, PCI_CHIP_R300_NE, RES_SHARED_VGA },
{ PCI_CHIP_R300_NF, PCI_CHIP_R300_NF, RES_SHARED_VGA },
{ PCI_CHIP_R300_NG, PCI_CHIP_R300_NG, RES_SHARED_VGA },
+ { PCI_CHIP_RV350_AP, PCI_CHIP_RV350_AP, RES_SHARED_VGA },
+ { PCI_CHIP_RV350_AR, PCI_CHIP_RV350_AR, RES_SHARED_VGA },
+ { PCI_CHIP_RV350_NP, PCI_CHIP_RV350_NP, RES_SHARED_VGA },
+ { PCI_CHIP_R350_AK, PCI_CHIP_R350_AK, RES_SHARED_VGA },
+ { PCI_CHIP_R350_NH, PCI_CHIP_R350_NH, RES_SHARED_VGA },
+ { PCI_CHIP_R350_NK, PCI_CHIP_R350_NK, RES_SHARED_VGA },
{ -1, -1, RES_UNDEFINED }
};
diff -urN xc.orig/programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h
--- xc.orig/programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h 2004-04-03 15:35:29.000000000 -0500
+++ xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h 2004-04-03 15:44:03.000000000 -0500
@@ -274,6 +274,8 @@
# define RADEON_CRTC2_CSYNC_EN (1 << 27)
# define RADEON_CRTC2_HSYNC_DIS (1 << 28)
# define RADEON_CRTC2_VSYNC_DIS (1 << 29)
+#define RADEON_CRTC_MORE_CNTL 0x27c
+# define RADEON_CRTC_H_CUTOFF_ACTIVE_EN (1<<4)
#define RADEON_CRTC_GUI_TRIG_VLINE 0x0218
#define RADEON_CRTC_H_SYNC_STRT_WID 0x0204
# define RADEON_CRTC_H_SYNC_STRT_PIX (0x07 << 0)
@@ -408,9 +410,12 @@
# define RADEON_DISP_ALPHA_MODE_KEY 0
# define RADEON_DISP_ALPHA_MODE_PER_PIXEL 1
# define RADEON_DISP_ALPHA_MODE_GLOBAL 2
+# define RADEON_DISP_RGB_OFFSET_EN (1<<8)
# define RADEON_DISP_GRPH_ALPHA_MASK (0xff << 16)
# define RADEON_DISP_OV0_ALPHA_MASK (0xff << 24)
# define RADEON_DISP_LIN_TRANS_BYPASS (0x01 << 9)
+#define RADEON_DISP2_MERGE_CNTL 0x0d68
+# define RADEON_DISP2_RGB_OFFSET_EN (1<<8)
#define RADEON_DISP_LIN_TRANS_GRPH_A 0x0d80
#define RADEON_DISP_LIN_TRANS_GRPH_B 0x0d84
#define RADEON_DISP_LIN_TRANS_GRPH_C 0x0d88
diff -urN xc.orig/programs/Xserver/hw/xfree86/drivers/ati/radeon_video.c xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_video.c
--- xc.orig/programs/Xserver/hw/xfree86/drivers/ati/radeon_video.c 2004-04-03 15:35:29.000000000 -0500
+++ xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_video.c 2004-04-03 15:44:03.000000000 -0500
@@ -400,8 +400,11 @@
OUTREG(RADEON_CAP0_TRIG_CNTL, 0);
RADEONSetColorKey(pScrn, pPriv->colorKey);
- if (info->ChipFamily == CHIP_FAMILY_R200 ||
- info->ChipFamily == CHIP_FAMILY_R300) {
+ if ((info->ChipFamily == CHIP_FAMILY_R300) ||
+ (info->ChipFamily == CHIP_FAMILY_R350) ||
+ (info->ChipFamily == CHIP_FAMILY_RV350) ||
+ (info->ChipFamily == CHIP_FAMILY_R200) ||
+ (info->ChipFamily == CHIP_FAMILY_RADEON)) {
int i;
OUTREG(RADEON_OV0_LIN_TRANS_A, 0x12a20000);
@@ -484,7 +487,9 @@
OUTPLL(RADEON_VCLK_ECP_CNTL, (INPLL(pScrn, RADEON_VCLK_ECP_CNTL) &
0xfffffCff) | (pPriv->ecp_div << 8));
- if ((info->ChipFamily == CHIP_FAMILY_RS100) || (info->ChipFamily == CHIP_FAMILY_RS200)) {
+ if ((info->ChipFamily == CHIP_FAMILY_RS100) ||
+ (info->ChipFamily == CHIP_FAMILY_RS200) ||
+ (info->ChipFamily == CHIP_FAMILY_RS300)) {
/* Force the overlay clock on for integrated chips
*/
OUTPLL(RADEON_VCLK_ECP_CNTL, (INPLL(pScrn, RADEON_VCLK_ECP_CNTL) | (1<<18)));
@@ -1048,8 +1053,11 @@
if (pScrn->currentMode->Flags & V_DBLSCAN)
y_mult = 2;
x_off = 8;
- if (info->ChipFamily == CHIP_FAMILY_R200 ||
- info->ChipFamily == CHIP_FAMILY_R300)
+
+ if ((info->ChipFamily == CHIP_FAMILY_R300) ||
+ (info->ChipFamily == CHIP_FAMILY_R350) ||
+ (info->ChipFamily == CHIP_FAMILY_RV350) ||
+ (info->ChipFamily == CHIP_FAMILY_R200))
x_off = 0;
/* Put the hardware overlay on CRTC2:
