Timo Aaltonen pushed to branch debian-unstable at X Strike Force / lib / mesa
Commits:
c4e497df by Timo Aaltonen at 2023-12-23T12:08:04+02:00
patches: Fix a regression in crocus. (Closes: #1059015)
- - - - -
6f7cc7a1 by Timo Aaltonen at 2023-12-23T12:08:16+02:00
release to sid
- - - - -
3 changed files:
- debian/changelog
- +
debian/patches/0001-intel-compiler-move-gen5-final-pass-to-actually-be-f.patch
- debian/patches/series
Changes:
=====================================
debian/changelog
=====================================
@@ -1,3 +1,9 @@
+mesa (23.3.1-4) unstable; urgency=medium
+
+ * patches: Fix a regression in crocus. (Closes: #1059015)
+
+ -- Timo Aaltonen <tjaal...@debian.org> Sat, 23 Dec 2023 12:08:05 +0200
+
mesa (23.3.1-3) unstable; urgency=medium
* llvmpipe-add-orcjit.diff: Fix to actually build with llvm-17.
=====================================
debian/patches/0001-intel-compiler-move-gen5-final-pass-to-actually-be-f.patch
=====================================
@@ -0,0 +1,56 @@
+From 5ea94d17248a91e3598306ada8085a7c144adb15 Mon Sep 17 00:00:00 2001
+From: Dave Airlie <airl...@redhat.com>
+Date: Mon, 18 Dec 2023 16:47:56 +1000
+Subject: [PATCH] intel/compiler: move gen5 final pass to actually be final
+ pass
+
+This got broken by the register conversion, this pass needs to be
+after all the others.
+
+Fixes: ce75c3c3fea9 ("intel: Switch to intrinsic-based registers")
+Reviewed-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
+Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26731>
+(cherry picked from commit f76f4be301ef311e6be21486b6a3f5fd5e90240f)
+---
+ .pick_status.json | 2 +-
+ src/intel/compiler/brw_nir.c | 17 +++++++++--------
+ 2 files changed, 10 insertions(+), 9 deletions(-)
+
+diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c
+index 8da98b0fbfd..c36269fd015 100644
+--- a/src/intel/compiler/brw_nir.c
++++ b/src/intel/compiler/brw_nir.c
+@@ -1753,14 +1753,6 @@ brw_postprocess_nir(nir_shader *nir, const struct
brw_compiler *compiler,
+ if (OPT(nir_opt_rematerialize_compares))
+ OPT(nir_opt_dce);
+
+- /* This is the last pass we run before we start emitting stuff. It
+- * determines when we need to insert boolean resolves on Gen <= 5. We
+- * run it last because it stashes data in instr->pass_flags and we don't
+- * want that to be squashed by other NIR passes.
+- */
+- if (devinfo->ver <= 5)
+- brw_nir_analyze_boolean_resolves(nir);
+-
+ OPT(nir_opt_dce);
+
+ /* The mesh stages require this pass to be called at the last minute,
+@@ -1773,6 +1765,15 @@ brw_postprocess_nir(nir_shader *nir, const struct
brw_compiler *compiler,
+ brw_nir_adjust_payload(nir, compiler);
+
+ nir_trivialize_registers(nir);
++
++ /* This is the last pass we run before we start emitting stuff. It
++ * determines when we need to insert boolean resolves on Gen <= 5. We
++ * run it last because it stashes data in instr->pass_flags and we don't
++ * want that to be squashed by other NIR passes.
++ */
++ if (devinfo->ver <= 5)
++ brw_nir_analyze_boolean_resolves(nir);
++
+ nir_sweep(nir);
+
+ if (unlikely(debug_enabled)) {
+--
+2.40.1
+
=====================================
debian/patches/series
=====================================
@@ -4,3 +4,4 @@ src_glx_dri_common.h.diff
0001-Revert-egl-add-automatic-zink-fallback-loading-betwe.patch
0002-Revert-glx-add-automatic-zink-fallback-loading-betwe.patch
llvmpipe-add-orcjit.diff
+0001-intel-compiler-move-gen5-final-pass-to-actually-be-f.patch
View it on GitLab:
https://salsa.debian.org/xorg-team/lib/mesa/-/compare/4e2fcb0907005f3b88cb7b312ad897e8f334b721...6f7cc7a13b14f4cc79ce71ae902d89214a0852b5
--
View it on GitLab:
https://salsa.debian.org/xorg-team/lib/mesa/-/compare/4e2fcb0907005f3b88cb7b312ad897e8f334b721...6f7cc7a13b14f4cc79ce71ae902d89214a0852b5
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