Tag 'mesa-17.3.0-rc5-1' created by Andreas Boll <andreas.boll....@gmail.com> at
2017-11-21 10:47 +0000
Tagging upload of mesa 17.3.0~rc5-1 to experimental.
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Changes since mesa-17.3.0-rc3-1:
Adam Jackson (2):
glx/drisw: Fix glXMakeCurrent(dpy, None, ctx)
glx/dri3: Fix passing renderType into glXCreateContext
Alex Smith (2):
spirv: Use correct type for sampled images
nir/spirv: tg4 requires a sampler
Andreas Boll (12):
broadcom/vc5: Add vc5_drm.h to the release tarball
broadcom/vc5: Remove unused v3d_compiler.c
glsl: Fix typo fragement -> fragment
Close bug #881374
Merge tag 'mesa-17.2.5' into debian-unstable
Bump changelog
Upload to unstable.
Merge tag 'mesa-17.2.5' into debian-experimental
Merge branch 'debian-unstable' into debian-experimental
Merge tag 'mesa-17.3.0-rc5' into debian-experimental
Bump changelog
Upload to experimental.
Andres Gomez (9):
docs: add sha256 checksums for 17.2.4
cherry-ignore: radv: copy indirect lowering settings from radeonsi
cherry-ignore: i965: fix blorp stage_prog_data->param leak
cherry-ignore: etnaviv: don't do resolve-in-place without valid TS
cherry-ignore: intel/fs: Alloc pull constants off mem_ctx
cherry-ignore: added 17.3 nominations.
cherry-ignore: automake: include git_sha1.h.in in release tarball
Update version to 17.2.5
docs: add release notes for 17.2.5
Anuj Phogat (2):
i965: Program DWord Length in MI_FLUSH_DW
i965/gen8+: Fix the number of dwords programmed in MI_FLUSH_DW
Bas Nieuwenhuizen (5):
radv: Don't expose heaps with 0 memory.
radv: Don't use vgpr indexing for outputs on GFX9.
radv: Disallow indirect outputs for GS on GFX9 as well.
radv: Free syncobj with multiple imports.
radv: Free temporary syncobj after waiting on it.
Dave Airlie (7):
i915g: make gears run again.
radv: free attachments on end command buffer.
radv: add initial copy descriptor support. (v2)
radv: free attachments on end command buffer.
radv: add initial copy descriptor support. (v2)
r600/shader: reserve first register of vertex shader.
r600: fix isoline tess factor component swapping.
Derek Foreman (1):
egl/wayland: Add a fallback when fourcc query isn't supported
Dylan Baker (1):
autotools: Set C++ visibility flags on Intel
Emil Velikov (7):
targets/opencl: don't hardcode the icd file install to /etc/...
automake: intel: correctly append to the LIBADD variable
configure.ac: loosen --enable-glvnd check to honour egl
configure.ac: require xcb* for the omx/va/... when using x11 platform
Update version to 17.3.0-rc4
meson: explicitly disable the build system for 17.3.x
Update version to 17.3.0-rc5
Emilio Pozuelo Monfort (1):
Make mesa-va-drivers enhance libva2
Eric Engestrom (1):
vc4: fix release build
Gert Wollny (1):
r600/sb: bail out if prepare_alu_group() doesn't find a proper scheduling
Jason Ekstrand (26):
spirv: Claim support for the simple memory model
i965/blorp: Use blorp_to_isl_format for src_isl_format in blit_miptrees
i965/blorp: Use more temporary isl_format variables
i965/miptree: Take an isl_format in render_aux_usage
intel/fs: Use a pure vertical stride for large register strides
intel/fs: Pass builders instead of blocks into emit_[un]zip
intel/fs: Be more explicit about our placement of [un]zip
intel/fs: Use ANY/ALL32 predicates in SIMD32
intel/fs: Don't stomp f0.1 in SIMD16 ballot
intel/fs: Use an explicit D type for vote any/all/eq intrinsics
intel/fs: Use a pair of 1-wide MOVs instead of SEL for any/all
intel/eu/reg: Add a subscript() helper
intel/fs: Fix MOV_INDIRECT for 64-bit values on little-core
intel/fs: Fix integer multiplication lowering for src/dst hazards
intel/fs: Mark 64-bit values as being contiguous
intel/fs: Rework zero-length URB write handling
intel/nir: Add a helper for getting the NoIndirect mask
intel/nir: Break the linking code into a helper in brw_nir.c
intel/nir: Use the correct indirect lowering masks in link_shaders
intel/blorp: Use mocs.tex for depth stencil
anv/blorp: Add a device parameter to blorp_surf_for_anv_image
intel/blorp: Make the MOCS setting part of blorp_address
i965: Use PTE MOCS for all external buffers
i965: Add stencil buffers to cache set regardless of stencil texturing
anv/cmd_buffer: Advance the address when initializing clear colors
anv/cmd_buffer: Take bo_offset into account in fast clear state addresses
Juan A. Suarez Romero (2):
glsl: add varying resources for arrays of complex types
automake: include git_sha1.h.in in release tarball
Kenneth Graunke (7):
mesa: Accept GL_BACK in get_fb0_attachment with ARB_ES3_1_compatibility.
i965: properly initialize brw->cs.base.stage to MESA_SHADER_COMPUTE
i965: Make L3 configuration atom listen for TCS/TES program updates.
i965: Implement another VF cache invalidate workaround on Gen8+.
i965: Upload invariant state once at the start of the batch on Gen4-5.
intel/tools: Fix detection of enabled shader stages.
i965: Revert Gen8 aspect of VF PIPE_CONTROL workaround.
Leo Liu (1):
radeon/video: add gfx9 offsets when rejoin the video surface
Marek Olšák (2):
st/dri: don't expose modifiers in EGL if the driver doesn't implement them
ac/surface/gfx9: don't allow DCC for the smallest mipmap levels
Matt Turner (4):
nir: Don't print swizzles when there are more than 4 components
i965/fs: Fix extract_i8/u8 to a 64-bit destination
i965/fs: Split all 32->64-bit MOVs on CHV, BXT, GLK
Revert "intel/fs: Use a pure vertical stride for large register strides"
Nanley Chery (1):
i965: Check CCS_E compatibility for texture view rendering
Neil Roberts (2):
nir/opt_intrinsics: Fix values for gl_SubGroupG{e,t}MaskARB
glsl: Transform fb buffers are only active if a variable uses them
Nicolai Hähnle (2):
amd/common/gfx9: workaround DCC corruption more conservatively
tgsi/exec: fix LDEXP in softpipe
Roland Scheidegger (1):
docs: Fix GL_MESA_program_debug enums
Tapani Pälli (1):
i965: unref push_const_bo in intelDestroyContext
Thomas Hellstrom (1):
loader/dri3: Improve dri3 thread-safety
Tim Rowley (2):
swr/rast: Use gather instruction for i32gather_ps on simd16/avx512
swr/rast: Faster emulated simd16 permute
Timo Aaltonen (1):
libglx-mesa0.links.in: Add libGLX_indirect.so.0 to link against
libGLX_mesa so that GLX with a remote xserver works. (Closes: #881789)
Timothy Arceri (5):
radv: copy indirect lowering settings from radeonsi
glsl: drop cache_fallback
glsl: use the correct parent when allocating program data members
mesa: rework how we free gl_shader_program_data
i965: disable NIR linking on HSW and below
Tomasz Figa (2):
glsl: Allow precision mismatch on dead data with GLSL ES 1.00
glsl: Allow precision mismatch on dead data with GLSL ES 1.00
Topi Pohjolainen (1):
intel/compiler/gen9: Pixel shader header only workaround
---
VERSION | 2
configure.ac | 16
debian/changelog | 20 +
debian/control | 2
debian/libglx-mesa0.links.in | 1
docs/specs/enums.txt | 26 -
meson.build | 2
src/Makefile.am | 2
src/amd/vulkan/radv_cmd_buffer.c | 2
src/amd/vulkan/radv_descriptor_set.c | 55 +++
src/amd/vulkan/radv_device.c | 32 +
src/broadcom/compiler/v3d_compiler.c | 43 --
src/compiler/glsl/ast_to_hir.cpp | 2
src/compiler/glsl/link_atomics.cpp | 4
src/compiler/glsl/link_uniforms.cpp | 17 -
src/compiler/glsl/link_varyings.cpp | 24 -
src/compiler/glsl/linker.cpp | 168
++++++----
src/compiler/glsl/shader_cache.cpp | 6
src/compiler/nir/nir.h | 1
src/compiler/nir/nir_print.c | 2
src/compiler/spirv/spirv_to_nir.c | 12
src/compiler/spirv/vtn_private.h | 1
src/compiler/spirv/vtn_variables.c | 1
src/egl/drivers/dri2/platform_wayland.c | 32 +
src/gallium/auxiliary/tgsi/tgsi_exec.c | 2
src/gallium/drivers/r600/r600_shader.c | 13
src/gallium/drivers/swr/rasterizer/common/simdlib_512_avx512.inl | 12
src/gallium/drivers/swr/rasterizer/common/simdlib_512_emu.inl | 34 --
src/gallium/drivers/vc5/Makefile.sources | 1
src/gallium/targets/opencl/Makefile.am | 2
src/glx/dri3_glx.c | 3
src/glx/drisw_glx.c | 6
src/intel/Makefile.am | 3
src/intel/Makefile.common.am | 2
src/intel/blorp/blorp.h | 7
src/intel/blorp/blorp_genX_exec.h | 20 -
src/intel/compiler/brw_fs.cpp | 94 +++--
src/intel/compiler/brw_fs_generator.cpp | 75 ++--
src/intel/compiler/brw_fs_nir.cpp | 128 ++++++-
src/intel/compiler/brw_fs_visitor.cpp | 60 +--
src/intel/compiler/brw_nir.c | 63 ++-
src/intel/compiler/brw_nir.h | 4
src/intel/compiler/brw_reg.h | 16
src/intel/tools/aubinator_error_decode.c | 2
src/intel/vulkan/anv_blorp.c | 68 ++--
src/intel/vulkan/genX_blorp_exec.c | 1
src/intel/vulkan/genX_cmd_buffer.c | 11
src/loader/loader_dri3_helper.c | 77 +++-
src/loader/loader_dri3_helper.h | 10
src/mesa/drivers/dri/i965/brw_blorp.c | 32 +
src/mesa/drivers/dri/i965/brw_context.c | 1
src/mesa/drivers/dri/i965/brw_defines.h | 2
src/mesa/drivers/dri/i965/brw_draw.c | 4
src/mesa/drivers/dri/i965/brw_link.cpp | 43 --
src/mesa/drivers/dri/i965/brw_misc_state.c | 9
src/mesa/drivers/dri/i965/brw_pipe_control.c | 52 ++-
src/mesa/drivers/dri/i965/brw_state.h | 1
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 21 -
src/mesa/drivers/dri/i965/gen7_l3_state.c | 2
src/mesa/drivers/dri/i965/genX_blorp_exec.c | 10
src/mesa/drivers/dri/i965/genX_state_upload.c | 2
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 4
src/mesa/drivers/dri/i965/intel_blit.c | 15
src/mesa/main/mtypes.h | 7
src/mesa/main/shaderobj.c | 60 ---
src/mesa/main/shaderobj.h | 3
src/mesa/program/ir_to_mesa.cpp | 2
67 files changed, 895 insertions(+), 562 deletions(-)
---
