Android.common.mk | 2
amdgpu/Android.mk | 2
amdgpu/amdgpu-symbol-check | 4
amdgpu/amdgpu.h | 64 ++++++++++
amdgpu/amdgpu_asic_id.c | 15 +-
amdgpu/amdgpu_cs.c | 54 ++++++++
amdgpu/amdgpu_device.c | 19 ++-
configure.ac | 2
data/Android.mk | 3
debian/changelog | 6
etnaviv/etnaviv_bo.c | 5
freedreno/kgsl/kgsl_ringbuffer.c | 2
include/drm/amdgpu_drm.h | 21 +++
include/drm/drm.h | 22 +++
include/drm/drm_mode.h | 47 +++++++
intel/intel_chipset.h | 4
tests/amdgpu/Makefile.am | 7 -
tests/amdgpu/amdgpu_test.c | 6
tests/amdgpu/amdgpu_test.h | 15 ++
tests/amdgpu/basic_tests.c | 8 +
tests/amdgpu/deadlock_tests.c | 245 +++++++++++++++++++++++++++++++++++++++
tests/amdgpu/uvd_enc_tests.c | 31 +++-
tests/amdgpu/uve_ib.h | 4
xf86drm.c | 22 +++
xf86drm.h | 3
25 files changed, 586 insertions(+), 27 deletions(-)
New commits:
commit 6bfd418587781ed6b1bc297985cb2736ca5a015b
Author: Timo Aaltonen <tjaal...@debian.org>
Date: Fri Oct 13 09:04:28 2017 +0300
release to unstable
diff --git a/debian/changelog b/debian/changelog
index 7eacdd0..ce8d938 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,8 +1,8 @@
-libdrm (2.4.84-1) UNRELEASED; urgency=medium
+libdrm (2.4.84-1) unstable; urgency=medium
* New upstream release.
- -- Timo Aaltonen <tjaal...@debian.org> Fri, 13 Oct 2017 08:59:10 +0300
+ -- Timo Aaltonen <tjaal...@debian.org> Fri, 13 Oct 2017 09:04:18 +0300
libdrm (2.4.83-1) unstable; urgency=medium
commit d88127af6625adcdf2717fc5472b9b7465bcdb14
Author: Timo Aaltonen <tjaal...@debian.org>
Date: Fri Oct 13 09:04:15 2017 +0300
update the changelog
diff --git a/debian/changelog b/debian/changelog
index 5e18d58..7eacdd0 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,3 +1,9 @@
+libdrm (2.4.84-1) UNRELEASED; urgency=medium
+
+ * New upstream release.
+
+ -- Timo Aaltonen <tjaal...@debian.org> Fri, 13 Oct 2017 08:59:10 +0300
+
libdrm (2.4.83-1) unstable; urgency=medium
* New upstream release.
commit 290d29d9794813a2fe0578dbb905ad09bc810516
Author: Marek Olšák <marek.ol...@amd.com>
Date: Thu Oct 12 20:48:54 2017 +0200
configure.ac: bump version to 2.4.84
diff --git a/configure.ac b/configure.ac
index f847a66..ccb910a 100644
--- a/configure.ac
+++ b/configure.ac
@@ -20,7 +20,7 @@
AC_PREREQ([2.63])
AC_INIT([libdrm],
- [2.4.83],
+ [2.4.84],
[https://bugs.freedesktop.org/enter_bug.cgi?product=DRI],
[libdrm])
commit c74d4614048f65b412caa572c900d15adba38ce3
Author: Marek Olšák <marek.ol...@amd.com>
Date: Fri Sep 8 16:05:54 2017 +0200
amdgpu: add amdgpu_cs_fence_to_handle
v2: update amdgpu-symbol-check
Reviewed-by: Chunming Zhou <david1.z...@amd.com>
diff --git a/amdgpu/amdgpu-symbol-check b/amdgpu/amdgpu-symbol-check
index 7ecfc98..d9f89ef 100755
--- a/amdgpu/amdgpu-symbol-check
+++ b/amdgpu/amdgpu-symbol-check
@@ -34,6 +34,7 @@ amdgpu_cs_ctx_free
amdgpu_cs_destroy_semaphore
amdgpu_cs_destroy_syncobj
amdgpu_cs_export_syncobj
+amdgpu_cs_fence_to_handle
amdgpu_cs_import_syncobj
amdgpu_cs_query_fence_status
amdgpu_cs_query_reset_state
diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h
index 979acfc..23cde10 100644
--- a/amdgpu/amdgpu.h
+++ b/amdgpu/amdgpu.h
@@ -1433,6 +1433,20 @@ int
amdgpu_cs_syncobj_import_sync_file(amdgpu_device_handle dev,
int sync_file_fd);
/**
+ * Export an amdgpu fence as a handle (syncobj or fd).
+ *
+ * \param what AMDGPU_FENCE_TO_HANDLE_GET_{SYNCOBJ, FD}
+ * \param out_handle returned handle
+ *
+ * \return 0 on success\n
+ * <0 - Negative POSIX Error code
+ */
+int amdgpu_cs_fence_to_handle(amdgpu_device_handle dev,
+ struct amdgpu_cs_fence *fence,
+ uint32_t what,
+ uint32_t *out_handle);
+
+/**
* Submit raw command submission to kernel
*
* \param dev - \c [in] device handle
diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c
index 2cde7bf..9577d5c 100644
--- a/amdgpu/amdgpu_cs.c
+++ b/amdgpu/amdgpu_cs.c
@@ -713,3 +713,25 @@ void amdgpu_cs_chunk_fence_to_dep(struct amdgpu_cs_fence
*fence,
dep->ctx_id = fence->context->id;
dep->handle = fence->fence;
}
+
+int amdgpu_cs_fence_to_handle(amdgpu_device_handle dev,
+ struct amdgpu_cs_fence *fence,
+ uint32_t what,
+ uint32_t *out_handle)
+{
+ union drm_amdgpu_fence_to_handle fth = {0};
+ int r;
+
+ fth.in.fence.ctx_id = fence->context->id;
+ fth.in.fence.ip_type = fence->ip_type;
+ fth.in.fence.ip_instance = fence->ip_instance;
+ fth.in.fence.ring = fence->ring;
+ fth.in.fence.seq_no = fence->fence;
+ fth.in.what = what;
+
+ r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_FENCE_TO_HANDLE,
+ &fth, sizeof(fth));
+ if (r == 0)
+ *out_handle = fth.out.handle;
+ return r;
+}
commit 59aa57b363ba8de550aced1d397c54fd9e5e213c
Author: Marek Olšák <marek.ol...@amd.com>
Date: Mon Sep 11 21:58:03 2017 +0200
amdgpu: add amdgpu_cs_syncobj_wait
v2: update amdgpu-symbol-check
Reviewed-by: Chunming Zhou <david1.z...@amd.com>
diff --git a/amdgpu/amdgpu-symbol-check b/amdgpu/amdgpu-symbol-check
index bc9ed3f..7ecfc98 100755
--- a/amdgpu/amdgpu-symbol-check
+++ b/amdgpu/amdgpu-symbol-check
@@ -42,6 +42,7 @@ amdgpu_cs_submit
amdgpu_cs_submit_raw
amdgpu_cs_syncobj_export_sync_file
amdgpu_cs_syncobj_import_sync_file
+amdgpu_cs_syncobj_wait
amdgpu_cs_wait_fences
amdgpu_cs_wait_semaphore
amdgpu_device_deinitialize
diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h
index b44b9b6..979acfc 100644
--- a/amdgpu/amdgpu.h
+++ b/amdgpu/amdgpu.h
@@ -1354,6 +1354,26 @@ int amdgpu_cs_destroy_syncobj(amdgpu_device_handle dev,
uint32_t syncobj);
/**
+ * Wait for one or all sync objects to signal.
+ *
+ * \param dev - \c [in] self-explanatory
+ * \param handles - \c [in] array of sync object handles
+ * \param num_handles - \c [in] self-explanatory
+ * \param timeout_nsec - \c [in] self-explanatory
+ * \param flags - \c [in] a bitmask of DRM_SYNCOBJ_WAIT_FLAGS_*
+ * \param first_signaled - \c [in] self-explanatory
+ *
+ * \return 0 on success\n
+ * -ETIME - Timeout
+ * <0 - Negative POSIX Error code
+ *
+ */
+int amdgpu_cs_syncobj_wait(amdgpu_device_handle dev,
+ uint32_t *handles, unsigned num_handles,
+ int64_t timeout_nsec, unsigned flags,
+ uint32_t *first_signaled);
+
+/**
* Export kernel sync object to shareable fd.
*
* \param dev - \c [in] device handle
diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c
index 4a05536..2cde7bf 100644
--- a/amdgpu/amdgpu_cs.c
+++ b/amdgpu/amdgpu_cs.c
@@ -615,6 +615,18 @@ int amdgpu_cs_destroy_syncobj(amdgpu_device_handle dev,
return drmSyncobjDestroy(dev->fd, handle);
}
+int amdgpu_cs_syncobj_wait(amdgpu_device_handle dev,
+ uint32_t *handles, unsigned num_handles,
+ int64_t timeout_nsec, unsigned flags,
+ uint32_t *first_signaled)
+{
+ if (NULL == dev)
+ return -EINVAL;
+
+ return drmSyncobjWait(dev->fd, handles, num_handles, timeout_nsec,
+ flags, first_signaled);
+}
+
int amdgpu_cs_export_syncobj(amdgpu_device_handle dev,
uint32_t handle,
int *shared_fd)
commit 2048a9e7278d64954080077fb29d603fbb611873
Author: Marek Olšák <marek.ol...@amd.com>
Date: Mon Sep 11 21:57:32 2017 +0200
drm: add drmSyncobjWait wrapper
Reviewed-by: Chunming Zhou <david1.z...@amd.com>
diff --git a/xf86drm.c b/xf86drm.c
index 6ea0112..8a32717 100644
--- a/xf86drm.c
+++ b/xf86drm.c
@@ -4225,3 +4225,25 @@ int drmSyncobjExportSyncFile(int fd, uint32_t handle,
int *sync_file_fd)
*sync_file_fd = args.fd;
return 0;
}
+
+int drmSyncobjWait(int fd, uint32_t *handles, unsigned num_handles,
+ int64_t timeout_nsec, unsigned flags,
+ uint32_t *first_signaled)
+{
+ struct drm_syncobj_wait args;
+ int ret;
+
+ memclear(args);
+ args.handles = (intptr_t)handles;
+ args.timeout_nsec = timeout_nsec;
+ args.count_handles = num_handles;
+ args.flags = flags;
+
+ ret = drmIoctl(fd, DRM_IOCTL_SYNCOBJ_WAIT, &args);
+ if (ret < 0)
+ return ret;
+
+ if (first_signaled)
+ *first_signaled = args.first_signaled;
+ return ret;
+}
diff --git a/xf86drm.h b/xf86drm.h
index 2855a3e..ea650ef 100644
--- a/xf86drm.h
+++ b/xf86drm.h
@@ -860,6 +860,9 @@ extern int drmSyncobjFDToHandle(int fd, int obj_fd,
uint32_t *handle);
extern int drmSyncobjImportSyncFile(int fd, uint32_t handle, int sync_file_fd);
extern int drmSyncobjExportSyncFile(int fd, uint32_t handle, int
*sync_file_fd);
+extern int drmSyncobjWait(int fd, uint32_t *handles, unsigned num_handles,
+ int64_t timeout_nsec, unsigned flags,
+ uint32_t *first_signaled);
#if defined(__cplusplus)
}
commit b6e24501a1f8c58501fdfa39b435e440ee667feb
Author: Marek Olšák <marek.ol...@amd.com>
Date: Mon Sep 11 21:12:12 2017 +0200
amdgpu: add sync_file import and export functions
v2: update amdgpu-symbol-check
Reviewed-by: Chunming Zhou <david1.z...@amd.com>
diff --git a/amdgpu/amdgpu-symbol-check b/amdgpu/amdgpu-symbol-check
index c5b85b5..bc9ed3f 100755
--- a/amdgpu/amdgpu-symbol-check
+++ b/amdgpu/amdgpu-symbol-check
@@ -40,6 +40,8 @@ amdgpu_cs_query_reset_state
amdgpu_cs_signal_semaphore
amdgpu_cs_submit
amdgpu_cs_submit_raw
+amdgpu_cs_syncobj_export_sync_file
+amdgpu_cs_syncobj_import_sync_file
amdgpu_cs_wait_fences
amdgpu_cs_wait_semaphore
amdgpu_device_deinitialize
diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h
index 238b1aa..b44b9b6 100644
--- a/amdgpu/amdgpu.h
+++ b/amdgpu/amdgpu.h
@@ -1383,6 +1383,36 @@ int amdgpu_cs_import_syncobj(amdgpu_device_handle dev,
uint32_t *syncobj);
/**
+ * Export kernel sync object to a sync_file.
+ *
+ * \param dev - \c [in] device handle
+ * \param syncobj - \c [in] sync object handle
+ * \param sync_file_fd - \c [out] sync_file file descriptor.
+ *
+ * \return 0 on success\n
+ * <0 - Negative POSIX Error code
+ *
+ */
+int amdgpu_cs_syncobj_export_sync_file(amdgpu_device_handle dev,
+ uint32_t syncobj,
+ int *sync_file_fd);
+
+/**
+ * Import kernel sync object from a sync_file.
+ *
+ * \param dev - \c [in] device handle
+ * \param syncobj - \c [in] sync object handle
+ * \param sync_file_fd - \c [in] sync_file file descriptor.
+ *
+ * \return 0 on success\n
+ * <0 - Negative POSIX Error code
+ *
+ */
+int amdgpu_cs_syncobj_import_sync_file(amdgpu_device_handle dev,
+ uint32_t syncobj,
+ int sync_file_fd);
+
+/**
* Submit raw command submission to kernel
*
* \param dev - \c [in] device handle
diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c
index dfba875..4a05536 100644
--- a/amdgpu/amdgpu_cs.c
+++ b/amdgpu/amdgpu_cs.c
@@ -635,6 +635,26 @@ int amdgpu_cs_import_syncobj(amdgpu_device_handle dev,
return drmSyncobjFDToHandle(dev->fd, shared_fd, handle);
}
+int amdgpu_cs_syncobj_export_sync_file(amdgpu_device_handle dev,
+ uint32_t syncobj,
+ int *sync_file_fd)
+{
+ if (NULL == dev)
+ return -EINVAL;
+
+ return drmSyncobjExportSyncFile(dev->fd, syncobj, sync_file_fd);
+}
+
+int amdgpu_cs_syncobj_import_sync_file(amdgpu_device_handle dev,
+ uint32_t syncobj,
+ int sync_file_fd)
+{
+ if (NULL == dev)
+ return -EINVAL;
+
+ return drmSyncobjImportSyncFile(dev->fd, syncobj, sync_file_fd);
+}
+
int amdgpu_cs_submit_raw(amdgpu_device_handle dev,
amdgpu_context_handle context,
amdgpu_bo_list_handle bo_list_handle,
commit ad4df736a9f8098cd47008c72948ceff9e9f9dac
Author: Marek Olšák <marek.ol...@amd.com>
Date: Thu Oct 12 20:31:44 2017 +0200
include: sync drm.h and amdgpu_drm.h with airlied/drm-next
diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
index d9aa4a3..4c6e8c4 100644
--- a/include/drm/amdgpu_drm.h
+++ b/include/drm/amdgpu_drm.h
@@ -52,6 +52,7 @@ extern "C" {
#define DRM_AMDGPU_GEM_USERPTR 0x11
#define DRM_AMDGPU_WAIT_FENCES 0x12
#define DRM_AMDGPU_VM 0x13
+#define DRM_AMDGPU_FENCE_TO_HANDLE 0x14
#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE +
DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
#define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE +
DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
@@ -67,6 +68,7 @@ extern "C" {
#define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE +
DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)
#define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE +
DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences)
#define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE +
DRM_AMDGPU_VM, union drm_amdgpu_vm)
+#define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE +
DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle)
#define AMDGPU_GEM_DOMAIN_CPU 0x1
#define AMDGPU_GEM_DOMAIN_GTT 0x2
@@ -87,6 +89,8 @@ extern "C" {
#define AMDGPU_GEM_CREATE_SHADOW (1 << 4)
/* Flag that allocating the BO should use linear VRAM */
#define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5)
+/* Flag that BO is always valid in this VM */
+#define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6)
struct drm_amdgpu_gem_create_in {
/** the requested memory size */
@@ -513,6 +517,20 @@ struct drm_amdgpu_cs_chunk_sem {
__u32 handle;
};
+#define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0
+#define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1
+#define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2
+
+union drm_amdgpu_fence_to_handle {
+ struct {
+ struct drm_amdgpu_fence fence;
+ __u32 what;
+ } in;
+ struct {
+ __u32 handle;
+ } out;
+};
+
struct drm_amdgpu_cs_chunk_data {
union {
struct drm_amdgpu_cs_chunk_ib ib_data;
@@ -764,6 +782,7 @@ struct drm_amdgpu_info_device {
__u64 max_memory_clock;
/* cu information */
__u32 cu_active_number;
+ /* NOTE: cu_ao_mask is INVALID, DON'T use it */
__u32 cu_ao_mask;
__u32 cu_bitmap[4][4];
/** Render backend pipe mask. One render backend is CB+DB. */
@@ -818,6 +837,8 @@ struct drm_amdgpu_info_device {
/* max gs wavefront per vgt*/
__u32 max_gs_waves_per_vgt;
__u32 _pad1;
+ /* always on cu bitmap */
+ __u32 cu_ao_bitmap[4][4];
};
struct drm_amdgpu_info_hw_ip {
commit d27fd2d02300fdc107c9cc54d57989b8a29efd9f
Author: Dave Airlie <airl...@redhat.com>
Date: Wed Oct 11 10:41:25 2017 +1000
headers: sync syncobj ioctl defines.
This syncs the drm.h header with my drm-next branch as of
bb7a9c8d712f37385a706a594d6edf6e6d2669d0
Signed-off-by: Dave Airlie <airl...@redhat.com>
diff --git a/include/drm/drm.h b/include/drm/drm.h
index bf3674a..4737261 100644
--- a/include/drm/drm.h
+++ b/include/drm/drm.h
@@ -694,6 +694,7 @@ struct drm_prime_handle {
struct drm_syncobj_create {
__u32 handle;
+#define DRM_SYNCOBJ_CREATE_SIGNALED (1 << 0)
__u32 flags;
};
@@ -712,6 +713,24 @@ struct drm_syncobj_handle {
__u32 pad;
};
+#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL (1 << 0)
+#define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT (1 << 1)
+struct drm_syncobj_wait {
+ __u64 handles;
+ /* absolute timeout */
+ __s64 timeout_nsec;
+ __u32 count_handles;
+ __u32 flags;
+ __u32 first_signaled; /* only valid when not waiting all */
+ __u32 pad;
+};
+
+struct drm_syncobj_array {
+ __u64 handles;
+ __u32 count_handles;
+ __u32 pad;
+};
+
#if defined(__cplusplus)
}
#endif
@@ -834,6 +853,9 @@ extern "C" {
#define DRM_IOCTL_SYNCOBJ_DESTROY DRM_IOWR(0xC0, struct
drm_syncobj_destroy)
#define DRM_IOCTL_SYNCOBJ_HANDLE_TO_FD DRM_IOWR(0xC1, struct
drm_syncobj_handle)
#define DRM_IOCTL_SYNCOBJ_FD_TO_HANDLE DRM_IOWR(0xC2, struct
drm_syncobj_handle)
+#define DRM_IOCTL_SYNCOBJ_WAIT DRM_IOWR(0xC3, struct drm_syncobj_wait)
+#define DRM_IOCTL_SYNCOBJ_RESET DRM_IOWR(0xC4, struct
drm_syncobj_array)
+#define DRM_IOCTL_SYNCOBJ_SIGNAL DRM_IOWR(0xC5, struct drm_syncobj_array)
/**
* Device specific ioctls should only be in their respective headers
commit 965133914b14f571b91109814c393b62f7bc588a
Author: Rob Herring <r...@kernel.org>
Date: Fri Oct 6 16:18:57 2017 -0500
headers: sync DRM_MODE_ROTATE/REFLECT defines from kernel v4.14-rc1
Add the new DRM_MODE_ROTATE_* and DRM_MODE_REFLECT_* defines from v4.14-rc1
kernel.
Reviewed-by: Thierry Reding <tred...@nvidia.com>
Reviewed-by: Robert Foss <robert.f...@collabora.com>
Signed-off-by: Rob Herring <r...@kernel.org>
diff --git a/include/drm/drm_mode.h b/include/drm/drm_mode.h
index 0807797..e01f129 100644
--- a/include/drm/drm_mode.h
+++ b/include/drm/drm_mode.h
@@ -119,6 +119,53 @@ extern "C" {
#define DRM_MODE_LINK_STATUS_GOOD 0
#define DRM_MODE_LINK_STATUS_BAD 1
+/*
+ * DRM_MODE_ROTATE_<degrees>
+ *
+ * Signals that a drm plane is been rotated <degrees> degrees in counter
+ * clockwise direction.
+ *
+ * This define is provided as a convenience, looking up the property id
+ * using the name->prop id lookup is the preferred method.
+ */
+#define DRM_MODE_ROTATE_0 (1<<0)
+#define DRM_MODE_ROTATE_90 (1<<1)
+#define DRM_MODE_ROTATE_180 (1<<2)
+#define DRM_MODE_ROTATE_270 (1<<3)
+
+/*
+ * DRM_MODE_ROTATE_MASK
+ *
+ * Bitmask used to look for drm plane rotations.
+ */
+#define DRM_MODE_ROTATE_MASK (\
+ DRM_MODE_ROTATE_0 | \
+ DRM_MODE_ROTATE_90 | \
+ DRM_MODE_ROTATE_180 | \
+ DRM_MODE_ROTATE_270)
+
+/*
+ * DRM_MODE_REFLECT_<axis>
+ *
+ * Signals that the contents of a drm plane is reflected in the <axis> axis,
+ * in the same way as mirroring.
+ *
+ * This define is provided as a convenience, looking up the property id
+ * using the name->prop id lookup is the preferred method.
+ */
+#define DRM_MODE_REFLECT_X (1<<4)
+#define DRM_MODE_REFLECT_Y (1<<5)
+
+/*
+ * DRM_MODE_REFLECT_MASK
+ *
+ * Bitmask used to look for drm plane reflections.
+ */
+#define DRM_MODE_REFLECT_MASK (\
+ DRM_MODE_REFLECT_X | \
+ DRM_MODE_REFLECT_Y)
+
+
struct drm_mode_modeinfo {
__u32 clock;
__u16 hdisplay;
commit 011fd913b445b5e17148c37d169396c39eced3df
Author: Rob Herring <r...@kernel.org>
Date: Fri Sep 15 08:45:59 2017 -0500
Android: move libraries to /vendor
As part of Treble project in Android O, all the device specific files have
to be located in a separate vendor partition. This is done by setting
LOCAL_PROPRIETARY_MODULE (the name is misleading). This change will not
break existing platforms without a vendor partition as it will just move
files to /system/vendor.
Signed-off-by: Rob Herring <r...@kernel.org>
diff --git a/Android.common.mk b/Android.common.mk
index b45ca10..d487acb 100644
--- a/Android.common.mk
+++ b/Android.common.mk
@@ -13,3 +13,5 @@ LOCAL_CFLAGS += \
# Quiet down the build system and remove any .h files from the sources
LOCAL_SRC_FILES := $(patsubst %.h, , $(LOCAL_SRC_FILES))
LOCAL_EXPORT_C_INCLUDE_DIRS += $(LOCAL_PATH)
+
+LOCAL_PROPRIETARY_MODULE := true
diff --git a/amdgpu/Android.mk b/amdgpu/Android.mk
index 88d3765..ce27301 100644
--- a/amdgpu/Android.mk
+++ b/amdgpu/Android.mk
@@ -11,7 +11,7 @@ LOCAL_SHARED_LIBRARIES := libdrm
LOCAL_SRC_FILES := $(LIBDRM_AMDGPU_FILES)
LOCAL_CFLAGS := \
- -DAMDGPU_ASIC_ID_TABLE=\"/system/etc/hwdata/amdgpu.ids\" \
+ -DAMDGPU_ASIC_ID_TABLE=\"/vendor/etc/hwdata/amdgpu.ids\" \
-DAMDGPU_ASIC_ID_TABLE_NUM_ENTRIES=$(shell egrep -ci
'^[0-9a-f]{4},.*[0-9a-f]+,' $(LIBDRM_TOP)/data/amdgpu.ids)
LOCAL_REQUIRED_MODULES := amdgpu.ids
diff --git a/data/Android.mk b/data/Android.mk
index 3c1fd7c..62013f0 100644
--- a/data/Android.mk
+++ b/data/Android.mk
@@ -4,6 +4,7 @@ include $(CLEAR_VARS)
LOCAL_MODULE := amdgpu.ids
LOCAL_MODULE_TAGS := optional
LOCAL_MODULE_CLASS := ETC
-LOCAL_MODULE_PATH := $(TARGET_OUT_ETC)/hwdata
+LOCAL_PROPRIETARY_MODULE := true
+LOCAL_MODULE_RELATIVE_PATH := hwdata
LOCAL_SRC_FILES := $(LOCAL_MODULE)
include $(BUILD_PREBUILT)
commit 2ecafcae8a215d9994fb26a122d97bcb5437c5e8
Author: James Zhu <james....@amd.com>
Date: Thu Oct 5 10:57:42 2017 -0400
tests/amdgpu: fix uvd enc data corruption issue
In uvd encode parameter package, parameters input_pic_luma_pitch and
input_pic_chroma_pitch should be picture width align with hardware
alignment.
The hardware alignment is 16 for amdgpu family earlier than
AMDGPU_FAMILY_AI,
and 256 for later than and including AMDGPU_FAMILY_AI.
Signed-off-by: James Zhu <james....@amd.com>
Reviewed-by: Leo Liu <leo....@amd.com>
diff --git a/tests/amdgpu/uvd_enc_tests.c b/tests/amdgpu/uvd_enc_tests.c
index 7518103..bbda131 100644
--- a/tests/amdgpu/uvd_enc_tests.c
+++ b/tests/amdgpu/uvd_enc_tests.c
@@ -272,7 +272,7 @@ static void amdgpu_cs_uvd_enc_create(void)
static void check_result(struct amdgpu_uvd_enc *enc)
{
uint64_t sum;
- uint32_t s = 26382;
+ uint32_t s = 175602;
uint32_t *ptr, size;
int i, j, r;
@@ -463,6 +463,8 @@ static void amdgpu_cs_uvd_enc_encode(void)
ib_cpu[len++] = chroma_offset >> 32;
ib_cpu[len++] = chroma_offset;
memcpy((ib_cpu + len), uve_encode_param, sizeof(uve_encode_param));
+ ib_cpu[len] = ALIGN(enc.width, align);
+ ib_cpu[len + 1] = ALIGN(enc.width, align);
len += sizeof(uve_encode_param) / 4;
memcpy((ib_cpu + len), uve_op_speed_enc_mode,
sizeof(uve_op_speed_enc_mode));
diff --git a/tests/amdgpu/uve_ib.h b/tests/amdgpu/uve_ib.h
index 9abd406..cb72be2 100644
--- a/tests/amdgpu/uve_ib.h
+++ b/tests/amdgpu/uve_ib.h
@@ -297,8 +297,8 @@ static const uint32_t uve_slice_header[] = {
};
static const uint32_t uve_encode_param[] = {
- 0x000000a0,
- 0x00000080,
+ 0x00000000,
+ 0x00000000,
0x00000000,
0x00000000,
0xffffffff,
commit 657b09438bf4978c9597368165c56227013625e9
Author: James Zhu <james....@amd.com>
Date: Thu Oct 5 10:56:51 2017 -0400
tests/amdgpu: add new uvd enc support check
Query hardware IP information to find out if there are uvd encode rings
ready for use in kernel driver.
Signed-off-by: James Zhu <james....@amd.com>
Reviewed-by: Leo Liu <leo....@amd.com>
diff --git a/tests/amdgpu/uvd_enc_tests.c b/tests/amdgpu/uvd_enc_tests.c
index 6c19f7b..7518103 100644
--- a/tests/amdgpu/uvd_enc_tests.c
+++ b/tests/amdgpu/uvd_enc_tests.c
@@ -79,6 +79,8 @@ static void amdgpu_cs_uvd_enc_session_init(void);
static void amdgpu_cs_uvd_enc_encode(void);
static void amdgpu_cs_uvd_enc_destroy(void);
+static bool uvd_enc_support(void);
+
CU_TestInfo uvd_enc_tests[] = {
{ "UVD ENC create", amdgpu_cs_uvd_enc_create },
{ "UVD ENC session init", amdgpu_cs_uvd_enc_session_init },
@@ -98,7 +100,7 @@ int suite_uvd_enc_tests_init(void)
family_id = device_handle->info.family_id;
- if (family_id < AMDGPU_FAMILY_AI || family_id >= AMDGPU_FAMILY_RV) {
+ if (!uvd_enc_support()) {
printf("\n\nThe ASIC NOT support UVD ENC, all sub-tests will
pass\n");
return CUE_SUCCESS;
}
@@ -121,7 +123,7 @@ int suite_uvd_enc_tests_clean(void)
{
int r;
- if (family_id < AMDGPU_FAMILY_AI || family_id >= AMDGPU_FAMILY_RV) {
+ if (!uvd_enc_support()) {
r = amdgpu_device_deinitialize(device_handle);
if (r)
@@ -238,11 +240,24 @@ static void free_resource(struct amdgpu_uvd_enc_bo
*uvd_enc_bo)
memset(uvd_enc_bo, 0, sizeof(*uvd_enc_bo));
}
+static bool uvd_enc_support(void)
+{
+ int r;
+ struct drm_amdgpu_info_hw_ip info;
+
+ r = amdgpu_query_hw_ip_info(device_handle, AMDGPU_HW_IP_UVD_ENC, 0,
&info);
+
+ if (r)
+ return false;
+ else
+ return (info.available_rings?true:false);
+}
+
static void amdgpu_cs_uvd_enc_create(void)
{
int len, r;
- if (family_id < AMDGPU_FAMILY_AI || family_id >= AMDGPU_FAMILY_RV)
+ if (!uvd_enc_support())
return;
enc.width = 160;
@@ -281,7 +296,7 @@ static void amdgpu_cs_uvd_enc_session_init(void)
{
int len, r;
- if (family_id < AMDGPU_FAMILY_AI || family_id >= AMDGPU_FAMILY_RV)
+ if (!uvd_enc_support())
return;
len = 0;
@@ -339,7 +354,7 @@ static void amdgpu_cs_uvd_enc_encode(void)
vbuf_size = ALIGN(enc.width, align) * ALIGN(enc.height, 16) * 1.5;
cpb_size = vbuf_size * 10;
- if (family_id < AMDGPU_FAMILY_AI || family_id >= AMDGPU_FAMILY_RV)
+ if (!uvd_enc_support())
return;
num_resources = 0;
@@ -472,7 +487,7 @@ static void amdgpu_cs_uvd_enc_destroy(void)
struct amdgpu_uvd_enc_bo sw_ctx;
int len, r;
- if (family_id < AMDGPU_FAMILY_AI || family_id >= AMDGPU_FAMILY_RV)
+ if (!uvd_enc_support())
return;
num_resources = 0;
commit 670db97dc39a7879f52bad230327edf4374b7516
Author: Andrey Grodzovsky <andrey.grodzov...@amd.com>
Date: Mon Oct 2 14:07:48 2017 -0400
amdgpu: Add deadlock detection test suit.
Adding initial tests for locks detection when SW
scheduler FIFO is full.
The test works by submitting a batch of identical commands which make the CP
stall waiting for condition to become true. The condition is later satisfied
form a helper thread. Other events that happen during this time
might create deadlock situations. One such example is GPU reset
triggered by this stall when amdgpu_lockup_timeout != 0.
v2:
Increase the delay from 2 to 100 ms.
Comment out the compute test until it's working.
Typos fix.
Signed-off-by: Andrey Grodzovsky <andrey.grodzov...@amd.com>
Reviewed-by: Christian König <christian.koe...@amd.com>
diff --git a/tests/amdgpu/Makefile.am b/tests/amdgpu/Makefile.am
index 9c02fd6..8700c4d 100644
--- a/tests/amdgpu/Makefile.am
+++ b/tests/amdgpu/Makefile.am
@@ -1,7 +1,8 @@
AM_CFLAGS = \
-I $(top_srcdir)/include/drm \
-I $(top_srcdir)/amdgpu \
- -I $(top_srcdir)
+ -I $(top_srcdir) \
+ -pthread
LDADD = $(top_builddir)/libdrm.la \
$(top_builddir)/amdgpu/libdrm_amdgpu.la \
@@ -29,4 +30,5 @@ amdgpu_test_SOURCES = \
frame.h \
uvd_enc_tests.c \
vcn_tests.c \
- uve_ib.h
+ uve_ib.h \
+ deadlock_tests.c
diff --git a/tests/amdgpu/amdgpu_test.c b/tests/amdgpu/amdgpu_test.c
index cd6b826..9925503 100644
--- a/tests/amdgpu/amdgpu_test.c
+++ b/tests/amdgpu/amdgpu_test.c
@@ -97,6 +97,12 @@ static CU_SuiteInfo suites[] = {
.pCleanupFunc = suite_uvd_enc_tests_clean,
.pTests = uvd_enc_tests,
},
+ {
+ .pName = "Deadlock Tests",
+ .pInitFunc = suite_deadlock_tests_init,
+ .pCleanupFunc = suite_deadlock_tests_clean,
+ .pTests = deadlock_tests,
+ },
CU_SUITE_INFO_NULL,
};
diff --git a/tests/amdgpu/amdgpu_test.h b/tests/amdgpu/amdgpu_test.h
index d0b61ba..ece93f4 100644
--- a/tests/amdgpu/amdgpu_test.h
+++ b/tests/amdgpu/amdgpu_test.h
@@ -135,6 +135,21 @@ int suite_uvd_enc_tests_clean();
extern CU_TestInfo uvd_enc_tests[];
/**
+ * Initialize deadlock test suite
+ */
+int suite_deadlock_tests_init();
+
+/**
+ * Deinitialize deadlock test suite
+ */
+int suite_deadlock_tests_clean();
+
+/**
+ * Tests in uvd enc test suite
+ */
+extern CU_TestInfo deadlock_tests[];
+
+/**
* Helper functions
*/
static inline amdgpu_bo_handle gpu_mem_alloc(
diff --git a/tests/amdgpu/deadlock_tests.c b/tests/amdgpu/deadlock_tests.c
new file mode 100644
index 0000000..e23d903
--- /dev/null
+++ b/tests/amdgpu/deadlock_tests.c
@@ -0,0 +1,245 @@
+/*
+ * Copyright 2017 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+*/
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <unistd.h>
+#ifdef HAVE_ALLOCA_H
+# include <alloca.h>
+#endif
+
+#include "CUnit/Basic.h"
+
+#include "amdgpu_test.h"
+#include "amdgpu_drm.h"
+
+#include <pthread.h>
+
+
+/*
+ * This defines the delay in MS after which memory location designated for
+ * compression against reference value is written to, unblocking command
+ * processor
+ */
+#define WRITE_MEM_ADDRESS_DELAY_MS 100
+
+#define PACKET_TYPE3 3
+
+#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \
+ (((op) & 0xFF) << 8) | \
+ ((n) & 0x3FFF) << 16)
+
+#define PACKET3_WAIT_REG_MEM 0x3C
+#define WAIT_REG_MEM_FUNCTION(x) ((x) << 0)
+ /* 0 - always
+ * 1 - <
+ * 2 - <=
+ * 3 - ==
+ * 4 - !=
+ * 5 - >=
+ * 6 - >
+ */
+#define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4)
+ /* 0 - reg
+ * 1 - mem
+ */
+#define WAIT_REG_MEM_OPERATION(x) ((x) << 6)
+ /* 0 - wait_reg_mem
+ * 1 - wr_wait_wr_reg
+ */
+#define WAIT_REG_MEM_ENGINE(x) ((x) << 8)
+ /* 0 - me
+ * 1 - pfp
+ */
+
+static amdgpu_device_handle device_handle;
+static uint32_t major_version;
+static uint32_t minor_version;
+
+static pthread_t stress_thread;
+static uint32_t *ptr;
+
+static void amdgpu_deadlock_helper(unsigned ip_type);
+static void amdgpu_deadlock_gfx(void);
+static void amdgpu_deadlock_compute(void);
+
+int suite_deadlock_tests_init(void)
+{
+ struct amdgpu_gpu_info gpu_info = {0};
+ int r;
+
+ r = amdgpu_device_initialize(drm_amdgpu[0], &major_version,
+ &minor_version, &device_handle);
+
+ if (r) {
+ if ((r == -EACCES) && (errno == EACCES))
+ printf("\n\nError:%s. "
+ "Hint:Try to run this test program as root.",
+ strerror(errno));
+ return CUE_SINIT_FAILED;
+ }
+
+ return CUE_SUCCESS;
+}
