Tag 'mesa-10.5.5' created by Emil Velikov <emil.l.veli...@gmail.com> at
2015-05-11 19:21 +0000
Mesa 10.5.5 release
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Changes since mesa-10.5.4:
Boyan Ding (1):
i965: Add XRGB8888 format to intel_screen_make_configs
Emil Velikov (4):
docs: Add sha256 sums for the 10.5.4 release
r300: do not link against libdrm_intel
Update version to 10.5.5
Add release notes for the 10.5.5 release
Ilia Mirkin (4):
nvc0/ir: flush denorms to zero in non-compute shaders
gk110/ir: fix set with a register dest to not auto-set the abs flag
nvc0/ir: fix predicated PFETCH emission
nv50/ir: fix asFlow() const helper for OP_JOIN
Kenneth Graunke (2):
i965: Make intel_emit_linear_blit handle Gen8+ alignment restrictions.
i965: Disallow linear blits that are not cacheline aligned.
Roland Scheidegger (1):
draw: fix prim ids when there's no gs
---
VERSION | 2
docs/relnotes/10.5.4.html | 3
docs/relnotes/10.5.5.html | 94 ++++++++++
src/gallium/auxiliary/draw/draw_context.c | 1
src/gallium/auxiliary/draw/draw_prim_assembler.c | 13 +
src/gallium/auxiliary/draw/draw_prim_assembler.h | 3
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp | 6
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 4
src/gallium/drivers/nouveau/codegen/nv50_ir_inlines.h | 2
src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 25 ++
src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.h | 1
src/gallium/drivers/r300/Automake.inc | 2
src/mesa/drivers/dri/i965/intel_blit.c | 49 +++--
src/mesa/drivers/dri/i965/intel_screen.c | 3
14 files changed, 181 insertions(+), 27 deletions(-)
---
