Tag 'mesa-10.2-rc5' created by Ian Romanick <ian.d.roman...@intel.com> at
2014-05-31 00:29 +0000
Mesa 10.2 release candidate 5
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Changes since mesa-10.2-rc4:
Brian Paul (1):
glsl: fix use-after free bug/crash in ast_declarator_list::hir()
Christoph Bumiller (7):
nv50,nvc0: always pull out bufctx on context destruction
nv50: setup scissors on clear_render_target/depth_stencil
nv50,nvc0: set constbufs dirty on pipe context switch
nv50/ir/tgsi: TGSI_OPCODE_POW replicates its result
nv50/ir/opt: fix constant folding with saturate modifier
nv50/ir: fix lowering of predicated instructions (without defs)
nv50/ir/tgsi: optimize KIL
Emil Velikov (1):
glx: do not leak dri3Display
Ian Romanick (2):
glapi: Duplicate GLES1 prototypes in glapi_dispatch.c
Bump version to 10.2-rc5
Ilia Mirkin (2):
mesa/st: fix color outputs in presence of sample mask output
nvc0: revert mistaken logic to collapse color outputs to the beginning
Jerome Glisse (1):
glx: load dri driver with RTLD_LOCAL so dlclose never fails to unload
Kenneth Graunke (1):
i965: Fix repeated usage of rectangle texture coordinate scaling.
Lubomir Rintel (1):
i915: add a missing NULL pointer check
Matt Turner (6):
Revert "i965/vec4: Change vec4_visitor::emit_lrp to use MAC for gen<6"
Revert "i965/fs: Change fs_visitor::emit_lrp to use MAC for gen<6"
Revert "i965/fs: Reduce restrictions on interference in register
coalescing."
Revert "i965/fs: Give up in interference check if we see a WHILE."
Revert "i965/fs: Simplify interference scan in register coalescing."
Revert "i965: Don't make instructions with a null dest a barrier to
scheduling."
Pavel Popov (1):
i965: Fix Line Stipple enable bit in 3DSTATE_SF for Haswell.
Rob Clark (1):
configure: fix build error with XA
Topi Pohjolainen (3):
meta/blit: Add stencil texturing mode save and restore
i965/meta: Store stencil texturing mode
meta/blit: Use gl_FragColor also in the msaa blit shader
---
VERSION | 2
configure.ac | 1
src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 11 +
src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nv50.cpp | 5
src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp | 4
src/gallium/drivers/nouveau/nv50/nv50_context.c | 7 -
src/gallium/drivers/nouveau/nv50/nv50_state_validate.c | 4
src/gallium/drivers/nouveau/nv50/nv50_surface.c | 20 +++
src/gallium/drivers/nouveau/nvc0/nvc0_context.c | 9 -
src/gallium/drivers/nouveau/nvc0/nvc0_program.c | 13 --
src/gallium/drivers/nouveau/nvc0/nvc0_state_validate.c | 1
src/glsl/ast_to_hir.cpp | 6 -
src/glx/dri_common.c | 10 -
src/glx/glxext.c | 4
src/mapi/glapi/glapi_dispatch.c | 57 ++++++++++
src/mesa/drivers/common/meta.h | 4
src/mesa/drivers/common/meta_blit.c | 15 ++
src/mesa/drivers/dri/i915/intel_context.c | 2
src/mesa/drivers/dri/i965/brw_defines.h | 2
src/mesa/drivers/dri/i965/brw_fs_register_coalesce.cpp | 37 ++++--
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 38 ++++--
src/mesa/drivers/dri/i965/brw_meta_stencil_blit.c | 1
src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp | 12 --
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 16 +-
src/mesa/state_tracker/st_program.c | 30 ++---
25 files changed, 227 insertions(+), 84 deletions(-)
---
