Rebased ref, commits from common ancestor:
commit a04f4015d6afef20c2b79e2779f6555836ee2b07
Author: Michel Dänzer <michel.daen...@amd.com>
Date:   Thu Apr 7 16:47:25 2016 +0900

    Bump version for 1.1.0 release

diff --git a/configure.ac b/configure.ac
index b11475a..824467d 100644
--- a/configure.ac
+++ b/configure.ac
@@ -23,7 +23,7 @@
 # Initialize Autoconf
 AC_PREREQ([2.60])
 AC_INIT([xf86-video-amdgpu],
-        [1.0.99],
+        [1.1.0],
         [https://bugs.freedesktop.org/enter_bug.cgi?product=xorg],
         [xf86-video-amdgpu])
 

commit aed1c17c43b2c0c983f6fc0973a5224d0faf32d9
Author: Michel Dänzer <michel.daen...@amd.com>
Date:   Mon Apr 4 18:28:02 2016 +0900

    glamor: Force GPU rendering to/from pixmaps created via DRI3
    
    Fixes crash when running DRI3 clients with ShadowPrimary enabled.
    
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94799
    
    Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>

diff --git a/src/amdgpu_dri3.c b/src/amdgpu_dri3.c
index c3042e7..0686599 100644
--- a/src/amdgpu_dri3.c
+++ b/src/amdgpu_dri3.c
@@ -135,8 +135,12 @@ static PixmapPtr amdgpu_dri3_pixmap_from_fd(ScreenPtr 
screen,
        if (AMDGPUPTR(xf86ScreenToScrn(screen))->use_glamor) {
                pixmap = glamor_pixmap_from_fd(screen, fd, width, height,
                                               stride, depth, bpp);
-               if (pixmap)
+               if (pixmap) {
+                       struct amdgpu_pixmap *priv = calloc(1, sizeof(*priv));
+
+                       amdgpu_set_pixmap_private(pixmap, priv);
                        return pixmap;
+               }
        }
 #endif
 
diff --git a/src/amdgpu_glamor_wrappers.c b/src/amdgpu_glamor_wrappers.c
index 6700851..35b6d7e 100644
--- a/src/amdgpu_glamor_wrappers.c
+++ b/src/amdgpu_glamor_wrappers.c
@@ -148,10 +148,11 @@ amdgpu_glamor_finish_access_cpu(PixmapPtr pixmap)
  */
 
 static Bool
-amdgpu_glamor_use_gpu(PixmapPtr pixmap)
+amdgpu_glamor_use_gpu(PixmapPtr pixmap, struct amdgpu_pixmap *priv)
 {
        return (pixmap->usage_hint &
-               (AMDGPU_CREATE_PIXMAP_SCANOUT | AMDGPU_CREATE_PIXMAP_DRI2)) != 
0;
+               (AMDGPU_CREATE_PIXMAP_SCANOUT | AMDGPU_CREATE_PIXMAP_DRI2)) != 
0 ||
+               (priv && !priv->bo);
 }
 
 static Bool
@@ -432,7 +433,7 @@ amdgpu_glamor_poly_fill_rect(DrawablePtr pDrawable, GCPtr 
pGC,
        PixmapPtr pixmap = get_drawable_pixmap(pDrawable);
        struct amdgpu_pixmap *priv = amdgpu_get_pixmap_private(pixmap);
 
-       if ((info->force_accel || amdgpu_glamor_use_gpu(pixmap)) &&
+       if ((info->force_accel || amdgpu_glamor_use_gpu(pixmap, priv)) &&
            amdgpu_glamor_prepare_access_gpu(priv)) {
                info->glamor.SavedPolyFillRect(pDrawable, pGC, nrect, prect);
                amdgpu_glamor_finish_access_gpu_rw(info, priv);
@@ -536,8 +537,8 @@ amdgpu_glamor_copy_area(DrawablePtr pSrcDrawable, 
DrawablePtr pDstDrawable,
        struct amdgpu_pixmap *dst_priv = amdgpu_get_pixmap_private(dst_pixmap);
        RegionPtr ret = NULL;
 
-       if (amdgpu_glamor_use_gpu(dst_pixmap) ||
-           amdgpu_glamor_use_gpu(src_pixmap)) {
+       if (amdgpu_glamor_use_gpu(dst_pixmap, dst_priv) ||
+           amdgpu_glamor_use_gpu(src_pixmap, src_priv)) {
                if (!amdgpu_glamor_prepare_access_gpu(dst_priv))
                        goto fallback;
                if (src_priv != dst_priv &&

commit faf9d720b7d650f5f1ea657a874d08eac3972e60
Author: Michel Dänzer <michel.daen...@amd.com>
Date:   Fri Apr 1 16:09:51 2016 +0900

    Update manpage entry for Option "TearFree"
    
    It's now effective for rotation as well.
    
    Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>

diff --git a/man/amdgpu.man b/man/amdgpu.man
index 4e95ead..0100400 100644
--- a/man/amdgpu.man
+++ b/man/amdgpu.man
@@ -72,9 +72,10 @@ Enable DRI2 page flipping.  The default is
 .TP
 .BI "Option \*qTearFree\*q \*q" boolean \*q
 Enable tearing prevention using the hardware page flipping mechanism. This
-option currently doesn't have any effect for rotated CRTCs. It requires
-allocating two separate scanout buffers for each non-rotated CRTC. Enabling
-this option currently disables Option \*qEnablePageFlip\*q. The default is
+option currently doesn't have any effect for CRTCs using transforms other than
+rotation or reflection. It requires allocating two separate scanout buffers for
+each supported CRTC. Enabling this option currently disables Option
+\*qEnablePageFlip\*q. The default is
 .B off.
 .TP
 .BI "Option \*qAccelMethod\*q \*q" string \*q

commit 5ba95c3abeb8df82aa8d33a47596eae6403ea7af
Author: Michel Dänzer <michel.daen...@amd.com>
Date:   Fri Apr 1 15:29:26 2016 +0900

    Identify DRM event queue entries by sequence number instead of by pointer
    
    If the memory for an entry was allocated at the same address as that for
    a previously cancelled entry, the handler could theoretically be called
    prematurely, triggered by the DRM event which was submitted for the
    cancelled entry.
    
    (Ported from radeon commit 4693b1bd5b5c381e8b7b68a6f7f0c6696d6a68df)
    
    Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>

diff --git a/src/amdgpu_dri2.c b/src/amdgpu_dri2.c
index 4478b16..29f60ba 100644
--- a/src/amdgpu_dri2.c
+++ b/src/amdgpu_dri2.c
@@ -395,7 +395,7 @@ typedef struct _DRI2FrameEvent {
        unsigned frame;
        xf86CrtcPtr crtc;
        OsTimerPtr timer;
-       struct amdgpu_drm_queue_entry *drm_queue;
+       uintptr_t drm_queue_seq;
 
        /* for swaps & flips only */
        DRI2SwapEventPtr event_complete;
@@ -961,8 +961,8 @@ CARD32 amdgpu_dri2_deferred_event(OsTimerPtr timer, CARD32 
now, pointer data)
         */
        if (!event_info->crtc) {
                ErrorF("%s no crtc\n", __func__);
-               if (event_info->drm_queue)
-                       amdgpu_drm_abort_entry(event_info->drm_queue);
+               if (event_info->drm_queue_seq)
+                       amdgpu_drm_abort_entry(event_info->drm_queue_seq);
                else
                        amdgpu_dri2_frame_event_abort(NULL, data);
                return 0;
@@ -974,9 +974,9 @@ CARD32 amdgpu_dri2_deferred_event(OsTimerPtr timer, CARD32 
now, pointer data)
        if (ret) {
                xf86DrvMsg(scrn->scrnIndex, X_ERROR,
                           "%s cannot get current time\n", __func__);
-               if (event_info->drm_queue)
+               if (event_info->drm_queue_seq)
                        amdgpu_drm_queue_handler(pAMDGPUEnt->fd, 0, 0, 0,
-                                                event_info->drm_queue);
+                                                
(void*)event_info->drm_queue_seq);
                else
                        amdgpu_dri2_frame_event_handler(crtc, 0, 0, data);
                return 0;
@@ -990,9 +990,10 @@ CARD32 amdgpu_dri2_deferred_event(OsTimerPtr timer, CARD32 
now, pointer data)
        delta_seq = delta_t * drmmode_crtc->dpms_last_fps;
        delta_seq /= 1000000;
        frame = (CARD64) drmmode_crtc->dpms_last_seq + delta_seq;
-       if (event_info->drm_queue)
+       if (event_info->drm_queue_seq)
                amdgpu_drm_queue_handler(pAMDGPUEnt->fd, frame, drm_now / 
1000000,
-                                        drm_now % 1000000, 
event_info->drm_queue);
+                                        drm_now % 1000000,
+                                        (void*)event_info->drm_queue_seq);
        else
                amdgpu_dri2_frame_event_handler(crtc, frame, drm_now, data);
        return 0;
@@ -1023,7 +1024,7 @@ static int amdgpu_dri2_schedule_wait_msc(ClientPtr 
client, DrawablePtr draw,
        ScrnInfoPtr scrn = xf86ScreenToScrn(screen);
        AMDGPUEntPtr pAMDGPUEnt = AMDGPUEntPriv(scrn);
        DRI2FrameEventPtr wait_info = NULL;
-       struct amdgpu_drm_queue_entry *wait = NULL;
+       uintptr_t drm_queue_seq = 0;
        xf86CrtcPtr crtc = amdgpu_dri2_drawable_crtc(draw, TRUE);
        uint32_t msc_delta;
        drmVBlank vbl;
@@ -1079,15 +1080,15 @@ static int amdgpu_dri2_schedule_wait_msc(ClientPtr 
client, DrawablePtr draw,
        current_msc = vbl.reply.sequence + msc_delta;
        current_msc &= 0xffffffff;
 
-       wait = amdgpu_drm_queue_alloc(crtc, client, AMDGPU_DRM_QUEUE_ID_DEFAULT,
-                                     wait_info, 
amdgpu_dri2_frame_event_handler,
-                                     amdgpu_dri2_frame_event_abort);
-       if (!wait) {
+       drm_queue_seq = amdgpu_drm_queue_alloc(crtc, client, 
AMDGPU_DRM_QUEUE_ID_DEFAULT,
+                                              wait_info, 
amdgpu_dri2_frame_event_handler,
+                                              amdgpu_dri2_frame_event_abort);
+       if (!drm_queue_seq) {
                xf86DrvMsg(scrn->scrnIndex, X_WARNING,
                           "Allocating DRM queue event entry failed.\n");
                goto out_complete;
        }
-       wait_info->drm_queue = wait;
+       wait_info->drm_queue_seq = drm_queue_seq;
 
        /*
         * If divisor is zero, or current_msc is smaller than target_msc,
@@ -1106,7 +1107,7 @@ static int amdgpu_dri2_schedule_wait_msc(ClientPtr 
client, DrawablePtr draw,
                vbl.request.type = DRM_VBLANK_ABSOLUTE | DRM_VBLANK_EVENT;
                vbl.request.type |= amdgpu_populate_vbl_request_type(crtc);
                vbl.request.sequence = target_msc - msc_delta;
-               vbl.request.signal = (unsigned long)wait;
+               vbl.request.signal = drm_queue_seq;
                ret = drmWaitVBlank(pAMDGPUEnt->fd, &vbl);
                if (ret) {
                        xf86DrvMsg(scrn->scrnIndex, X_WARNING,
@@ -1138,7 +1139,7 @@ static int amdgpu_dri2_schedule_wait_msc(ClientPtr 
client, DrawablePtr draw,
        if ((current_msc % divisor) >= remainder)
                vbl.request.sequence += divisor;
 
-       vbl.request.signal = (unsigned long)wait;
+       vbl.request.signal = drm_queue_seq;
        ret = drmWaitVBlank(pAMDGPUEnt->fd, &vbl);
        if (ret) {
                xf86DrvMsg(scrn->scrnIndex, X_WARNING,
@@ -1190,7 +1191,7 @@ static int amdgpu_dri2_schedule_swap(ClientPtr client, 
DrawablePtr draw,
        drmVBlank vbl;
        int ret, flip = 0;
        DRI2FrameEventPtr swap_info = NULL;
-       struct amdgpu_drm_queue_entry *swap;
+       uintptr_t drm_queue_seq;
        CARD64 current_msc;
        BoxRec box;
        RegionRec region;
@@ -1227,15 +1228,15 @@ static int amdgpu_dri2_schedule_swap(ClientPtr client, 
DrawablePtr draw,
        swap_info->back = back;
        swap_info->crtc = crtc;
 
-       swap = amdgpu_drm_queue_alloc(crtc, client, AMDGPU_DRM_QUEUE_ID_DEFAULT,
-                                     swap_info, 
amdgpu_dri2_frame_event_handler,
-                                     amdgpu_dri2_frame_event_abort);
-       if (!swap) {
+       drm_queue_seq = amdgpu_drm_queue_alloc(crtc, client, 
AMDGPU_DRM_QUEUE_ID_DEFAULT,
+                                              swap_info, 
amdgpu_dri2_frame_event_handler,
+                                              amdgpu_dri2_frame_event_abort);
+       if (!drm_queue_seq) {
                xf86DrvMsg(scrn->scrnIndex, X_WARNING,
                           "Allocating DRM queue entry failed.\n");
                goto blit_fallback;
        }
-       swap_info->drm_queue = swap;
+       swap_info->drm_queue_seq = drm_queue_seq;
 
        /*
         * CRTC is in DPMS off state, fallback to blit, but calculate
@@ -1304,7 +1305,7 @@ static int amdgpu_dri2_schedule_swap(ClientPtr client, 
DrawablePtr draw,
                        *target_msc = current_msc;
 
                vbl.request.sequence = *target_msc - msc_delta;
-               vbl.request.signal = (unsigned long)swap;
+               vbl.request.signal = drm_queue_seq;
                ret = drmWaitVBlank(pAMDGPUEnt->fd, &vbl);
                if (ret) {
                        xf86DrvMsg(scrn->scrnIndex, X_WARNING,
@@ -1350,7 +1351,7 @@ static int amdgpu_dri2_schedule_swap(ClientPtr client, 
DrawablePtr draw,
        /* Account for 1 frame extra pageflip delay if flip > 0 */
        vbl.request.sequence -= flip;
 
-       vbl.request.signal = (unsigned long)swap;
+       vbl.request.signal = drm_queue_seq;
        ret = drmWaitVBlank(pAMDGPUEnt->fd, &vbl);
        if (ret) {
                xf86DrvMsg(scrn->scrnIndex, X_WARNING,
diff --git a/src/amdgpu_drm_queue.c b/src/amdgpu_drm_queue.c
index 11b74a0..562a11a 100644
--- a/src/amdgpu_drm_queue.c
+++ b/src/amdgpu_drm_queue.c
@@ -40,6 +40,7 @@
 struct amdgpu_drm_queue_entry {
        struct xorg_list list;
        uint64_t id;
+       uintptr_t seq;
        void *data;
        ClientPtr client;
        xf86CrtcPtr crtc;
@@ -49,6 +50,7 @@ struct amdgpu_drm_queue_entry {
 
 static int amdgpu_drm_queue_refcnt;
 static struct xorg_list amdgpu_drm_queue;
+static uintptr_t amdgpu_drm_queue_seq;
 
 
 /*
@@ -58,11 +60,11 @@ void
 amdgpu_drm_queue_handler(int fd, unsigned int frame, unsigned int sec,
                         unsigned int usec, void *user_ptr)
 {
-       struct amdgpu_drm_queue_entry *user_data = user_ptr;
+       uintptr_t seq = (uintptr_t)user_ptr;
        struct amdgpu_drm_queue_entry *e, *tmp;
 
        xorg_list_for_each_entry_safe(e, tmp, &amdgpu_drm_queue, list) {
-               if (e == user_data) {
+               if (e->seq == seq) {
                        xorg_list_del(&e->list);
                        if (e->handler)
                                e->handler(e->crtc, frame,
@@ -80,7 +82,7 @@ amdgpu_drm_queue_handler(int fd, unsigned int frame, unsigned 
int sec,
  * Enqueue a potential drm response; when the associated response
  * appears, we've got data to pass to the handler from here
  */
-struct amdgpu_drm_queue_entry *
+uintptr_t
 amdgpu_drm_queue_alloc(xf86CrtcPtr crtc, ClientPtr client,
                       uint64_t id, void *data,
                       amdgpu_drm_handler_proc handler,
@@ -92,6 +94,9 @@ amdgpu_drm_queue_alloc(xf86CrtcPtr crtc, ClientPtr client,
        if (!e)
                return NULL;
 
+       if (!amdgpu_drm_queue_seq)
+               amdgpu_drm_queue_seq = 1;
+       e->seq = amdgpu_drm_queue_seq++;
        e->client = client;
        e->crtc = crtc;
        e->id = id;
@@ -101,7 +106,7 @@ amdgpu_drm_queue_alloc(xf86CrtcPtr crtc, ClientPtr client,
 
        xorg_list_add(&e->list, &amdgpu_drm_queue);
 
-       return e;
+       return e->seq;
 }
 
 /*
@@ -139,9 +144,16 @@ amdgpu_drm_abort_client(ClientPtr client)
  * Abort specific drm queue entry
  */
 void
-amdgpu_drm_abort_entry(struct amdgpu_drm_queue_entry *entry)
+amdgpu_drm_abort_entry(uintptr_t seq)
 {
-       amdgpu_drm_abort_one(entry);
+       struct amdgpu_drm_queue_entry *e, *tmp;
+
+       xorg_list_for_each_entry_safe(e, tmp, &amdgpu_drm_queue, list) {
+               if (e->seq == seq) {
+                       amdgpu_drm_abort_one(e);
+                       break;
+               }
+       }
 }
 
 /*
diff --git a/src/amdgpu_drm_queue.h b/src/amdgpu_drm_queue.h
index 892ba13..b4d4009 100644
--- a/src/amdgpu_drm_queue.h
+++ b/src/amdgpu_drm_queue.h
@@ -43,14 +43,12 @@ typedef void (*amdgpu_drm_abort_proc)(xf86CrtcPtr crtc, 
void *data);
 void amdgpu_drm_queue_handler(int fd, unsigned int frame,
                              unsigned int tv_sec, unsigned int tv_usec,
                              void *user_ptr);
-struct amdgpu_drm_queue_entry *amdgpu_drm_queue_alloc(xf86CrtcPtr crtc,
-                                                     ClientPtr client,
-                                                     uint64_t id,
-                                                     void *data,
-                                                     amdgpu_drm_handler_proc 
handler,
-                                                     amdgpu_drm_abort_proc 
abort);
+uintptr_t amdgpu_drm_queue_alloc(xf86CrtcPtr crtc, ClientPtr client,
+                                uint64_t id, void *data,
+                                amdgpu_drm_handler_proc handler,
+                                amdgpu_drm_abort_proc abort);
 void amdgpu_drm_abort_client(ClientPtr client);
-void amdgpu_drm_abort_entry(struct amdgpu_drm_queue_entry *entry);
+void amdgpu_drm_abort_entry(uintptr_t seq);
 void amdgpu_drm_abort_id(uint64_t id);
 void amdgpu_drm_queue_init();
 void amdgpu_drm_queue_close(ScrnInfoPtr scrn);
diff --git a/src/amdgpu_kms.c b/src/amdgpu_kms.c
index 6dcec69..ae98cf1 100644
--- a/src/amdgpu_kms.c
+++ b/src/amdgpu_kms.c
@@ -397,7 +397,7 @@ static void
 amdgpu_scanout_update(xf86CrtcPtr xf86_crtc)
 {
        drmmode_crtc_private_ptr drmmode_crtc = xf86_crtc->driver_private;
-       struct amdgpu_drm_queue_entry *drm_queue_entry;
+       uintptr_t drm_queue_seq;
        ScrnInfoPtr scrn;
        AMDGPUEntPtr pAMDGPUEnt;
        drmVBlank vbl;
@@ -427,13 +427,13 @@ amdgpu_scanout_update(xf86CrtcPtr xf86_crtc)
                return;
 
        scrn = xf86_crtc->scrn;
-       drm_queue_entry = amdgpu_drm_queue_alloc(xf86_crtc,
-                                                
AMDGPU_DRM_QUEUE_CLIENT_DEFAULT,
-                                                AMDGPU_DRM_QUEUE_ID_DEFAULT,
-                                                drmmode_crtc,
-                                                amdgpu_scanout_update_handler,
-                                                amdgpu_scanout_update_abort);
-       if (!drm_queue_entry) {
+       drm_queue_seq = amdgpu_drm_queue_alloc(xf86_crtc,
+                                              AMDGPU_DRM_QUEUE_CLIENT_DEFAULT,
+                                              AMDGPU_DRM_QUEUE_ID_DEFAULT,
+                                              drmmode_crtc,
+                                              amdgpu_scanout_update_handler,
+                                              amdgpu_scanout_update_abort);
+       if (!drm_queue_seq) {
                xf86DrvMsg(scrn->scrnIndex, X_WARNING,
                           "amdgpu_drm_queue_alloc failed for scanout 
update\n");
                return;
@@ -443,12 +443,12 @@ amdgpu_scanout_update(xf86CrtcPtr xf86_crtc)
        vbl.request.type = DRM_VBLANK_RELATIVE | DRM_VBLANK_EVENT;
        vbl.request.type |= amdgpu_populate_vbl_request_type(xf86_crtc);
        vbl.request.sequence = 1;
-       vbl.request.signal = (unsigned long)drm_queue_entry;
+       vbl.request.signal = drm_queue_seq;
        if (drmWaitVBlank(pAMDGPUEnt->fd, &vbl)) {
                xf86DrvMsg(scrn->scrnIndex, X_WARNING,
                           "drmWaitVBlank failed for scanout update: %s\n",
                           strerror(errno));
-               amdgpu_drm_abort_entry(drm_queue_entry);
+               amdgpu_drm_abort_entry(drm_queue_seq);
                return;
        }
 
@@ -471,7 +471,7 @@ amdgpu_scanout_flip(ScreenPtr pScreen, AMDGPUInfoPtr info,
        drmmode_crtc_private_ptr drmmode_crtc = xf86_crtc->driver_private;
        ScrnInfoPtr scrn;
        AMDGPUEntPtr pAMDGPUEnt;
-       struct amdgpu_drm_queue_entry *drm_queue_entry;
+       uintptr_t drm_queue_seq;
        unsigned scanout_id;
 
        if (drmmode_crtc->scanout_update_pending)
@@ -482,12 +482,12 @@ amdgpu_scanout_flip(ScreenPtr pScreen, AMDGPUInfoPtr info,
                return;
 
        scrn = xf86_crtc->scrn;
-       drm_queue_entry = amdgpu_drm_queue_alloc(xf86_crtc,
-                                                
AMDGPU_DRM_QUEUE_CLIENT_DEFAULT,
-                                                AMDGPU_DRM_QUEUE_ID_DEFAULT,
-                                                drmmode_crtc, NULL,
-                                                amdgpu_scanout_flip_abort);
-       if (!drm_queue_entry) {
+       drm_queue_seq = amdgpu_drm_queue_alloc(xf86_crtc,
+                                              AMDGPU_DRM_QUEUE_CLIENT_DEFAULT,
+                                              AMDGPU_DRM_QUEUE_ID_DEFAULT,
+                                              drmmode_crtc, NULL,
+                                              amdgpu_scanout_flip_abort);
+       if (!drm_queue_seq) {
                xf86DrvMsg(scrn->scrnIndex, X_WARNING,
                           "Allocating DRM event queue entry failed.\n");
                return;
@@ -496,7 +496,7 @@ amdgpu_scanout_flip(ScreenPtr pScreen, AMDGPUInfoPtr info,
        pAMDGPUEnt = AMDGPUEntPriv(scrn);
        if (drmModePageFlip(pAMDGPUEnt->fd, drmmode_crtc->mode_crtc->crtc_id,
                            drmmode_crtc->scanout[scanout_id].fb_id,
-                           DRM_MODE_PAGE_FLIP_EVENT, drm_queue_entry)) {
+                           DRM_MODE_PAGE_FLIP_EVENT, (void*)drm_queue_seq)) {
                xf86DrvMsg(scrn->scrnIndex, X_WARNING, "flip queue failed in 
%s: %s\n",
                           __func__, strerror(errno));
                return;
diff --git a/src/amdgpu_present.c b/src/amdgpu_present.c
index 4b33ce2..4aa0708 100644
--- a/src/amdgpu_present.c
+++ b/src/amdgpu_present.c
@@ -157,7 +157,7 @@ amdgpu_present_queue_vblank(RRCrtcPtr crtc, uint64_t 
event_id, uint64_t msc)
        AMDGPUEntPtr pAMDGPUEnt = AMDGPUEntPriv(scrn);
        int crtc_id = drmmode_get_crtc_id(xf86_crtc);
        struct amdgpu_present_vblank_event *event;
-       struct amdgpu_drm_queue_entry *queue;
+       uintptr_t drm_queue_seq;
        drmVBlank vbl;
        int ret;
 
@@ -165,24 +165,25 @@ amdgpu_present_queue_vblank(RRCrtcPtr crtc, uint64_t 
event_id, uint64_t msc)
        if (!event)
                return BadAlloc;
        event->event_id = event_id;
-       queue = amdgpu_drm_queue_alloc(xf86_crtc, 
AMDGPU_DRM_QUEUE_CLIENT_DEFAULT,
-                                      event_id, event,
-                                      amdgpu_present_vblank_handler,
-                                      amdgpu_present_vblank_abort);
-       if (!queue) {
+       drm_queue_seq = amdgpu_drm_queue_alloc(xf86_crtc,
+                                              AMDGPU_DRM_QUEUE_CLIENT_DEFAULT,
+                                              event_id, event,
+                                              amdgpu_present_vblank_handler,
+                                              amdgpu_present_vblank_abort);
+       if (!drm_queue_seq) {
                free(event);
                return BadAlloc;
        }
 
        vbl.request.type = DRM_VBLANK_ABSOLUTE | DRM_VBLANK_EVENT | 
crtc_select(crtc_id);
        vbl.request.sequence = msc;
-       vbl.request.signal = (unsigned long)queue;
+       vbl.request.signal = drm_queue_seq;
        for (;;) {
                ret = drmWaitVBlank(pAMDGPUEnt->fd, &vbl);
                if (!ret)
                        break;
                if (errno != EBUSY || !amdgpu_present_flush_drm_events(screen)) 
{
-                       amdgpu_drm_abort_entry(queue);
+                       amdgpu_drm_abort_entry(drm_queue_seq);
                        return BadAlloc;
                }
        }
diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index 2aea542..07ae9b2 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -2504,7 +2504,7 @@ Bool amdgpu_do_pageflip(ScrnInfoPtr scrn, ClientPtr 
client,
        drmmode_ptr drmmode = drmmode_crtc->drmmode;
        int i;
        drmmode_flipdata_ptr flipdata;
-       struct amdgpu_drm_queue_entry *drm_queue = NULL;
+       uintptr_t drm_queue_seq = 0;
        uint32_t new_front_handle;
 
        if (!amdgpu_pixmap_get_handle(new_front, &new_front_handle)) {
@@ -2559,11 +2559,11 @@ Bool amdgpu_do_pageflip(ScrnInfoPtr scrn, ClientPtr 
client,
                if (drmmode_crtc->hw_id == ref_crtc_hw_id)
                        flipdata->fe_crtc = crtc;
 
-               drm_queue = amdgpu_drm_queue_alloc(crtc, client, id,
-                                                  flipdata,
-                                                  drmmode_flip_handler,
-                                                  drmmode_flip_abort);
-               if (!drm_queue) {
+               drm_queue_seq = amdgpu_drm_queue_alloc(crtc, client, id,
+                                                      flipdata,
+                                                      drmmode_flip_handler,
+                                                      drmmode_flip_abort);
+               if (!drm_queue_seq) {
                        xf86DrvMsg(scrn->scrnIndex, X_WARNING,
                                   "Allocating DRM queue event entry 
failed.\n");
                        goto error;
@@ -2571,13 +2571,13 @@ Bool amdgpu_do_pageflip(ScrnInfoPtr scrn, ClientPtr 
client,
 
                if (drmModePageFlip(pAMDGPUEnt->fd, 
drmmode_crtc->mode_crtc->crtc_id,
                                    drmmode->fb_id, DRM_MODE_PAGE_FLIP_EVENT,
-                                   drm_queue)) {
+                                   (void*)drm_queue_seq)) {
                        xf86DrvMsg(scrn->scrnIndex, X_WARNING,
                                   "flip queue failed: %s\n", strerror(errno));
                        goto error;
                }
                drmmode_crtc->flip_pending = TRUE;
-               drm_queue = NULL;
+               drm_queue_seq = 0;
        }
 
        if (flipdata->flip_count > 0)
@@ -2589,8 +2589,8 @@ error:
                drmmode->fb_id = flipdata->old_fb_id;
        }
 
-       if (drm_queue)
-               amdgpu_drm_abort_entry(drm_queue);
+       if (drm_queue_seq)
+               amdgpu_drm_abort_entry(drm_queue_seq);
        else if (crtc)
                drmmode_flip_abort(crtc, flipdata);
        else if (flipdata && flipdata->flip_count <= 1)

commit 8ecfa69b5a833bd4c39e773a6acfd7eef9144d13
Author: Michel Dänzer <michel.daen...@amd.com>
Date:   Wed Mar 30 18:33:00 2016 +0900

    DRI3: Refuse to open DRM file descriptor for ssh clients
    
    Fixes hangs when attempting to use DRI3 on display connections forwarded
    via SSH.
    
    Don't do this for Xorg > 1.18.99.1 since the corresponding xserver
    change has landed in Git master.
    
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93261
    
    (Ported from radeon commit 0b3aac1de9db42bfca545fa331e4985836682ec7)
    
    Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>

diff --git a/src/amdgpu_dri3.c b/src/amdgpu_dri3.c
index 06d0668..c3042e7 100644
--- a/src/amdgpu_dri3.c
+++ b/src/amdgpu_dri3.c
@@ -38,6 +38,7 @@
 #include <sys/stat.h>
 #include <fcntl.h>
 #include <errno.h>
+#include <libgen.h>
 
 
 static int
@@ -87,6 +88,38 @@ amdgpu_dri3_open(ScreenPtr screen, RRProviderPtr provider, 
int *out)
        return Success;
 }
 
+#if DRI3_SCREEN_INFO_VERSION >= 1 && XORG_VERSION_CURRENT <= 
XORG_VERSION_NUMERIC(1,18,99,1,0)
+
+static int
+amdgpu_dri3_open_client(ClientPtr client, ScreenPtr screen,
+                       RRProviderPtr provider, int *out)
+{
+       const char *cmdname = GetClientCmdName(client);
+       Bool is_ssh = FALSE;
+
+       /* If the executable name is "ssh", assume that this client connection
+        * is forwarded from another host via SSH
+        */
+       if (cmdname) {
+               char *cmd = strdup(cmdname);
+
+               /* Cut off any colon and whatever comes after it, see
+                * 
https://lists.freedesktop.org/archives/xorg-devel/2015-December/048164.html
+                */
+               cmd = strtok(cmd, ":");
+
+               is_ssh = strcmp(basename(cmd), "ssh") == 0;
+               free(cmd);
+       }
+
+       if (!is_ssh)
+               return amdgpu_dri3_open(screen, provider, out);
+
+       return BadAccess;
+}
+
+#endif /* DRI3_SCREEN_INFO_VERSION >= 1 && XORG_VERSION_CURRENT <= 
XORG_VERSION_NUMERIC(1,18,99,1,0) */
+
 static PixmapPtr amdgpu_dri3_pixmap_from_fd(ScreenPtr screen,
                                            int fd,
                                            CARD16 width,
@@ -172,9 +205,13 @@ static int amdgpu_dri3_fd_from_pixmap(ScreenPtr screen,
 }
 
 static dri3_screen_info_rec amdgpu_dri3_screen_info = {
+#if DRI3_SCREEN_INFO_VERSION >= 1 && XORG_VERSION_CURRENT <= 
XORG_VERSION_NUMERIC(1,18,99,1,0)
+       .version = 1,
+       .open_client = amdgpu_dri3_open_client,
+#else
        .version = 0,
-
        .open = amdgpu_dri3_open,
+#endif
        .pixmap_from_fd = amdgpu_dri3_pixmap_from_fd,
        .fd_from_pixmap = amdgpu_dri3_fd_from_pixmap
 };

commit b2a2e114eec0967f7b67f030fbab8983cf980489
Author: Michel Dänzer <michel.daen...@amd.com>
Date:   Fri Mar 25 11:55:34 2016 +0900

    Revert "Use render node for DRI3 if available"
    
    This reverts commit ea558e645786b08d75307716036045170e97b43e.
    
    It broke VDPAU<->GL interop with DRI3 enabled, because the Gallium VDPAU
    code doesn't support DRI3 yet. We can consider re-enabling this once
    there is a Mesa release where the Gallium VDPAU code supports DRI3.
    
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94675
    
    Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>

diff --git a/configure.ac b/configure.ac
index 58b79c5..b11475a 100644
--- a/configure.ac
+++ b/configure.ac
@@ -71,7 +71,7 @@ XORG_DRIVER_CHECK_EXT(XV, videoproto)
 XORG_DRIVER_CHECK_EXT(DPMSExtension, xextproto)
 
 # Checks for libraries.
-PKG_CHECK_MODULES(LIBDRM, [libdrm >= 2.4.60])
+PKG_CHECK_MODULES(LIBDRM, [libdrm >= 2.4.58])
 PKG_CHECK_MODULES(LIBDRM_AMDGPU, [libdrm_amdgpu])
 PKG_CHECK_MODULES(GBM, [gbm])
 
diff --git a/src/amdgpu_dri3.c b/src/amdgpu_dri3.c
index 65d4899..06d0668 100644
--- a/src/amdgpu_dri3.c
+++ b/src/amdgpu_dri3.c
@@ -39,7 +39,9 @@
 #include <fcntl.h>
 #include <errno.h>
 
-static int open_master_node(ScreenPtr screen, int *out)
+
+static int
+amdgpu_dri3_open(ScreenPtr screen, RRProviderPtr provider, int *out)
 {
        ScrnInfoPtr scrn = xf86ScreenToScrn(screen);
        AMDGPUEntPtr pAMDGPUEnt = AMDGPUEntPriv(scrn);
@@ -85,36 +87,6 @@ static int open_master_node(ScreenPtr screen, int *out)
        return Success;
 }
 
-static int open_render_node(ScreenPtr screen, int *out)
-{
-       ScrnInfoPtr scrn = xf86ScreenToScrn(screen);
-       AMDGPUEntPtr pAMDGPUEnt = AMDGPUEntPriv(scrn);
-       int fd;
-
-       fd = open(pAMDGPUEnt->render_node, O_RDWR | O_CLOEXEC);
-       if (fd < 0)
-               return BadAlloc;
-
-       *out = fd;
-       return Success;
-}
-
-static int
-amdgpu_dri3_open(ScreenPtr screen, RRProviderPtr provider, int *out)
-{
-       ScrnInfoPtr scrn = xf86ScreenToScrn(screen);
-       AMDGPUEntPtr pAMDGPUEnt = AMDGPUEntPriv(scrn);
-       int ret = BadAlloc;
-
-       if (pAMDGPUEnt->render_node)
-               ret = open_render_node(screen, out);
-
-       if (ret != Success)
-               ret = open_master_node(screen, out);
-
-       return ret;
-}
-
 static PixmapPtr amdgpu_dri3_pixmap_from_fd(ScreenPtr screen,
                                            int fd,
                                            CARD16 width,
@@ -211,9 +183,6 @@ Bool
 amdgpu_dri3_screen_init(ScreenPtr screen)
 {
        ScrnInfoPtr scrn = xf86ScreenToScrn(screen);
-       AMDGPUEntPtr pAMDGPUEnt = AMDGPUEntPriv(scrn);
-
-       pAMDGPUEnt->render_node = drmGetRenderDeviceNameFromFd(pAMDGPUEnt->fd);
 
        if (!dri3_screen_init(screen, &amdgpu_dri3_screen_info)) {
                xf86DrvMsg(scrn->scrnIndex, X_WARNING,
diff --git a/src/amdgpu_probe.h b/src/amdgpu_probe.h
index 865c197..1e6b99e 100644
--- a/src/amdgpu_probe.h
+++ b/src/amdgpu_probe.h
@@ -88,7 +88,6 @@ typedef struct {
        int fd_wakeup_ref;
        unsigned int assigned_crtcs;
        struct xf86_platform_device *platform_dev;
-       char *render_node;
 } AMDGPUEntRec, *AMDGPUEntPtr;
 
 extern const OptionInfoRec *AMDGPUOptionsWeak(void);

commit e31a2d668a1b5ebaf75d423c8123cbc8e0dcbae9
Author: Flora Cui <flora....@amd.com>
Date:   Wed Nov 18 16:44:13 2015 +0800

    add polaris10 pci id
    
    Reviewed-by: Michel Dänzer <michel.daen...@amd.com>
    Signed-off-by: Flora Cui <flora....@amd.com>
    Reviewed-by: Jammy Zhou <jammy.z...@amd.com>

diff --git a/src/amdgpu_chipinfo_gen.h b/src/amdgpu_chipinfo_gen.h
index df8d717..4a0f6b8 100644
--- a/src/amdgpu_chipinfo_gen.h
+++ b/src/amdgpu_chipinfo_gen.h
@@ -85,4 +85,6 @@ static AMDGPUCardInfo AMDGPUCards[] = {
  { 0x67E9, CHIP_FAMILY_POLARIS11 },
  { 0x67EB, CHIP_FAMILY_POLARIS11 },
  { 0x67FF, CHIP_FAMILY_POLARIS11 },
+ { 0x67C0, CHIP_FAMILY_POLARIS10 },
+ { 0x67DF, CHIP_FAMILY_POLARIS10 },
 };
diff --git a/src/amdgpu_chipset_gen.h b/src/amdgpu_chipset_gen.h
index fe7c7a8..1be967c 100644
--- a/src/amdgpu_chipset_gen.h
+++ b/src/amdgpu_chipset_gen.h
@@ -85,5 +85,7 @@ SymTabRec AMDGPUChipsets[] = {
   { PCI_CHIP_POLARIS11_67E9, "POLARIS11" },
   { PCI_CHIP_POLARIS11_67EB, "POLARIS11" },
   { PCI_CHIP_POLARIS11_67FF, "POLARIS11" },
+  { PCI_CHIP_POLARIS10_67C0, "POLARIS10" },
+  { PCI_CHIP_POLARIS10_67DF, "POLARIS10" },
   { -1,                 NULL }
 };
diff --git a/src/amdgpu_pci_chipset_gen.h b/src/amdgpu_pci_chipset_gen.h
index 3fa9a47..9ed8faf 100644
--- a/src/amdgpu_pci_chipset_gen.h
+++ b/src/amdgpu_pci_chipset_gen.h
@@ -85,5 +85,7 @@ static PciChipsets AMDGPUPciChipsets[] = {
  { PCI_CHIP_POLARIS11_67E9, PCI_CHIP_POLARIS11_67E9, RES_SHARED_VGA },
  { PCI_CHIP_POLARIS11_67EB, PCI_CHIP_POLARIS11_67EB, RES_SHARED_VGA },
  { PCI_CHIP_POLARIS11_67FF, PCI_CHIP_POLARIS11_67FF, RES_SHARED_VGA },
+ { PCI_CHIP_POLARIS10_67C0, PCI_CHIP_POLARIS10_67C0, RES_SHARED_VGA },
+ { PCI_CHIP_POLARIS10_67DF, PCI_CHIP_POLARIS10_67DF, RES_SHARED_VGA },
  { -1,                 -1,                 RES_UNDEFINED }
 };
diff --git a/src/amdgpu_pci_device_match_gen.h 
b/src/amdgpu_pci_device_match_gen.h
index 5021d99..dd2c0cd 100644
--- a/src/amdgpu_pci_device_match_gen.h
+++ b/src/amdgpu_pci_device_match_gen.h
@@ -85,5 +85,7 @@ static const struct pci_id_match amdgpu_device_match[] = {
  ATI_DEVICE_MATCH( PCI_CHIP_POLARIS11_67E9, 0 ),
  ATI_DEVICE_MATCH( PCI_CHIP_POLARIS11_67EB, 0 ),
  ATI_DEVICE_MATCH( PCI_CHIP_POLARIS11_67FF, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_POLARIS10_67C0, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_POLARIS10_67DF, 0 ),
  { 0, 0, 0 }
 };
diff --git a/src/ati_pciids_gen.h b/src/ati_pciids_gen.h
index 86a8e19..a949118 100644
--- a/src/ati_pciids_gen.h
+++ b/src/ati_pciids_gen.h
@@ -83,3 +83,5 @@
 #define PCI_CHIP_POLARIS11_67E9 0x67E9
 #define PCI_CHIP_POLARIS11_67EB 0x67EB
 #define PCI_CHIP_POLARIS11_67FF 0x67FF
+#define PCI_CHIP_POLARIS10_67C0 0x67C0
+#define PCI_CHIP_POLARIS10_67DF 0x67DF
diff --git a/src/pcidb/ati_pciids.csv b/src/pcidb/ati_pciids.csv
index 55e5cda..7620aa3 100644
--- a/src/pcidb/ati_pciids.csv
+++ b/src/pcidb/ati_pciids.csv
@@ -84,3 +84,5 @@
 "0x67E9","POLARIS11_67E9","POLARIS11","POLARIS11"
 "0x67EB","POLARIS11_67EB","POLARIS11","POLARIS11"
 "0x67FF","POLARIS11_67FF","POLARIS11","POLARIS11"
+"0x67C0","POLARIS10_67C0","POLARIS10","POLARIS10"
+"0x67DF","POLARIS10_67DF","POLARIS10","POLARIS10"

commit 6e09b8deb77f76b9bb7d393cc1ad924ebba62eff
Author: Flora Cui <flora....@amd.com>
Date:   Thu Nov 5 14:16:39 2015 +0800

    add polaris11 pci id
    
    Reviewed-by: Michel Dänzer <michel.daen...@amd.com>
    Signed-off-by: Flora Cui <flora....@amd.com>
    Reviewed-By: Jammy Zhou <jammy.z...@amd.com>
    Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>

diff --git a/src/amdgpu_chipinfo_gen.h b/src/amdgpu_chipinfo_gen.h
index dab8746..df8d717 100644
--- a/src/amdgpu_chipinfo_gen.h
+++ b/src/amdgpu_chipinfo_gen.h
@@ -79,4 +79,10 @@ static AMDGPUCardInfo AMDGPUCards[] = {
  { 0x9877, CHIP_FAMILY_CARRIZO },
  { 0x7300, CHIP_FAMILY_FIJI },
  { 0x98E4, CHIP_FAMILY_STONEY },
+ { 0x67E0, CHIP_FAMILY_POLARIS11 },
+ { 0x67E1, CHIP_FAMILY_POLARIS11 },
+ { 0x67E8, CHIP_FAMILY_POLARIS11 },
+ { 0x67E9, CHIP_FAMILY_POLARIS11 },
+ { 0x67EB, CHIP_FAMILY_POLARIS11 },
+ { 0x67FF, CHIP_FAMILY_POLARIS11 },
 };
diff --git a/src/amdgpu_chipset_gen.h b/src/amdgpu_chipset_gen.h
index a8683e0..fe7c7a8 100644
--- a/src/amdgpu_chipset_gen.h
+++ b/src/amdgpu_chipset_gen.h
@@ -79,5 +79,11 @@ SymTabRec AMDGPUChipsets[] = {
   { PCI_CHIP_CARRIZO_9877, "CARRIZO" },
   { PCI_CHIP_FIJI_7300, "FIJI" },
   { PCI_CHIP_STONEY_98E4, "STONEY" },
+  { PCI_CHIP_POLARIS11_67E0, "POLARIS11" },
+  { PCI_CHIP_POLARIS11_67E1, "POLARIS11" },
+  { PCI_CHIP_POLARIS11_67E8, "POLARIS11" },
+  { PCI_CHIP_POLARIS11_67E9, "POLARIS11" },
+  { PCI_CHIP_POLARIS11_67EB, "POLARIS11" },
+  { PCI_CHIP_POLARIS11_67FF, "POLARIS11" },
   { -1,                 NULL }
 };
diff --git a/src/amdgpu_pci_chipset_gen.h b/src/amdgpu_pci_chipset_gen.h
index fc16b62..3fa9a47 100644
--- a/src/amdgpu_pci_chipset_gen.h
+++ b/src/amdgpu_pci_chipset_gen.h
@@ -79,5 +79,11 @@ static PciChipsets AMDGPUPciChipsets[] = {
  { PCI_CHIP_CARRIZO_9877, PCI_CHIP_CARRIZO_9877, RES_SHARED_VGA },
  { PCI_CHIP_FIJI_7300, PCI_CHIP_FIJI_7300, RES_SHARED_VGA },
  { PCI_CHIP_STONEY_98E4, PCI_CHIP_STONEY_98E4, RES_SHARED_VGA },
+ { PCI_CHIP_POLARIS11_67E0, PCI_CHIP_POLARIS11_67E0, RES_SHARED_VGA },
+ { PCI_CHIP_POLARIS11_67E1, PCI_CHIP_POLARIS11_67E1, RES_SHARED_VGA },
+ { PCI_CHIP_POLARIS11_67E8, PCI_CHIP_POLARIS11_67E8, RES_SHARED_VGA },
+ { PCI_CHIP_POLARIS11_67E9, PCI_CHIP_POLARIS11_67E9, RES_SHARED_VGA },
+ { PCI_CHIP_POLARIS11_67EB, PCI_CHIP_POLARIS11_67EB, RES_SHARED_VGA },
+ { PCI_CHIP_POLARIS11_67FF, PCI_CHIP_POLARIS11_67FF, RES_SHARED_VGA },
  { -1,                 -1,                 RES_UNDEFINED }
 };
diff --git a/src/amdgpu_pci_device_match_gen.h 
b/src/amdgpu_pci_device_match_gen.h
index 1c00759..5021d99 100644
--- a/src/amdgpu_pci_device_match_gen.h
+++ b/src/amdgpu_pci_device_match_gen.h
@@ -79,5 +79,11 @@ static const struct pci_id_match amdgpu_device_match[] = {
  ATI_DEVICE_MATCH( PCI_CHIP_CARRIZO_9877, 0 ),
  ATI_DEVICE_MATCH( PCI_CHIP_FIJI_7300, 0 ),
  ATI_DEVICE_MATCH( PCI_CHIP_STONEY_98E4, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_POLARIS11_67E0, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_POLARIS11_67E1, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_POLARIS11_67E8, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_POLARIS11_67E9, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_POLARIS11_67EB, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_POLARIS11_67FF, 0 ),
  { 0, 0, 0 }
 };
diff --git a/src/ati_pciids_gen.h b/src/ati_pciids_gen.h
index 76d161c..86a8e19 100644
--- a/src/ati_pciids_gen.h
+++ b/src/ati_pciids_gen.h
@@ -77,3 +77,9 @@
 #define PCI_CHIP_CARRIZO_9877 0x9877
 #define PCI_CHIP_FIJI_7300 0x7300
 #define PCI_CHIP_STONEY_98E4 0x98E4
+#define PCI_CHIP_POLARIS11_67E0 0x67E0
+#define PCI_CHIP_POLARIS11_67E1 0x67E1
+#define PCI_CHIP_POLARIS11_67E8 0x67E8
+#define PCI_CHIP_POLARIS11_67E9 0x67E9
+#define PCI_CHIP_POLARIS11_67EB 0x67EB
+#define PCI_CHIP_POLARIS11_67FF 0x67FF
diff --git a/src/pcidb/ati_pciids.csv b/src/pcidb/ati_pciids.csv
index 21de3a9..55e5cda 100644
--- a/src/pcidb/ati_pciids.csv
+++ b/src/pcidb/ati_pciids.csv
@@ -78,3 +78,9 @@
 "0x9877","CARRIZO_9877","CARRIZO","CARRIZO"
 "0x7300","FIJI_7300","FIJI","FIJI"
 "0x98E4","STONEY_98E4","STONEY","STONEY"
+"0x67E0","POLARIS11_67E0","POLARIS11","POLARIS11"
+"0x67E1","POLARIS11_67E1","POLARIS11","POLARIS11"
+"0x67E8","POLARIS11_67E8","POLARIS11","POLARIS11"
+"0x67E9","POLARIS11_67E9","POLARIS11","POLARIS11"
+"0x67EB","POLARIS11_67EB","POLARIS11","POLARIS11"
+"0x67FF","POLARIS11_67FF","POLARIS11","POLARIS11"

commit 7d32c43fff4c8df32cce150223094f793e036cf3
Author: Alex Deucher <alexander.deuc...@amd.com>
Date:   Wed Oct 28 17:28:23 2015 -0400

    add Polaris chip families
    
    Reviewed-by: Michel Dänzer <michel.daen...@amd.com>
    Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>

diff --git a/src/amdgpu_probe.h b/src/amdgpu_probe.h
index 6edd4a1..865c197 100644
--- a/src/amdgpu_probe.h
+++ b/src/amdgpu_probe.h
@@ -67,6 +67,8 @@ typedef enum {
        CHIP_FAMILY_CARRIZO,
        CHIP_FAMILY_FIJI,
        CHIP_FAMILY_STONEY,
+       CHIP_FAMILY_POLARIS10,
+       CHIP_FAMILY_POLARIS11,
        CHIP_FAMILY_LAST
 } AMDGPUChipFamily;
 

commit fbf9ae18cd241b8b78936aa30441e5fbfd9ba1c5
Author: Michel Dänzer <michel.daen...@amd.com>
Date:   Thu Mar 24 19:05:15 2016 +0900

    Require xserver 1.9 or newer
    
    1.9.0 was released in August 2010.
    
    We were already unintentionally relying on things not available in 1.8
    for at least a year, and nobody has complained.
    
    (Ported from radeon commit e592f32f8b5f5873fcc18b10a69dd5e4ccf11073)
    
    Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>

diff --git a/configure.ac b/configure.ac
index 1deab68..58b79c5 100644
--- a/configure.ac
+++ b/configure.ac
@@ -76,7 +76,7 @@ PKG_CHECK_MODULES(LIBDRM_AMDGPU, [libdrm_amdgpu])
 PKG_CHECK_MODULES(GBM, [gbm])
 
 # Obtain compiler/linker options for the driver dependencies
-PKG_CHECK_MODULES(XORG, [xorg-server >= 1.8 xproto fontsproto xf86driproto 
$REQUIRED_MODULES])
+PKG_CHECK_MODULES(XORG, [xorg-server >= 1.9 xproto fontsproto xf86driproto 
$REQUIRED_MODULES])
 PKG_CHECK_MODULES(XEXT, [xextproto >= 7.0.99.1],
                   HAVE_XEXTPROTO_71="yes"; AC_DEFINE(HAVE_XEXTPROTO_71, 1, 
[xextproto 7.1 available]),
                   HAVE_XEXTPROTO_71="no")
diff --git a/src/amdgpu_dri2.c b/src/amdgpu_dri2.c
index de628cd..4478b16 100644
--- a/src/amdgpu_dri2.c
+++ b/src/amdgpu_dri2.c
@@ -71,18 +71,9 @@ struct dri2_window_priv {

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