VERSION | 2
debian/changelog | 8 +
debian/rules | 3
src/gallium/auxiliary/util/u_debug.c | 7 -
src/gallium/drivers/freedreno/a3xx/fd3_emit.c | 19 +++
src/gallium/drivers/freedreno/freedreno_context.h | 2
src/gallium/drivers/freedreno/freedreno_state.c | 4
src/gallium/drivers/nouveau/nv50/nv50_state.c | 10 -
src/gallium/drivers/nouveau/nv50/nv50_state_validate.c | 22 ++++
src/gallium/drivers/nouveau/nv50/nv50_stateobj.h | 2
src/gallium/drivers/nouveau/nv50/nv50_surface.c | 6 +
src/gallium/drivers/nouveau/nvc0/nvc0_surface.c | 1
src/gallium/drivers/r600/r600_asm.c | 2
src/gallium/drivers/r600/r600_pipe.h | 31 +++---
src/gallium/drivers/r600/r600_shader.c | 4
src/gallium/drivers/r600/sb/sb_bc_decoder.cpp | 1
src/gallium/drivers/r600/sb/sb_bc_parser.cpp | 9 +
src/gallium/drivers/r600/sb/sb_sched.cpp | 2
src/gallium/drivers/radeon/r600_query.c | 16 +--
src/gallium/winsys/radeon/drm/radeon_drm_cs.c | 8 -
src/gallium/winsys/radeon/drm/radeon_drm_cs.h | 2
src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 12 --
src/gallium/winsys/radeon/drm/radeon_drm_winsys.h | 1
src/mesa/drivers/dri/i965/brw_draw_upload.c | 30 ++---
src/mesa/drivers/dri/i965/brw_fs.cpp | 4
src/mesa/drivers/dri/i965/brw_misc_state.c | 3
src/mesa/drivers/dri/i965/gen8_draw_upload.c | 71 ++++++++++----
src/mesa/main/get.c | 86 +++++++++++++++++
src/mesa/main/texgetimage.c | 7 +
src/mesa/main/teximage.c | 11 +-
src/mesa/main/texparam.c | 12 ++
src/mesa/main/texstore.c | 2
src/mesa/main/uniform_query.cpp | 21 ++--
src/mesa/main/uniforms.c | 9 -
34 files changed, 314 insertions(+), 116 deletions(-)
New commits:
commit f5d38c5aaa73c33f5b2de1bd2f3ee2c5e0545d56
Author: Timo Aaltonen <tjaal...@debian.org>
Date: Fri Sep 4 17:25:36 2015 +0300
rules: add a missing hunk lost in a merge, oops.
diff --git a/debian/rules b/debian/rules
index 2f0cadd..38f8432 100755
--- a/debian/rules
+++ b/debian/rules
@@ -100,6 +100,9 @@ else
GALLIUM_DRIVERS += radeonsi
confflags_GALLIUM += --enable-gallium-llvm
confflags_GALLIUM += ac_cv_path_LLVM_CONFIG=llvm-config-3.7
+ GALLIUM_DRIVERS += swrast
+ else
+ DRI_DRIVERS += swrast
endif
confflags_DIRECT_RENDERING = --enable-driglx-direct
commit 822902d8dd381e266c677e056b1ea62c71cc7a80
Author: Timo Aaltonen <tjaal...@debian.org>
Date: Wed Sep 2 11:38:49 2015 +0300
release to experimental
diff --git a/debian/changelog b/debian/changelog
index cd40081..9dca1ae 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,3 +1,9 @@
+mesa (11.0.0~rc2-1) experimental; urgency=medium
+
+ * New upstream release candidate.
+
+ -- Timo Aaltonen <tjaal...@debian.org> Wed, 02 Sep 2015 11:38:28 +0300
+
mesa (11.0.0~rc1-1) experimental; urgency=medium
[ Andreas Boll ]
commit 3f8d44210c70f4b16651f1faf5fd72c47c64ab07
Author: Emil Velikov <emil.l.veli...@gmail.com>
Date: Mon Aug 31 13:40:19 2015 +0100
Update version to 11.0.0-rc2
Signed-off-by: Emil Velikov <emil.l.veli...@gmail.com>
diff --git a/VERSION b/VERSION
index 69d3cd2..f25fb60 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-11.0.0-rc1
+11.0.0-rc2
commit 579ca506aefabc018d2cdd1856de4ce0e95bdfcf
Author: Marek Olšák <marek.ol...@amd.com>
Date: Sun Aug 23 12:57:09 2015 +0200
gallium/radeon: fix the ADDRESS_HI mask for EVENT_WRITE CIK packets
Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
(cherry picked from commit 437cb1e3f482570447501526927df4d80c845bf5)
diff --git a/src/gallium/drivers/radeon/r600_query.c
b/src/gallium/drivers/radeon/r600_query.c
index 7057aa1..65339bb 100644
--- a/src/gallium/drivers/radeon/r600_query.c
+++ b/src/gallium/drivers/radeon/r600_query.c
@@ -197,7 +197,7 @@ static void r600_emit_query_begin(struct
r600_common_context *ctx, struct r600_q
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) |
EVENT_INDEX(1));
radeon_emit(cs, va);
- radeon_emit(cs, (va >> 32UL) & 0xFF);
+ radeon_emit(cs, (va >> 32) & 0xFFFF);
break;
case PIPE_QUERY_PRIMITIVES_EMITTED:
case PIPE_QUERY_PRIMITIVES_GENERATED:
@@ -206,13 +206,13 @@ static void r600_emit_query_begin(struct
r600_common_context *ctx, struct r600_q
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
radeon_emit(cs, EVENT_TYPE(event_type_for_stream(query)) |
EVENT_INDEX(3));
radeon_emit(cs, va);
- radeon_emit(cs, (va >> 32UL) & 0xFF);
+ radeon_emit(cs, (va >> 32) & 0xFFFF);
break;
case PIPE_QUERY_TIME_ELAPSED:
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
radeon_emit(cs,
EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
radeon_emit(cs, va);
- radeon_emit(cs, (3 << 29) | ((va >> 32UL) & 0xFF));
+ radeon_emit(cs, (3 << 29) | ((va >> 32) & 0xFFFF));
radeon_emit(cs, 0);
radeon_emit(cs, 0);
break;
@@ -220,7 +220,7 @@ static void r600_emit_query_begin(struct
r600_common_context *ctx, struct r600_q
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SAMPLE_PIPELINESTAT) |
EVENT_INDEX(2));
radeon_emit(cs, va);
- radeon_emit(cs, (va >> 32UL) & 0xFF);
+ radeon_emit(cs, (va >> 32) & 0xFFFF);
break;
default:
assert(0);
@@ -254,7 +254,7 @@ static void r600_emit_query_end(struct r600_common_context
*ctx, struct r600_que
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_ZPASS_DONE) |
EVENT_INDEX(1));
radeon_emit(cs, va);
- radeon_emit(cs, (va >> 32UL) & 0xFF);
+ radeon_emit(cs, (va >> 32) & 0xFFFF);
break;
case PIPE_QUERY_PRIMITIVES_EMITTED:
case PIPE_QUERY_PRIMITIVES_GENERATED:
@@ -264,7 +264,7 @@ static void r600_emit_query_end(struct r600_common_context
*ctx, struct r600_que
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
radeon_emit(cs, EVENT_TYPE(event_type_for_stream(query)) |
EVENT_INDEX(3));
radeon_emit(cs, va);
- radeon_emit(cs, (va >> 32UL) & 0xFF);
+ radeon_emit(cs, (va >> 32) & 0xFFFF);
break;
case PIPE_QUERY_TIME_ELAPSED:
va += query->buffer.results_end + query->result_size/2;
@@ -273,7 +273,7 @@ static void r600_emit_query_end(struct r600_common_context
*ctx, struct r600_que
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
radeon_emit(cs,
EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
radeon_emit(cs, va);
- radeon_emit(cs, (3 << 29) | ((va >> 32UL) & 0xFF));
+ radeon_emit(cs, (3 << 29) | ((va >> 32) & 0xFFFF));
radeon_emit(cs, 0);
radeon_emit(cs, 0);
break;
@@ -282,7 +282,7 @@ static void r600_emit_query_end(struct r600_common_context
*ctx, struct r600_que
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_SAMPLE_PIPELINESTAT) |
EVENT_INDEX(2));
radeon_emit(cs, va);
- radeon_emit(cs, (va >> 32UL) & 0xFF);
+ radeon_emit(cs, (va >> 32) & 0xFFFF);
break;
default:
assert(0);
commit 94205d0aa229d0cbfb9a5f9ed0cbd1cb07ba9d33
Author: Ilia Mirkin <imir...@alum.mit.edu>
Date: Mon Aug 24 23:31:00 2015 -0400
freedreno/a3xx: add basic clip plane support
The hardware is capable of dealing with GL1-style user clip planes.
No clip vertex, no clip distances. Fixes a number of ucp tests, as well
as neverball.
Signed-off-by: Ilia Mirkin <imir...@alum.mit.edu>
Cc: "11.0" <mesa-sta...@lists.freedesktop.org>
(cherry picked from commit 58e24b4761ec8c348bf6825c2355a6e047599306)
diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_emit.c
b/src/gallium/drivers/freedreno/a3xx/fd3_emit.c
index 752e7f8..6f514ed 100644
--- a/src/gallium/drivers/freedreno/a3xx/fd3_emit.c
+++ b/src/gallium/drivers/freedreno/a3xx/fd3_emit.c
@@ -563,10 +563,29 @@ fd3_emit_state(struct fd_context *ctx, struct
fd_ringbuffer *ring,
val |= COND(fp->writes_pos,
A3XX_GRAS_CL_CLIP_CNTL_ZCLIP_DISABLE);
val |= COND(fp->frag_coord, A3XX_GRAS_CL_CLIP_CNTL_ZCOORD |
A3XX_GRAS_CL_CLIP_CNTL_WCOORD);
+ /* TODO only use if prog doesn't use clipvertex/clipdist */
+ val |= MIN2(util_bitcount(ctx->rasterizer->clip_plane_enable),
6) << 26;
OUT_PKT0(ring, REG_A3XX_GRAS_CL_CLIP_CNTL, 1);
OUT_RING(ring, val);
}
+ if (dirty & (FD_DIRTY_RASTERIZER | FD_DIRTY_UCP)) {
+ uint32_t planes = ctx->rasterizer->clip_plane_enable;
+ int count = 0;
+
+ while (planes && count < 6) {
+ int i = ffs(planes) - 1;
+
+ planes &= ~(1U << i);
+ fd_wfi(ctx, ring);
+ OUT_PKT0(ring, REG_A3XX_GRAS_CL_USER_PLANE(count++), 4);
+ OUT_RING(ring, fui(ctx->ucp.ucp[i][0]));
+ OUT_RING(ring, fui(ctx->ucp.ucp[i][1]));
+ OUT_RING(ring, fui(ctx->ucp.ucp[i][2]));
+ OUT_RING(ring, fui(ctx->ucp.ucp[i][3]));
+ }
+ }
+
/* NOTE: since primitive_restart is not actually part of any
* state object, we need to make sure that we always emit
* PRIM_VTX_CNTL.. either that or be more clever and detect
diff --git a/src/gallium/drivers/freedreno/freedreno_context.h
b/src/gallium/drivers/freedreno/freedreno_context.h
index 509a90f..3486c2f 100644
--- a/src/gallium/drivers/freedreno/freedreno_context.h
+++ b/src/gallium/drivers/freedreno/freedreno_context.h
@@ -334,6 +334,7 @@ struct fd_context {
FD_DIRTY_INDEXBUF = (1 << 16),
FD_DIRTY_SCISSOR = (1 << 17),
FD_DIRTY_STREAMOUT = (1 << 18),
+ FD_DIRTY_UCP = (1 << 19),
} dirty;
struct pipe_blend_state *blend;
@@ -355,6 +356,7 @@ struct fd_context {
struct fd_constbuf_stateobj constbuf[PIPE_SHADER_TYPES];
struct pipe_index_buffer indexbuf;
struct fd_streamout_stateobj streamout;
+ struct pipe_clip_state ucp;
/* GMEM/tile handling fxns: */
void (*emit_tile_init)(struct fd_context *ctx);
diff --git a/src/gallium/drivers/freedreno/freedreno_state.c
b/src/gallium/drivers/freedreno/freedreno_state.c
index 7bf8bdb..e75865a 100644
--- a/src/gallium/drivers/freedreno/freedreno_state.c
+++ b/src/gallium/drivers/freedreno/freedreno_state.c
@@ -65,7 +65,9 @@ static void
fd_set_clip_state(struct pipe_context *pctx,
const struct pipe_clip_state *clip)
{
- DBG("TODO: ");
+ struct fd_context *ctx = fd_context(pctx);
+ ctx->ucp = *clip;
+ ctx->dirty |= FD_DIRTY_UCP;
}
static void
commit 1b40221850d41b622e66f7bbea0eed6594b85c4a
Author: Dave Airlie <airl...@redhat.com>
Date: Fri Aug 28 10:46:10 2015 +1000
r600: port si_conv_prim_to_gs_out from radeonsi
This code was broken by the tess merge, and I totally missed it
until now. I'm not sure this fixes anything but it stops the assert.
Cc: "11.0" <mesa-sta...@lists.freedesktop.org>
Reviewed-by: Glenn Kennard <glenn.kenn...@gmail.com>
Signed-off-by: Dave Airlie <airl...@redhat.com>
(cherry picked from commit 6941883175612ae602a8745945153ba064f53a7a)
diff --git a/src/gallium/drivers/r600/r600_pipe.h
b/src/gallium/drivers/r600/r600_pipe.h
index 384ba80..3247aba 100644
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -939,21 +939,22 @@ static inline bool r600_can_read_depth(struct
r600_texture *rtex)
static inline unsigned r600_conv_prim_to_gs_out(unsigned mode)
{
static const int prim_conv[] = {
- V_028A6C_OUTPRIM_TYPE_POINTLIST,
- V_028A6C_OUTPRIM_TYPE_LINESTRIP,
- V_028A6C_OUTPRIM_TYPE_LINESTRIP,
- V_028A6C_OUTPRIM_TYPE_LINESTRIP,
- V_028A6C_OUTPRIM_TYPE_TRISTRIP,
- V_028A6C_OUTPRIM_TYPE_TRISTRIP,
- V_028A6C_OUTPRIM_TYPE_TRISTRIP,
- V_028A6C_OUTPRIM_TYPE_TRISTRIP,
- V_028A6C_OUTPRIM_TYPE_TRISTRIP,
- V_028A6C_OUTPRIM_TYPE_TRISTRIP,
- V_028A6C_OUTPRIM_TYPE_LINESTRIP,
- V_028A6C_OUTPRIM_TYPE_LINESTRIP,
- V_028A6C_OUTPRIM_TYPE_TRISTRIP,
- V_028A6C_OUTPRIM_TYPE_TRISTRIP,
- V_028A6C_OUTPRIM_TYPE_TRISTRIP
+ [PIPE_PRIM_POINTS] =
V_028A6C_OUTPRIM_TYPE_POINTLIST,
+ [PIPE_PRIM_LINES] =
V_028A6C_OUTPRIM_TYPE_LINESTRIP,
+ [PIPE_PRIM_LINE_LOOP] =
V_028A6C_OUTPRIM_TYPE_LINESTRIP,
+ [PIPE_PRIM_LINE_STRIP] =
V_028A6C_OUTPRIM_TYPE_LINESTRIP,
+ [PIPE_PRIM_TRIANGLES] =
V_028A6C_OUTPRIM_TYPE_TRISTRIP,
+ [PIPE_PRIM_TRIANGLE_STRIP] =
V_028A6C_OUTPRIM_TYPE_TRISTRIP,
+ [PIPE_PRIM_TRIANGLE_FAN] =
V_028A6C_OUTPRIM_TYPE_TRISTRIP,
+ [PIPE_PRIM_QUADS] =
V_028A6C_OUTPRIM_TYPE_TRISTRIP,
+ [PIPE_PRIM_QUAD_STRIP] =
V_028A6C_OUTPRIM_TYPE_TRISTRIP,
+ [PIPE_PRIM_POLYGON] =
V_028A6C_OUTPRIM_TYPE_TRISTRIP,
+ [PIPE_PRIM_LINES_ADJACENCY] =
V_028A6C_OUTPRIM_TYPE_LINESTRIP,
+ [PIPE_PRIM_LINE_STRIP_ADJACENCY] =
V_028A6C_OUTPRIM_TYPE_LINESTRIP,
+ [PIPE_PRIM_TRIANGLES_ADJACENCY] =
V_028A6C_OUTPRIM_TYPE_TRISTRIP,
+ [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] =
V_028A6C_OUTPRIM_TYPE_TRISTRIP,
+ [PIPE_PRIM_PATCHES] =
V_028A6C_OUTPRIM_TYPE_POINTLIST,
+ [R600_PRIM_RECTANGLE_LIST] =
V_028A6C_OUTPRIM_TYPE_TRISTRIP
};
assert(mode < Elements(prim_conv));
commit 2fe87a1b68c282846c119bdd930aa936c6504054
Author: Dave Airlie <airl...@redhat.com>
Date: Fri Aug 28 09:57:04 2015 +1000
gallium/util: fix debug_get_flags_option on 32-bit
On 32-bit we need to use PRIu64 flags for printfs,
otherwise this segfaults in R600_DEBUG=help otherwise.
Reviewed-by: Marek Olšák <marek.ol...@amd.com>
Cc: "11.0" <mesa-sta...@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airl...@redhat.com>
(cherry picked from commit 8d6d0cc17d945317f44328a7761801e6781dc3fc)
diff --git a/src/gallium/auxiliary/util/u_debug.c
b/src/gallium/auxiliary/util/u_debug.c
index b4503de..5fe9e33 100644
--- a/src/gallium/auxiliary/util/u_debug.c
+++ b/src/gallium/auxiliary/util/u_debug.c
@@ -41,6 +41,7 @@
#include "util/u_tile.h"
#include "util/u_prim.h"
#include "util/u_surface.h"
+#include <inttypes.h>
#include <stdio.h>
#include <limits.h> /* CHAR_BIT */
@@ -275,7 +276,7 @@ debug_get_flags_option(const char *name,
for (; flags->name; ++flags)
namealign = MAX2(namealign, strlen(flags->name));
for (flags = orig; flags->name; ++flags)
- _debug_printf("| %*s [0x%0*lx]%s%s\n", namealign, flags->name,
+ _debug_printf("| %*s [0x%0*"PRIu64"]%s%s\n", namealign, flags->name,
(int)sizeof(uint64_t)*CHAR_BIT/4, flags->value,
flags->desc ? " " : "", flags->desc ? flags->desc : "");
}
@@ -290,9 +291,9 @@ debug_get_flags_option(const char *name,
if (debug_get_option_should_print()) {
if (str) {
- debug_printf("%s: %s = 0x%lx (%s)\n", __FUNCTION__, name, result,
str);
+ debug_printf("%s: %s = 0x%"PRIu64" (%s)\n", __FUNCTION__, name,
result, str);
} else {
- debug_printf("%s: %s = 0x%lx\n", __FUNCTION__, name, result);
+ debug_printf("%s: %s = 0x%"PRIu64"\n", __FUNCTION__, name, result);
}
}
commit b83b452eea6db023f50611e090f05c5dcafdbc93
Author: Daniel Scharrer <dan...@constexpr.org>
Date: Fri Aug 28 11:45:35 2015 +0200
mesa: add missing queries for ARB_direct_state_access
This adds index queries (glGet*i_v) for GL_TEXTURE_BINDING_* and
GL_SAMPLER_BINDING, as well as textue queries
(glGetTex{,ture}Parameter*) for GL_TEXTURE_TARGET.
CC: "10.6 11.0" <mesa-sta...@lists.freedesktop.org>
Reviewed-by: Fredrik Höglund <fred...@kde.org>
Signed-off-by: Fredrik Höglund <fred...@kde.org>
(cherry picked from commit 5aaaaebf22c920745d577c49e463d23b90ba5ea8)
diff --git a/src/mesa/main/get.c b/src/mesa/main/get.c
index 307a5ff..f524eb2 100644
--- a/src/mesa/main/get.c
+++ b/src/mesa/main/get.c
@@ -35,6 +35,7 @@
#include "mtypes.h"
#include "state.h"
#include "texcompress.h"
+#include "texstate.h"
#include "framebuffer.h"
#include "samplerobj.h"
#include "stencil.h"
@@ -1785,6 +1786,52 @@ _mesa_GetDoublev(GLenum pname, GLdouble *params)
}
}
+/**
+ * Convert a GL texture binding enum such as GL_TEXTURE_BINDING_2D
+ * into the corresponding Mesa texture target index.
+ * \return TEXTURE_x_INDEX or -1 if binding is invalid
+ */
+static int
+tex_binding_to_index(const struct gl_context *ctx, GLenum binding)
+{
+ switch (binding) {
+ case GL_TEXTURE_BINDING_1D:
+ return _mesa_is_desktop_gl(ctx) ? TEXTURE_1D_INDEX : -1;
+ case GL_TEXTURE_BINDING_2D:
+ return TEXTURE_2D_INDEX;
+ case GL_TEXTURE_BINDING_3D:
+ return ctx->API != API_OPENGLES ? TEXTURE_3D_INDEX : -1;
+ case GL_TEXTURE_BINDING_CUBE_MAP:
+ return ctx->Extensions.ARB_texture_cube_map
+ ? TEXTURE_CUBE_INDEX : -1;
+ case GL_TEXTURE_BINDING_RECTANGLE:
+ return _mesa_is_desktop_gl(ctx) && ctx->Extensions.NV_texture_rectangle
+ ? TEXTURE_RECT_INDEX : -1;
+ case GL_TEXTURE_BINDING_1D_ARRAY:
+ return _mesa_is_desktop_gl(ctx) && ctx->Extensions.EXT_texture_array
+ ? TEXTURE_1D_ARRAY_INDEX : -1;
+ case GL_TEXTURE_BINDING_2D_ARRAY:
+ return (_mesa_is_desktop_gl(ctx) && ctx->Extensions.EXT_texture_array)
+ || _mesa_is_gles3(ctx)
+ ? TEXTURE_2D_ARRAY_INDEX : -1;
+ case GL_TEXTURE_BINDING_BUFFER:
+ return ctx->API == API_OPENGL_CORE &&
+ ctx->Extensions.ARB_texture_buffer_object ?
+ TEXTURE_BUFFER_INDEX : -1;
+ case GL_TEXTURE_BINDING_CUBE_MAP_ARRAY:
+ return _mesa_is_desktop_gl(ctx) &&
ctx->Extensions.ARB_texture_cube_map_array
+ ? TEXTURE_CUBE_ARRAY_INDEX : -1;
+ case GL_TEXTURE_BINDING_2D_MULTISAMPLE:
+ return _mesa_is_desktop_gl(ctx) &&
ctx->Extensions.ARB_texture_multisample
+ ? TEXTURE_2D_MULTISAMPLE_INDEX : -1;
+ case GL_TEXTURE_BINDING_2D_MULTISAMPLE_ARRAY:
+ return _mesa_is_desktop_gl(ctx) &&
ctx->Extensions.ARB_texture_multisample
+ ? TEXTURE_2D_MULTISAMPLE_ARRAY_INDEX : -1;
+ default:
+ return -1;
+ }
+}
+
static enum value_type
find_value_indexed(const char *func, GLenum pname, GLuint index, union value
*v)
{
@@ -2048,6 +2095,45 @@ find_value_indexed(const char *func, GLenum pname,
GLuint index, union value *v)
v->value_int = ctx->ImageUnits[index].Format;
return TYPE_INT;
+ /* ARB_direct_state_access */
+ case GL_TEXTURE_BINDING_1D:
+ case GL_TEXTURE_BINDING_1D_ARRAY:
+ case GL_TEXTURE_BINDING_2D:
+ case GL_TEXTURE_BINDING_2D_ARRAY:
+ case GL_TEXTURE_BINDING_2D_MULTISAMPLE:
+ case GL_TEXTURE_BINDING_2D_MULTISAMPLE_ARRAY:
+ case GL_TEXTURE_BINDING_3D:
+ case GL_TEXTURE_BINDING_BUFFER:
+ case GL_TEXTURE_BINDING_CUBE_MAP:
+ case GL_TEXTURE_BINDING_CUBE_MAP_ARRAY:
+ case GL_TEXTURE_BINDING_RECTANGLE: {
+ int target;
+
+ if (ctx->API != API_OPENGL_CORE)
+ goto invalid_enum;
+ target = tex_binding_to_index(ctx, pname);
+ if (target < 0)
+ goto invalid_enum;
+ if (index >= _mesa_max_tex_unit(ctx))
+ goto invalid_value;
+
+ v->value_int = ctx->Texture.Unit[index].CurrentTex[target]->Name;
+ return TYPE_INT;
+ }
+
+ case GL_SAMPLER_BINDING: {
+ struct gl_sampler_object *samp;
+
+ if (ctx->API != API_OPENGL_CORE)
+ goto invalid_enum;
+ if (index >= _mesa_max_tex_unit(ctx))
+ goto invalid_value;
+
+ samp = ctx->Texture.Unit[index].Sampler;
+ v->value_int = samp ? samp->Name : 0;
+ return TYPE_INT;
+ }
+
case GL_MAX_COMPUTE_WORK_GROUP_COUNT:
if (!_mesa_is_desktop_gl(ctx) || !ctx->Extensions.ARB_compute_shader)
goto invalid_enum;
diff --git a/src/mesa/main/texparam.c b/src/mesa/main/texparam.c
index 16739f1..68c6e58 100644
--- a/src/mesa/main/texparam.c
+++ b/src/mesa/main/texparam.c
@@ -1914,6 +1914,12 @@ get_tex_parameterfv(struct gl_context *ctx,
*params = (GLfloat) obj->ImageFormatCompatibilityType;
break;
+ case GL_TEXTURE_TARGET:
+ if (ctx->API != API_OPENGL_CORE)
+ goto invalid_pname;
+ *params = ENUM_TO_FLOAT(obj->Target);
+ break;
+
default:
goto invalid_pname;
}
@@ -2139,6 +2145,12 @@ get_tex_parameteriv(struct gl_context *ctx,
*params = obj->ImageFormatCompatibilityType;
break;
+ case GL_TEXTURE_TARGET:
+ if (ctx->API != API_OPENGL_CORE)
+ goto invalid_pname;
+ *params = (GLint) obj->Target;
+ break;
+
default:
goto invalid_pname;
}
commit 68bd2ddda026afd5e45324d51a5b6b74227c5408
Author: Glenn Kennard <glenn.kenn...@gmail.com>
Date: Thu Aug 27 19:04:17 2015 +0200
r600g/sb: Don't crash on empty if jump target
Signed-off-by: Glenn Kennard <glenn.kenn...@gmail.com>
Cc: <mesa-sta...@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airl...@redhat.com>
(cherry picked from commit 608c7b4a63d5818f7ae0b3d48496b02cf8458d9b)
diff --git a/src/gallium/drivers/r600/sb/sb_bc_parser.cpp
b/src/gallium/drivers/r600/sb/sb_bc_parser.cpp
index 748aae2..c479927 100644
--- a/src/gallium/drivers/r600/sb/sb_bc_parser.cpp
+++ b/src/gallium/drivers/r600/sb/sb_bc_parser.cpp
@@ -792,6 +792,9 @@ int bc_parser::prepare_if(cf_node* c) {
assert(c->bc.addr-1 < cf_map.size());
cf_node *c_else = NULL, *end = cf_map[c->bc.addr];
+ if (!end)
+ return 0; // not quite sure how this happens, malformed input?
+
BCP_DUMP(
sblog << "parsing JUMP @" << c->bc.id;
sblog << "\n";
@@ -817,7 +820,7 @@ int bc_parser::prepare_if(cf_node* c) {
if (c_else->parent != c->parent)
c_else = NULL;
- if (end->parent != c->parent)
+ if (end && end->parent != c->parent)
end = NULL;
region_node *reg = sh->create_region();
commit 9db5c2ca2ea8f4172611337db1cc81f19aab443e
Author: Glenn Kennard <glenn.kenn...@gmail.com>
Date: Thu Aug 27 19:04:16 2015 +0200
r600g/sb: Don't read junk after EOP
Shaders that contain instruction data after an instruction with EOP could
end
up parsing that as an instruction, leading to various crashes and asserts in
SB as it gets very confused if it sees for instance a loop start instruction
jumping off to some random point.
Add a couple of asserts, and print EOP bit if set in old asm printer.
Signed-off-by: Glenn Kennard <glenn.kenn...@gmail.com>
Cc: <mesa-sta...@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airl...@redhat.com>
(cherry picked from commit a830225adbb77073272961df409885cca6b861ee)
diff --git a/src/gallium/drivers/r600/r600_asm.c
b/src/gallium/drivers/r600/r600_asm.c
index 762cc7f..b514c58 100644
--- a/src/gallium/drivers/r600/r600_asm.c
+++ b/src/gallium/drivers/r600/r600_asm.c
@@ -2029,6 +2029,8 @@ void r600_bytecode_disasm(struct r600_bytecode *bc)
fprintf(stderr, "CND:%X ", cf->cond);
if (cf->pop_count)
fprintf(stderr, "POP:%X ",
cf->pop_count);
+ if (cf->end_of_program)
+ fprintf(stderr, "EOP ");
fprintf(stderr, "\n");
}
}
diff --git a/src/gallium/drivers/r600/sb/sb_bc_decoder.cpp
b/src/gallium/drivers/r600/sb/sb_bc_decoder.cpp
index 5e233f9..5fe8f50 100644
--- a/src/gallium/drivers/r600/sb/sb_bc_decoder.cpp
+++ b/src/gallium/drivers/r600/sb/sb_bc_decoder.cpp
@@ -32,6 +32,7 @@ int bc_decoder::decode_cf(unsigned &i, bc_cf& bc) {
int r = 0;
uint32_t dw0 = dw[i];
uint32_t dw1 = dw[i+1];
+ assert(i+1 <= ndw);
if ((dw1 >> 29) & 1) { // CF_ALU
return decode_cf_alu(i, bc);
diff --git a/src/gallium/drivers/r600/sb/sb_bc_parser.cpp
b/src/gallium/drivers/r600/sb/sb_bc_parser.cpp
index 4879c03..748aae2 100644
--- a/src/gallium/drivers/r600/sb/sb_bc_parser.cpp
+++ b/src/gallium/drivers/r600/sb/sb_bc_parser.cpp
@@ -95,7 +95,7 @@ int bc_parser::decode_shader() {
if ((r = decode_cf(i, eop)))
return r;
- } while (!eop || (i >> 1) <= max_cf);
+ } while (!eop || (i >> 1) < max_cf);
return 0;
}
@@ -769,6 +769,7 @@ int bc_parser::prepare_ir() {
}
int bc_parser::prepare_loop(cf_node* c) {
+ assert(c->bc.addr-1 < cf_map.size());
cf_node *end = cf_map[c->bc.addr - 1];
assert(end->bc.op == CF_OP_LOOP_END);
@@ -788,6 +789,7 @@ int bc_parser::prepare_loop(cf_node* c) {
}
int bc_parser::prepare_if(cf_node* c) {
+ assert(c->bc.addr-1 < cf_map.size());
cf_node *c_else = NULL, *end = cf_map[c->bc.addr];
BCP_DUMP(
commit 08c41221d7102106d0b70a6399e2270919458077
Author: Glenn Kennard <glenn.kenn...@gmail.com>
Date: Thu Aug 27 19:04:15 2015 +0200
r600g/sb: Handle undef in read port tracker
e8e443 missed adding check for undef values also in
unreserve function, leading to an assert triggering.
Signed-off-by: Glenn Kennard <glenn.kenn...@gmail.com>
Cc: <mesa-sta...@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airl...@redhat.com>
(cherry picked from commit 36f1999a87258603b6720d55e6020d5d24c215c9)
diff --git a/src/gallium/drivers/r600/sb/sb_sched.cpp
b/src/gallium/drivers/r600/sb/sb_sched.cpp
index 6268078..c98b8ff 100644
--- a/src/gallium/drivers/r600/sb/sb_sched.cpp
+++ b/src/gallium/drivers/r600/sb/sb_sched.cpp
@@ -236,7 +236,7 @@ void rp_gpr_tracker::unreserve(alu_node* n) {
for (i = 0; i < nsrc; ++i) {
value *v = n->src[i];
- if (v->is_readonly())
+ if (v->is_readonly() || v->is_undef())
continue;
if (i == 1 && opt)
continue;
commit 896ef5cb95557fbf68c75600d2bcbb01f8933b98
Author: Ilia Mirkin <imir...@alum.mit.edu>
Date: Thu Aug 27 15:28:24 2015 -0400
mesa: only copy the requested teximage faces
Cube maps are special in that they have separate teximages for each
face. We handled that by copying the data to them separately, but in
case zoffset != 0 or depth != 6 we would read off the end of the client
array or modify the wrong images.
zoffset/depth have already been verified by the time the code gets to
this stage, so no need to double-check.
Signed-off-by: Ilia Mirkin <imir...@alum.mit.edu>
Reviewed-by: Brian Paul <bri...@vmware.com>
Cc: "10.6 11.0" <mesa-sta...@lists.freedesktop.org>
(cherry picked from commit 2259b111003f2e8c55cae42677ec45345fb1b6e3)
diff --git a/src/mesa/main/teximage.c b/src/mesa/main/teximage.c
index 6a5489e..3ee33fb 100644
--- a/src/mesa/main/teximage.c
+++ b/src/mesa/main/teximage.c
@@ -3711,12 +3711,12 @@ texturesubimage(struct gl_context *ctx, GLuint dims,
rowStride = _mesa_image_image_stride(&ctx->Unpack, width, height,
format, type);
/* Copy in each face. */
- for (i = 0; i < 6; ++i) {
+ for (i = zoffset; i < zoffset + depth; ++i) {
texImage = texObj->Image[i][level];
assert(texImage);
_mesa_texture_sub_image(ctx, 3, texObj, texImage, texObj->Target,
- level, xoffset, yoffset, zoffset,
+ level, xoffset, yoffset, 0,
width, height, 1, format,
type, pixels, true);
pixels = (GLubyte *) pixels + rowStride;
commit 594388e5776312c1bdc9d5613369ed530bb7fbbc
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Wed Aug 19 14:29:53 2015 -0700
i965/fs: Split VGRFs after lowering pull constants
The split_virtual_grfs code doesn't properly rewrite reladdr so we need to
make sure that any uniform indirects are lowered away first.
This fixes the glsl-fs-uniform-indexed-by-swizzled-vec4.shader_test in
piglit
Cc: "10.6" <mesa-sta...@lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
(cherry picked from commit fee0c5af11dd0995de96e7053377d425a66d03a0)
Conflicts:
src/mesa/drivers/dri/i965/brw_fs.cpp
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 82cb499..055ef55 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -4801,12 +4801,12 @@ fs_visitor::optimize()
*/
bld = fs_builder(this, 64);
- split_virtual_grfs();
-
move_uniform_array_access_to_pull_constants();
assign_constant_locations();
demote_pull_constants();
+ split_virtual_grfs();
+
#define OPT(pass, args...) ({ \
pass_num++; \
bool this_progress = pass(args); \
commit 812f2855dd601e23a4f813f53547d446ca484df7
Author: Marek Olšák <marek.ol...@amd.com>
Date: Mon Aug 24 00:22:37 2015 +0200
mesa: create multisample fallback textures like normal textures
This works if drivers upsample on upload (like all radeon ones do).
The alternative is an unexpected GL error from anything calling
_mesa_update_state and possibly other issues.
Cc: 10.6 11.0 <mesa-sta...@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airl...@redhat.com>
(cherry picked from commit f432ae899fb81468778dbeb17ac7615da3ed5c0d)
diff --git a/src/mesa/main/texstore.c b/src/mesa/main/texstore.c
index 37c0569..7774664 100644
--- a/src/mesa/main/texstore.c
+++ b/src/mesa/main/texstore.c
@@ -1004,6 +1004,7 @@ store_texsubimage(struct gl_context *ctx,
/* compute slice info (and do some sanity checks) */
switch (target) {
case GL_TEXTURE_2D:
+ case GL_TEXTURE_2D_MULTISAMPLE:
case GL_TEXTURE_RECTANGLE:
case GL_TEXTURE_CUBE_MAP:
case GL_TEXTURE_EXTERNAL_OES:
@@ -1025,6 +1026,7 @@ store_texsubimage(struct gl_context *ctx,
srcImageStride = _mesa_image_row_stride(packing, width, format, type);
break;
case GL_TEXTURE_2D_ARRAY:
+ case GL_TEXTURE_2D_MULTISAMPLE_ARRAY:
numSlices = depth;
sliceOffset = zoffset;
depth = 1;
commit 5d8ce45d9031e9949dfbab27ab4d608853b86d72
Author: Dave Airlie <airl...@redhat.com>
Date: Mon Aug 24 09:52:12 2015 +1000
mesa/texgetimage: fix missing stencil check
GetTexImage can read to stencil8 but only from
a stencil or depthstencil textures.
This fixes a bunch of failures in CTS
GL33-CTS.gtf32.GL3Tests.packed_pixels
Reviewed-by: Marek Olšák <marek.ol...@amd.com>
Cc: "11.0" <mesa-sta...@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airl...@redhat.com>
(cherry picked from commit c1452983b44cc8ee238b8c7e2cfca1105c707487)
diff --git a/src/mesa/main/texgetimage.c b/src/mesa/main/texgetimage.c
index c0ccce3..56f5de1 100644
--- a/src/mesa/main/texgetimage.c
+++ b/src/mesa/main/texgetimage.c
@@ -1213,6 +1213,13 @@ getteximage_error_check(struct gl_context *ctx,
"%s(format=GL_STENCIL_INDEX)", caller);
return true;
}
+ else if (_mesa_is_stencil_format(format)
+ && !_mesa_is_depthstencil_format(baseFormat)
+ && !_mesa_is_stencil_format(baseFormat)) {
+ _mesa_error(ctx, GL_INVALID_OPERATION,
+ "%s(format mismatch)", caller);
+ return true;
+ }
else if (_mesa_is_ycbcr_format(format)
&& !_mesa_is_ycbcr_format(baseFormat)) {
_mesa_error(ctx, GL_INVALID_OPERATION,
commit 33b0f6e5e181c52c3eeb7ba4cb3bc0db13f10670
Author: Dave Airlie <airl...@redhat.com>
Date: Wed Jul 29 18:09:44 2015 +1000
mesa: enable texture stencil8 for multisample
This fixes GL45-CTS.gtf44.GL31Tests.texture_stencil8.texture_stencil8_gl44
from the ogl conform suite.
Reviewed-by: Ilia Mirkin <imir...@alum.mit.edu>
Cc: 10.6 11.0 <mesa-sta...@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airl...@redhat.com>
(cherry picked from commit 529acab22a3e21e0ed0c5243675aec6c0ee27e8f)
diff --git a/src/mesa/main/teximage.c b/src/mesa/main/teximage.c
index 253e881..6a5489e 100644
--- a/src/mesa/main/teximage.c
+++ b/src/mesa/main/teximage.c
@@ -5569,10 +5569,13 @@ static GLboolean
is_renderable_texture_format(struct gl_context *ctx, GLenum internalformat)
{
/* Everything that is allowed for renderbuffers,
- * except for a base format of GL_STENCIL_INDEX.
+ * except for a base format of GL_STENCIL_INDEX, unless supported.
*/
GLenum baseFormat = _mesa_base_fbo_format(ctx, internalformat);
- return baseFormat != 0 && baseFormat != GL_STENCIL_INDEX;
+ if (ctx->Extensions.ARB_texture_stencil8)
+ return baseFormat != 0;
+ else
+ return baseFormat != 0 && baseFormat != GL_STENCIL_INDEX;
}
commit 6659fba2c0ea9a5c358e3ef3770585381e619d39
Author: Chris Wilson <ch...@chris-wilson.co.uk>
Date: Sun Aug 23 09:24:57 2015 +0100
i965: Always re-emit the pipeline select during invariant state emission
On the older platforms where we don't have logical contexts preserving
state across batches, we emit the invariant state setup on every batch
using the brw_invariant_state atom. This includes the pipeline selection
which is cached with the introduction of
commit 0e0e23ef537c9add672ff322f34e129a07edc55e
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Wed Apr 22 11:43:50 2015 -0700
i965/state: Emit pipeline select when changing pipelines
However, we do not reset the cache between batches on context-less
platforms resulting in us not setting the pipeline selection and can
cause GPU hangs if a media pipelined was loaded in the meantime (e.g.
mixing mplayer/gstreamer using libva and gnome-shell). A simple solution
is to just forcibly re-emit the pipeline select along with the invariant
state and reset the cache at that point.
Reported-and-tested-by: Tomasz C. <toma...@o2.pl>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91254
Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Jordan Justen <jordan.l.jus...@intel.com>
Cc: Kenneth Graunke <kenn...@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.jus...@intel.com>
Cc: "10.6 11.0" <mesa-sta...@lists.freedesktop.org>
(cherry picked from commit 4e5752e2b78243a71766538f62ca0a80488047a7)
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c
b/src/mesa/drivers/dri/i965/brw_misc_state.c
index e9d9467..2751152 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -878,7 +878,8 @@ brw_upload_invariant_state(struct brw_context *brw)
{
const bool is_965 = brw->gen == 4 && !brw->is_g4x;
- brw_select_pipeline(brw, BRW_RENDER_PIPELINE);
+ brw_emit_select_pipeline(brw, BRW_RENDER_PIPELINE);
+ brw->last_pipeline = BRW_RENDER_PIPELINE;
if (brw->gen < 6) {
/* Disable depth offset clamping. */
commit adae777f24fd84d3a0c074c5f2c01a31d9f63cce
Author: Marek Olšák <marek.ol...@amd.com>
Date: Sun Aug 23 18:57:44 2015 +0200
Revert "radeon/winsys: increase the IB size for VM"
This reverts commit 567394112d904096abff1d994ab952f475dfb444.
It regressed performance. It looks like smaller IBs are better, because
the GPU goes idle quicker and there is less waiting for buffers and fences.
Cc: 11.0 <mesa-sta...@lists.freedesktop.org>
(cherry picked from commit a83c36b5c0c64c717ced76db89bab900006648aa)
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
index 7a267f9..f04a696 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
@@ -97,22 +97,17 @@ static boolean radeon_init_cs_context(struct
radeon_cs_context *csc,
{
int i;
- csc->buf = MALLOC(ws->ib_max_size);
- if (!csc->buf)
- return FALSE;
csc->fd = ws->fd;
csc->nrelocs = 512;
csc->relocs_bo = (struct radeon_bo**)
CALLOC(1, csc->nrelocs * sizeof(struct radeon_bo*));
if (!csc->relocs_bo) {
- FREE(csc->buf);
return FALSE;
}
csc->relocs = (struct drm_radeon_cs_reloc*)
CALLOC(1, csc->nrelocs * sizeof(struct drm_radeon_cs_reloc));
if (!csc->relocs) {
- FREE(csc->buf);
FREE(csc->relocs_bo);
return FALSE;
}
@@ -165,7 +160,6 @@ static void radeon_destroy_cs_context(struct
radeon_cs_context *csc)
radeon_cs_context_cleanup(csc);
FREE(csc->relocs_bo);
FREE(csc->relocs);
- FREE(csc->buf);
}
@@ -206,7 +200,7 @@ radeon_drm_cs_create(struct radeon_winsys_ctx *ctx,
cs->cst = &cs->csc2;
cs->base.buf = cs->csc->buf;
cs->base.ring_type = ring_type;
- cs->base.max_dw = ws->ib_max_size / 4;
+ cs->base.max_dw = ARRAY_SIZE(cs->csc->buf);
p_atomic_inc(&ws->num_cs);
return &cs->base;
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_cs.h
b/src/gallium/winsys/radeon/drm/radeon_drm_cs.h
index ab15494..6ceb8e9 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_cs.h
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_cs.h
@@ -30,7 +30,7 @@
#include "radeon_drm_bo.h"
struct radeon_cs_context {
- uint32_t *buf;
+ uint32_t buf[16 * 1024];
int fd;
struct drm_radeon_cs cs;
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index b70bbaa..f7784fb 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -395,20 +395,16 @@ static boolean do_winsys_init(struct radeon_drm_winsys
*ws)
}
ws->info.r600_virtual_address = FALSE;
- ws->ib_max_size = 64 * 1024;
-
if (ws->info.drm_minor >= 13) {
+ uint32_t ib_vm_max_size;
+
ws->info.r600_virtual_address = TRUE;
if (!radeon_get_drm_value(ws->fd, RADEON_INFO_VA_START, NULL,
&ws->va_start))
ws->info.r600_virtual_address = FALSE;
-
- if (radeon_get_drm_value(ws->fd, RADEON_INFO_IB_VM_MAX_SIZE, NULL,
- &ws->ib_max_size))
- ws->ib_max_size *= 4; /* the kernel returns the size in dwords
*/
- else
+ if (!radeon_get_drm_value(ws->fd, RADEON_INFO_IB_VM_MAX_SIZE, NULL,
+ &ib_vm_max_size))
ws->info.r600_virtual_address = FALSE;
-
radeon_get_drm_value(ws->fd, RADEON_INFO_VA_UNMAP_WORKING, NULL,
&ws->va_unmap_working);
}
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
index c1a8d6a..308b5bd 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
@@ -73,7 +73,6 @@ struct radeon_drm_winsys {
