debian/changelog | 11 +
debian/patches/i965-add-cherryview-support.diff | 62 ++++++++
debian/patches/i965-drop-bogus-instructions-use-mov.diff | 69
++++++++++
debian/patches/i965-initialize-more-device-info-fields-chv.diff | 26 +++
debian/patches/i965-store-absolute-thread-count.diff | 51 +++++++
debian/patches/i965-use-mov-not-or-for-setting-urb.diff | 34 ++++
debian/patches/series | 5
7 files changed, 258 insertions(+)
New commits:
commit 7265bd33b633efa3faa12c48bc1756e3a61103ab
Author: Timo Aaltonen <tjaal...@debian.org>
Date: Fri Dec 19 14:48:38 2014 +0200
release to trusty
diff --git a/debian/changelog b/debian/changelog
index 6b8a72e..da7c98a 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,4 +1,4 @@
-mesa (10.1.3-0ubuntu0.3) UNRELEASED; urgency=medium
+mesa (10.1.3-0ubuntu0.3) trusty; urgency=medium
* Backport Braswell support (LP: #1404217)
- i965-add-cherryview-support.diff
@@ -7,7 +7,7 @@ mesa (10.1.3-0ubuntu0.3) UNRELEASED; urgency=medium
- i965-store-absolute-thread-count.diff
- i965-use-mov-not-or-for-setting-urb.diff
- -- Timo Aaltonen <tjaal...@debian.org> Thu, 18 Dec 2014 07:22:35 +0200
+ -- Timo Aaltonen <tjaal...@debian.org> Fri, 19 Dec 2014 14:47:21 +0200
mesa (10.1.3-0ubuntu0.2) trusty; urgency=medium
commit c64c68cc132a32f62791321d8fe886a03b9bc99f
Author: Timo Aaltonen <tjaal...@debian.org>
Date: Fri Dec 19 14:44:12 2014 +0200
backport support for braswell
diff --git a/debian/changelog b/debian/changelog
index fec4ee1..6b8a72e 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,3 +1,14 @@
+mesa (10.1.3-0ubuntu0.3) UNRELEASED; urgency=medium
+
+ * Backport Braswell support (LP: #1404217)
+ - i965-add-cherryview-support.diff
+ - i965-drop-bogus-instructions-use-mov.diff
+ - i965-initialize-more-device-info-fields-chv.diff
+ - i965-store-absolute-thread-count.diff
+ - i965-use-mov-not-or-for-setting-urb.diff
+
+ -- Timo Aaltonen <tjaal...@debian.org> Thu, 18 Dec 2014 07:22:35 +0200
+
mesa (10.1.3-0ubuntu0.2) trusty; urgency=medium
[ Timo Aaltonen ]
diff --git a/debian/patches/i965-add-cherryview-support.diff
b/debian/patches/i965-add-cherryview-support.diff
new file mode 100644
index 0000000..b85f13c
--- /dev/null
+++ b/debian/patches/i965-add-cherryview-support.diff
@@ -0,0 +1,62 @@
+commit 9b6b084eb7b10d006b44e3cd22585fc3e39e0c00
+Author: Kenneth Graunke <kenn...@whitecape.org>
+Date: Tue Feb 18 16:39:11 2014 -0800
+
+ i965: Add Cherryview support.
+
+ Based on a patch by Ville Syrjälä.
+
+ As usual, these are placeholder values; actual values will come later.
+
+ Signed-off-by: Kenneth Graunke <kenn...@whitecape.org>
+
+diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h
+index a71f6d4..cf0c904 100644
+--- a/include/pci_ids/i965_pci_ids.h
++++ b/include/pci_ids/i965_pci_ids.h
+@@ -109,3 +109,7 @@ CHIPSET(0x162A, bdw_gt3, "Intel(R) Broadwell")
+ CHIPSET(0x162B, bdw_gt3, "Intel(R) Broadwell")
+ CHIPSET(0x162D, bdw_gt3, "Intel(R) Broadwell")
+ CHIPSET(0x162E, bdw_gt3, "Intel(R) Broadwell")
++CHIPSET(0x22B0, chv, "Intel(R) Cherryview")
++CHIPSET(0x22B1, chv, "Intel(R) Cherryview")
++CHIPSET(0x22B2, chv, "Intel(R) Cherryview")
++CHIPSET(0x22B3, chv, "Intel(R) Cherryview")
+diff --git a/src/mesa/drivers/dri/i965/brw_device_info.c
b/src/mesa/drivers/dri/i965/brw_device_info.c
+index e4c110d..1fc8ef4 100644
+--- a/src/mesa/drivers/dri/i965/brw_device_info.c
++++ b/src/mesa/drivers/dri/i965/brw_device_info.c
+@@ -221,6 +221,21 @@ static const struct brw_device_info
brw_device_info_bdw_gt3 = {
+ GEN8_FEATURES, .gt = 3,
+ };
+
++/* Thread counts and URB limits are placeholders, and may not be accurate.
++ * These were copied from Haswell GT1, above.
++ */
++static const struct brw_device_info brw_device_info_chv = {
++ GEN8_FEATURES, .is_cherryview = 1, .gt = 1,
++ .has_llc = false,
++ .max_vs_threads = 70,
++ .max_gs_threads = 70,
++ .max_wm_threads = 102,
++ .urb = {
++ .max_vs_entries = 640,
++ .max_gs_entries = 256,
++ }
++};
++
+ const struct brw_device_info *
+ brw_get_device_info(int devid)
+ {
+diff --git a/src/mesa/drivers/dri/i965/brw_device_info.h
b/src/mesa/drivers/dri/i965/brw_device_info.h
+index 66ec935..e506beb 100644
+--- a/src/mesa/drivers/dri/i965/brw_device_info.h
++++ b/src/mesa/drivers/dri/i965/brw_device_info.h
+@@ -34,6 +34,7 @@ struct brw_device_info
+ bool is_ivybridge;
+ bool is_baytrail;
+ bool is_haswell;
++ bool is_cherryview;
+
+ bool has_hiz_and_separate_stencil;
+ bool must_use_separate_stencil;
diff --git a/debian/patches/i965-drop-bogus-instructions-use-mov.diff
b/debian/patches/i965-drop-bogus-instructions-use-mov.diff
new file mode 100644
index 0000000..7d90c93
--- /dev/null
+++ b/debian/patches/i965-drop-bogus-instructions-use-mov.diff
@@ -0,0 +1,69 @@
+commit 850e372fc7ff3377d7ffdf825d5ebcdd72beee1b
+Author: Kenneth Graunke <kenn...@whitecape.org>
+Date: Wed Jan 29 14:16:27 2014 -0800
+
+ i965: Drop bogus F32TO16/F16TO32 instructions on Broadwell - use MOV.
+
+ Broadwell removed the F32TO16 and F16TO32 instructions. However, it has
+ actual support for HF values, so they're actually just MOV.
+
+ Fixes vs-packHalf2x16 and vs-unpackHalf2x16 tests (both the ARB
+ extension and ES 3.0 variants).
+
+ v2: Emulate F32TO16's align16 zeroing bug, since Chad's front end code
+ relies on it happening. We can probably refactor this code to be
+ better later.
+
+ Signed-off-by: Kenneth Graunke <kenn...@whitecape.org>
+ Reviewed-by: Eric Anholt <e...@anholt.net>
+
+diff --git a/src/mesa/drivers/dri/i965/gen8_fs_generator.cpp
b/src/mesa/drivers/dri/i965/gen8_fs_generator.cpp
+index e5fa3d2..0e1214d 100644
+--- a/src/mesa/drivers/dri/i965/gen8_fs_generator.cpp
++++ b/src/mesa/drivers/dri/i965/gen8_fs_generator.cpp
+@@ -920,10 +920,10 @@ gen8_fs_generator::generate_code(exec_list *instructions)
+ break;
+
+ case BRW_OPCODE_F32TO16:
+- F32TO16(dst, src[0]);
++ MOV(retype(dst, BRW_REGISTER_TYPE_HF), src[0]);
+ break;
+ case BRW_OPCODE_F16TO32:
+- F16TO32(dst, src[0]);
++ MOV(dst, retype(src[0], BRW_REGISTER_TYPE_HF));
+ break;
+
+ case BRW_OPCODE_CMP:
+diff --git a/src/mesa/drivers/dri/i965/gen8_generator.cpp
b/src/mesa/drivers/dri/i965/gen8_generator.cpp
+index 1e2ac09..ca38af6 100644
+--- a/src/mesa/drivers/dri/i965/gen8_generator.cpp
++++ b/src/mesa/drivers/dri/i965/gen8_generator.cpp
+@@ -154,8 +154,6 @@ ALU2(ASR)
+ ALU3(BFE)
+ ALU2(BFI1)
+ ALU3(BFI2)
+-ALU1(F32TO16)
+-ALU1(F16TO32)
+ ALU1(BFREV)
+ ALU1(CBIT)
+ ALU2_ACCUMULATE(ADDC)
+diff --git a/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp
b/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp
+index 7ed5d2a..7f6b209 100644
+--- a/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp
++++ b/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp
+@@ -586,11 +586,13 @@
gen8_vec4_generator::generate_vec4_instruction(vec4_instruction *instruction,
+ break;
+
+ case BRW_OPCODE_F32TO16:
+- F32TO16(dst, src[0]);
++ /* Emulate the Gen7 zeroing bug. */
++ MOV(retype(dst, BRW_REGISTER_TYPE_UD), brw_imm_ud(0u));
++ MOV(retype(dst, BRW_REGISTER_TYPE_HF), src[0]);
+ break;
+
+ case BRW_OPCODE_F16TO32:
+- F16TO32(dst, src[0]);
++ MOV(dst, retype(src[0], BRW_REGISTER_TYPE_HF));
+ break;
+
+ case BRW_OPCODE_LRP:
diff --git a/debian/patches/i965-initialize-more-device-info-fields-chv.diff
b/debian/patches/i965-initialize-more-device-info-fields-chv.diff
new file mode 100644
index 0000000..386cae5
--- /dev/null
+++ b/debian/patches/i965-initialize-more-device-info-fields-chv.diff
@@ -0,0 +1,26 @@
+commit 70285f607ce2a0680c3e51b3717fed6a8dd19e72
+Author: Jordan Justen <jordan.l.jus...@intel.com>
+Date: Thu Apr 3 11:30:41 2014 -0700
+
+ i965: initialize more device info fields for Cherryview
+
+ The intent in 9b6b084eb7b10d006b44e3cd22585fc3e39e0c00 was
+ for urb .size and .min_vs_entries fields to use the values
+ from the GEN8_FEATURES macro.
+
+ Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
+ Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
+
+diff --git a/src/mesa/drivers/dri/i965/brw_device_info.c
b/src/mesa/drivers/dri/i965/brw_device_info.c
+index 7625c74..bf3c62e 100644
+--- a/src/mesa/drivers/dri/i965/brw_device_info.c
++++ b/src/mesa/drivers/dri/i965/brw_device_info.c
+@@ -231,6 +231,8 @@ static const struct brw_device_info brw_device_info_chv = {
+ .max_gs_threads = 70,
+ .max_wm_threads = 102,
+ .urb = {
++ .size = 128,
++ .min_vs_entries = 64,
+ .max_vs_entries = 640,
+ .max_gs_entries = 256,
+ }
diff --git a/debian/patches/i965-store-absolute-thread-count.diff
b/debian/patches/i965-store-absolute-thread-count.diff
new file mode 100644
index 0000000..c5c6679
--- /dev/null
+++ b/debian/patches/i965-store-absolute-thread-count.diff
@@ -0,0 +1,51 @@
+commit a5e54c91a3b73551609efea1f6f31eaae26281ea
+Author: Kenneth Graunke <kenn...@whitecape.org>
+Date: Tue Feb 4 22:18:03 2014 -0800
+
+ i965: Store absolute thread count in max_wm_threads on Broadwell.
+
+ In the past, 3DSTATE_PS took an absolute number of threads. Conversely,
+ on Broadwell you always program 64, and it implicitly scales based on
+ the GT-level with no special programming. So, I stored 64 in
+ brw_device_info::max_wm_threads.
+
+ However, I didn't realize that we also use max_wm_threads to compute the
+ size of the scratch space buffer. In that case, we really need the
+ absolute number of threads.
+
+ This patch hardcodes 3DSTATE_PS to use the value it expects, and changes
+ max_wm_threads back to a (completely fake) absolute thread count (once
+ again copied from Haswell).
+
+ Signed-off-by: Kenneth Graunke <kenn...@whitecape.org>
+ Reviewed-by: Eric Anholt <e...@anholt.net>
+
+diff --git a/src/mesa/drivers/dri/i965/brw_device_info.c
b/src/mesa/drivers/dri/i965/brw_device_info.c
+index d931091..e4c110d 100644
+--- a/src/mesa/drivers/dri/i965/brw_device_info.c
++++ b/src/mesa/drivers/dri/i965/brw_device_info.c
+@@ -201,7 +201,7 @@ static const struct brw_device_info
brw_device_info_hsw_gt3 = {
+ .has_pln = true, \
+ .max_vs_threads = 280, \
+ .max_gs_threads = 256, \
+- .max_wm_threads = 64, /* threads per PSD */ \
++ .max_wm_threads = 408, \
+ .urb = { \
+ .size = 128, \
+ .min_vs_entries = 64, \
+diff --git a/src/mesa/drivers/dri/i965/gen8_ps_state.c
b/src/mesa/drivers/dri/i965/gen8_ps_state.c
+index c2810bb..561fc96 100644
+--- a/src/mesa/drivers/dri/i965/gen8_ps_state.c
++++ b/src/mesa/drivers/dri/i965/gen8_ps_state.c
+@@ -174,7 +174,10 @@ upload_ps_state(struct brw_context *brw)
+ if (ctx->Shader.CurrentProgram[MESA_SHADER_FRAGMENT] == NULL)
+ dw3 |= GEN7_PS_FLOATING_POINT_MODE_ALT;
+
+- dw6 |= (brw->max_wm_threads - 2) << HSW_PS_MAX_THREADS_SHIFT;
++ /* 3DSTATE_PS expects the number of threads per PSD, which is always 64;
++ * it implicitly scales for different GT levels (which have some # of
PSDs).
++ */
++ dw6 |= (64 - 2) << HSW_PS_MAX_THREADS_SHIFT;
+
+ /* CACHE_NEW_WM_PROG */
+ if (brw->wm.prog_data->base.nr_params > 0)
diff --git a/debian/patches/i965-use-mov-not-or-for-setting-urb.diff
b/debian/patches/i965-use-mov-not-or-for-setting-urb.diff
new file mode 100644
index 0000000..517d113
--- /dev/null
+++ b/debian/patches/i965-use-mov-not-or-for-setting-urb.diff
@@ -0,0 +1,34 @@
+commit dca84b4b5b23b68b3ea9da53d1775fa22cd1aff4
+Author: Kenneth Graunke <kenn...@whitecape.org>
+Date: Thu Jan 30 15:30:19 2014 -0800
+
+ i965: Use MOV, not OR for setting URB write channel enables on Gen8+.
+
+ On Broadwell, g0.5 contains the "Scratch Space Pointer"; using OR
+ puts some bits of that into "ignored" sections of our message header.
+
+ While this doesn't hurt, it's also not terribly /useful/. Using MOV
+ is sufficient to set the only interesting bits in this part of the
+ message header.
+
+ Signed-off-by: Kenneth Graunke <kenn...@whitecape.org>
+ Reviewed-by: Eric Anholt <e...@anholt.net>
+
+diff --git a/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp
b/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp
+index d0f574a..7ed5d2a 100644
+--- a/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp
++++ b/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp
+@@ -173,11 +173,8 @@ gen8_vec4_generator::generate_urb_write(vec4_instruction
*ir, bool vs)
+ if (!(ir->urb_write_flags & BRW_URB_WRITE_USE_CHANNEL_MASKS)) {
+ /* Enable Channel Masks in the URB_WRITE_OWORD message header */
+ default_state.access_mode = BRW_ALIGN_1;
+- inst = OR(retype(brw_vec1_grf(GEN7_MRF_HACK_START + ir->base_mrf, 5),
+- BRW_REGISTER_TYPE_UD),
+- retype(brw_vec1_grf(0, 5), BRW_REGISTER_TYPE_UD),
+- brw_imm_ud(0xff00));
+- gen8_set_mask_control(inst, BRW_MASK_DISABLE);
++ MOV_RAW(brw_vec1_grf(GEN7_MRF_HACK_START + ir->base_mrf, 5),
++ brw_imm_ud(0xff00));
+ default_state.access_mode = BRW_ALIGN_16;
+ }
+
diff --git a/debian/patches/series b/debian/patches/series
index 0b36287..681f4ed 100644
--- a/debian/patches/series
+++ b/debian/patches/series
@@ -16,3 +16,8 @@ enable-bdw.diff
fix-unity-on-bdw.diff
fix-gpu-hangs-on-bdw.diff
fix-svga-ioctl.patch
+i965-add-cherryview-support.diff
+i965-initialize-more-device-info-fields-chv.diff
+i965-use-mov-not-or-for-setting-urb.diff
+i965-store-absolute-thread-count.diff
+i965-drop-bogus-instructions-use-mov.diff
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