VERSION | 2
bin/.cherry-ignore | 11 +
debian/changelog | 9
docs/relnotes/10.2.4.html | 4
docs/relnotes/10.2.5.html | 185 +++++++++++++++++++
src/gallium/auxiliary/util/u_prim.h | 15 +
src/gallium/drivers/nouveau/nv50/nv84_video_bsp.c | 5
src/gallium/drivers/nouveau/nvc0/nvc0_program.c | 2
src/gallium/drivers/r300/r300_context.c | 4
src/gallium/drivers/r600/evergreen_state.c | 2
src/gallium/drivers/r600/r600_asm.c | 1
src/gallium/drivers/r600/r600_blit.c | 5
src/gallium/drivers/r600/r600_shader.c | 2
src/gallium/drivers/r600/r600_state.c | 2
src/gallium/drivers/radeon/r600_pipe_common.c | 8
src/gallium/drivers/radeon/r600_pipe_common.h | 1
src/gallium/drivers/radeon/r600_texture.c | 13 -
src/gallium/drivers/radeonsi/si_blit.c | 2
src/gallium/drivers/radeonsi/si_dma.c | 3
src/gallium/drivers/radeonsi/si_state_draw.c | 42 +++-
src/gallium/drivers/radeonsi/sid.h | 2
src/gallium/state_trackers/clover/core/timestamp.cpp | 1
src/gallium/state_trackers/wgl/stw_ext_pixelformat.c | 6
src/gallium/winsys/radeon/drm/radeon_drm_cs.h | 4
src/gallium/winsys/radeon/drm/radeon_winsys.h | 4
src/mesa/drivers/dri/i915/intel_screen.c | 3
src/mesa/drivers/dri/i965/brw_fs.cpp | 7
src/mesa/drivers/dri/i965/brw_wm.c | 6
src/mesa/drivers/dri/i965/brw_wm.h | 1
src/mesa/drivers/dri/i965/gen8_fs_generator.cpp | 11 -
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 4
src/mesa/main/format_pack.c | 2
src/mesa/main/get_hash_params.py | 1
src/mesa/main/texparam.c | 11 -
src/mesa/main/texstore.c | 15 +
35 files changed, 346 insertions(+), 50 deletions(-)
New commits:
commit 6b7c50d1c866649d1ebce82f17a2489bea8f568b
Author: Andreas Boll <andreas.boll....@gmail.com>
Date: Mon Aug 4 10:36:27 2014 +0200
Close bug #754297
diff --git a/debian/changelog b/debian/changelog
index 47310dd..90d8311 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -3,6 +3,7 @@ mesa (10.2.5-1) UNRELEASED; urgency=medium
* New upstream release.
- nv50: fix build failure on m68k due to invalid struct alignment
assumptions (Closes: #728053).
+ - i915: Fix up intelInitScreen2 for DRI3 (Closes: #754297).
-- Andreas Boll <andreas.boll....@gmail.com> Mon, 04 Aug 2014 10:30:18 +0200
commit d21c05b1d64bbf37eb37b74e18b6878d9e99bdfe
Author: Andreas Boll <andreas.boll....@gmail.com>
Date: Mon Aug 4 10:34:58 2014 +0200
Close bug #728053
diff --git a/debian/changelog b/debian/changelog
index 60f9ff7..47310dd 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,6 +1,8 @@
mesa (10.2.5-1) UNRELEASED; urgency=medium
* New upstream release.
+ - nv50: fix build failure on m68k due to invalid struct alignment
+ assumptions (Closes: #728053).
-- Andreas Boll <andreas.boll....@gmail.com> Mon, 04 Aug 2014 10:30:18 +0200
commit 34c5d89c1a8e74b0ed61f12ba3895577d243de9c
Author: Andreas Boll <andreas.boll....@gmail.com>
Date: Mon Aug 4 10:30:48 2014 +0200
New upstream release.
diff --git a/debian/changelog b/debian/changelog
index 16995ee..60f9ff7 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,3 +1,9 @@
+mesa (10.2.5-1) UNRELEASED; urgency=medium
+
+ * New upstream release.
+
+ -- Andreas Boll <andreas.boll....@gmail.com> Mon, 04 Aug 2014 10:30:18 +0200
+
mesa (10.2.4-1) unstable; urgency=medium
* New upstream release.
commit a53047f6d18fa50080a6a2bed41160318bd48c8a
Author: Carl Worth <cwo...@cworth.org>
Date: Sat Aug 2 19:06:05 2014 -0700
docs: Add release notes for 10.2.5
diff --git a/docs/relnotes/10.2.5.html b/docs/relnotes/10.2.5.html
new file mode 100644
index 0000000..68be843
--- /dev/null
+++ b/docs/relnotes/10.2.5.html
@@ -0,0 +1,185 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN"
"http://www.w3.org/TR/html4/loose.dtd";>
+<html lang="en">
+<head>
+ <meta http-equiv="content-type" content="text/html; charset=utf-8">
+ <title>Mesa Release Notes</title>
+ <link rel="stylesheet" type="text/css" href="../mesa.css">
+</head>
+<body>
+
+<div class="header">
+ <h1>The Mesa 3D Graphics Library</h1>
+</div>
+
+<iframe src="../contents.html"></iframe>
+<div class="content">
+
+<h1>Mesa 10.2.5 Release Notes / August 2, 2014</h1>
+
+<p>
+Mesa 10.2.5 is a bug fix release which fixes bugs found since the 10.2.4
release.
+</p>
+<p>
+Mesa 10.2.5 implements the OpenGL 3.3 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 3.3. OpenGL
+3.3 is <strong>only</strong> available if requested at context creation
+because compatibility contexts are not supported.
+</p>
+
+<h2>SHA256 checksums</h2>
+<pre>
+</pre>
+
+<h2>New features</h2>
+<p>None</p>
+
+<h2>Bug fixes</h2>
+
+<p>This list is likely incomplete.</p>
+
+<ul>
+
+<li><a href="https://bugs.freedesktop.org/show_bug.cgi?id=80991";>Bug 80991</a>
- [BDW]Piglit spec_ARB_sample_shading_builtin-gl-sample-mask_2 fails</li>
+
+</ul>
+
+<h2>Changes</h2>
+
+<p>Abdiel Janulgue (3):</p>
+<ul>
+ <li>i965/fs: Refactor check for potential copy propagated instructions.</li>
+ <li>i965/fs: skip copy-propate for logical instructions with negated src
entries</li>
+ <li>i965/vec4: skip copy-propate for logical instructions with negated src
entries</li>
+</ul>
+
+<p>Adel Gadllah (1):</p>
+<ul>
+ <li>i915: Fix up intelInitScreen2 for DRI3</li>
+</ul>
+
+<p>Anuj Phogat (2):</p>
+<ul>
+ <li>i965: Fix z_offset computation in intel_miptree_unmap_depthstencil()</li>
+ <li>mesa: Don't use memcpy() in _mesa_texstore() for float depth texture
data</li>
+</ul>
+
+<p>Brian Paul (3):</p>
+<ul>
+ <li>mesa: fix geometry shader memory leaks</li>
+ <li>st/mesa: fix geometry shader memory leak</li>
+ <li>gallium/u_blitter: fix some shader memory leaks</li>
+</ul>
+
+<p>Carl Worth (6):</p>
+<ul>
+ <li>docs: Add sha256 checksums for the 10.2.3 release</li>
+ <li>Update VERSION to 10.2.4</li>
+ <li>Add release notes for 10.2.4</li>
+ <li>docs: Add SHA256 checksums for the 10.2.4 release</li>
+ <li>cherry-ignore: Ignore a few patches picked in the previous stable
release</li>
+ <li>Update version to 10.2.5</li>
+</ul>
+
+<p>Christian König (1):</p>
+<ul>
+ <li>radeonsi: fix order of r600_need_dma_space and r600_context_bo_reloc</li>
+</ul>
+
+<p>Eric Anholt (1):</p>
+<ul>
+ <li>i965: Generalize the pixel_x/y workaround for all UW types.</li>
+</ul>
+
+<p>Ian Romanick (2):</p>
+<ul>
+ <li>mesa: Don't allow GL_TEXTURE_BORDER queries outside compat profile</li>
+ <li>mesa: Don't allow GL_TEXTURE_{LUMINANCE,INTENSITY}_* queries outside
compat profile</li>
+</ul>
+
+<p>Ilia Mirkin (5):</p>
+<ul>
+ <li>nv50/ir: retrieve shadow compare from first arg</li>
+ <li>nv50/ir: ignore bias for samplerCubeShadow on nv50</li>
+ <li>nvc0/ir: do quadops on the right texture coordinates for TXD</li>
+ <li>nvc0/ir: use manual TXD when offsets are involved</li>
+ <li>nvc0: make sure that the local memory allocation is aligned to 0x10</li>
+</ul>
+
+<p>Jason Ekstrand (2):</p>
+<ul>
+ <li>main/format_pack: Fix a wrong datatype in pack_ubyte_R8G8_UNORM</li>
+ <li>main/get_hash_params: Add GL_SAMPLE_SHADING_ARB</li>
+</ul>
+
+<p>Jordan Justen (1):</p>
+<ul>
+ <li>i965: Add auxiliary surface field #defines for Broadwell.</li>
+</ul>
+
+<p>José Fonseca (1):</p>
+<ul>
+ <li>st/wgl: Clamp wglChoosePixelFormatARB's output nNumFormats to
nMaxFormats.</li>
+</ul>
+
+<p>Kenneth Graunke (13):</p>
+<ul>
+ <li>i965: Don't copy propagate abs into Broadwell logic instructions.</li>
+ <li>i965: Set execution size to 8 for instructions with force_sechalf
set.</li>
+ <li>i965/fs: Set force_uncompressed and force_sechalf on samplepos
setup.</li>
+ <li>i965/fs: Use WE_all for gl_SampleID header register munging.</li>
+ <li>i965: Add plumbing for Broadwell's auxiliary surface support.</li>
+ <li>i965: Drop SINT workaround for CMS layout on Broadwell.</li>
+ <li>i965: Hook up the MCS buffers in SURFACE_STATE on Broadwell.</li>
+ <li>i965: Add 2x MSAA support to the MCS allocation function.</li>
+ <li>i965: Enable compressed multisample support (CMS) on Broadwell.</li>
+ <li>i965: Add missing persample_shading field to brw_wm_debug_recompile.</li>
+ <li>i965/fs: Fix gl_SampleID for 2x MSAA and SIMD16 mode.</li>
+ <li>i965/fs: Fix gl_SampleMask handling for SIMD16 on Gen8+.</li>
+ <li>i965/fs: Set LastRT on the final FB write on Broadwell.</li>
+</ul>
+
+<p>Marek Olšák (14):</p>
+<ul>
+ <li>gallium: fix u_default_transfer_inline_write for textures</li>
+ <li>st/mesa: fix samplerCubeShadow with bias</li>
+ <li>radeonsi: fix samplerCubeShadow with bias</li>
+ <li>radeonsi: add support for TXB2</li>
+ <li>r600g: switch SNORM conversion to DX and GLES behavior</li>
+ <li>radeonsi: fix CMASK and HTILE calculations for Hawaii</li>
+ <li>gallium/util: add a helper for calculating primitive count from vertex
count</li>
+ <li>radeonsi: fix a hang with instancing on Hawaii</li>
+ <li>radeonsi: fix a hang with streamout on Hawaii</li>
+ <li>winsys/radeon: fix vram_size overflow with Hawaii</li>
+ <li>radeonsi: fix occlusion queries on Hawaii</li>
+ <li>r600g,radeonsi: switch all occurences of array_size to
util_max_layer</li>
+ <li>radeonsi: fix build because of lack of draw_indirect infrastructure in
10.2</li>
+ <li>radeonsi: use DRAW_PREAMBLE on CIK</li>
+</ul>
+
+<p>Matt Turner (8):</p>
+<ul>
+ <li>i965/vec4: Don't return void from a void function.</li>
+ <li>i965/vec4: Don't fix_math_operand() on Gen >= 8.</li>
+ <li>i965/fs: Don't fix_math_operand() on Gen >= 8.</li>
+ <li>i965/fs: Make try_constant_propagate() static.</li>
+ <li>i965/fs: Constant propagate into 2-src math instructions on Gen8.</li>
+ <li>i965/vec4: Constant propagate into 2-src math instructions on Gen8.</li>
+ <li>i965/fs: Don't use brw_imm_* unnecessarily.</li>
+ <li>i965/fs: Set correct number of regs_written for MCS fetches.</li>
+</ul>
+
+<p>Thorsten Glaser (1):</p>
+<ul>
+ <li>nv50: fix build failure on m68k due to invalid struct alignment
assumptions</li>
+</ul>
+
+<p>Tom Stellard (1):</p>
+<ul>
+ <li>clover: Call end_query before getting timestamp result v2</li>
+</ul>
+
+</div>
+</body>
+</html>
commit b83b9b677b00b17fa449c519563838629093ec7c
Author: Carl Worth <cwo...@cworth.org>
Date: Sat Aug 2 19:03:34 2014 -0700
Update version to 10.2.5
In preparation for the 10.2.5 release, of course.
diff --git a/VERSION b/VERSION
index 06bcad3..9b36ab7 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-10.2.4
+10.2.5
commit 853cd6a4f76c936a0128747b237eefb7471b5d03
Author: Marek Olšák <marek.ol...@amd.com>
Date: Wed Apr 30 01:03:40 2014 +0200
radeonsi: use DRAW_PREAMBLE on CIK
It's the same as setting the 3 regs separately, but shorter, and it also
seems to be required on GFX7.2 and later. This doesn't fix Hawaii.
Reviewed-by: Michel Dänzer <michel.daen...@amd.com>
(cherry picked from commit 315f3c171d423e13069beb99a6b772726a141865)
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c
b/src/gallium/drivers/radeonsi/si_state_draw.c
index ec144a5..a24d9c0 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -439,15 +439,18 @@ static bool si_update_draw_info_state(struct si_context
*sctx,
ia_switch_on_eop = true;
}
- si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM,
+ si_pm4_set_reg(pm4, R_028B74_VGT_DISPATCH_DRAW_INDEX,
+ ib->index_size == 4 ? 0xFC000000 : 0xFC00);
+
+ si_pm4_cmd_begin(pm4, PKT3_DRAW_PREAMBLE);
+ si_pm4_cmd_add(pm4, prim); /* VGT_PRIMITIVE_TYPE */
+ si_pm4_cmd_add(pm4, /* IA_MULTI_VGT_PARAM */
S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
S_028AA8_PARTIAL_VS_WAVE_ON(1) |
S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1) |
S_028AA8_WD_SWITCH_ON_EOP(wd_switch_on_eop));
- si_pm4_set_reg(pm4, R_028B74_VGT_DISPATCH_DRAW_INDEX,
- ib->index_size == 4 ? 0xFC000000 : 0xFC00);
-
- si_pm4_set_reg(pm4, R_030908_VGT_PRIMITIVE_TYPE, prim);
+ si_pm4_cmd_add(pm4, 0); /* VGT_LS_HS_CONFIG */
+ si_pm4_cmd_end(pm4, false);
} else {
si_pm4_set_reg(pm4, R_008958_VGT_PRIMITIVE_TYPE, prim);
}
diff --git a/src/gallium/drivers/radeonsi/sid.h
b/src/gallium/drivers/radeonsi/sid.h
index 2bd2cb4..558da10 100644
--- a/src/gallium/drivers/radeonsi/sid.h
+++ b/src/gallium/drivers/radeonsi/sid.h
@@ -83,6 +83,8 @@
#define PKT3_DRAW_INDEX_IMMD 0x2E /* not on CIK */
#define PKT3_NUM_INSTANCES 0x2F
#define PKT3_STRMOUT_BUFFER_UPDATE 0x34
+#define PKT3_DRAW_INDEX_OFFSET_2 0x35
+#define PKT3_DRAW_PREAMBLE 0x36 /* new on CIK, required on
GFX7.2 and later */
#define PKT3_WRITE_DATA 0x37
#define PKT3_WRITE_DATA_DST_SEL(x) ((x) << 8)
#define PKT3_WRITE_DATA_DST_SEL_REG 0
commit c66da3d45761f8776c08aa7f29ef2efd6bb635d3
Author: Christian König <christian.koe...@amd.com>
Date: Wed Jul 9 14:38:06 2014 +0200
radeonsi: fix order of r600_need_dma_space and r600_context_bo_reloc
Signed-off-by: Christian König <christian.koe...@amd.com>
Reviewed-by: Marek Olšák <marek.ol...@amd.com>
(cherry picked from commit c8011c1885003b79c9f0c6530e46ae6cb0e69575)
diff --git a/src/gallium/drivers/radeonsi/si_dma.c
b/src/gallium/drivers/radeonsi/si_dma.c
index dc8c609..26f1e1b 100644
--- a/src/gallium/drivers/radeonsi/si_dma.c
+++ b/src/gallium/drivers/radeonsi/si_dma.c
@@ -91,12 +91,13 @@ static void si_dma_copy_buffer(struct si_context *ctx,
}
ncopy = (size / max_csize) + !!(size % max_csize);
+ r600_need_dma_space(&ctx->b, ncopy * 5);
+
r600_context_bo_reloc(&ctx->b, &ctx->b.rings.dma, rsrc,
RADEON_USAGE_READ,
RADEON_PRIO_MIN);
r600_context_bo_reloc(&ctx->b, &ctx->b.rings.dma, rdst,
RADEON_USAGE_WRITE,
RADEON_PRIO_MIN);
- r600_need_dma_space(&ctx->b, ncopy * 5);
for (i = 0; i < ncopy; i++) {
csize = size < max_csize ? size : max_csize;
cs->buf[cs->cdw++] = SI_DMA_PACKET(SI_DMA_PACKET_COPY, sub_cmd,
csize);
commit f75dfcee1058d77670d85e047c3ef1e102011a2f
Author: Marek Olšák <marek.ol...@amd.com>
Date: Thu Jul 31 20:04:42 2014 +0200
radeonsi: fix build because of lack of draw_indirect infrastructure in 10.2
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c
b/src/gallium/drivers/radeonsi/si_state_draw.c
index 33e8e2a..ec144a5 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -433,8 +433,7 @@ static bool si_update_draw_info_state(struct si_context
*sctx,
* We don't know that for indirect drawing, so treat it as
* always problematic. */
if (sctx->b.family == CHIP_HAWAII &&
- (info->indirect ||
- (info->instance_count > 1 &&
+ ((info->instance_count > 1 &&
u_prims_for_vertices(info->mode, info->count) <
primgroup_size))) {
wd_switch_on_eop = true;
ia_switch_on_eop = true;
commit 490d8ddf879300cdab44d344f0e5f72b3400b4cc
Author: Carl Worth <cwo...@cworth.org>
Date: Wed Jul 30 19:20:51 2014 -0700
cherry-ignore: Ignore a few patches picked in the previous stable release
I don't know what happened here, but these three commits were picked
earlier,
but the commit IDs referenced in their commit messages do not currently
appear in the master branch, (perhaps a force-push occurred?).
Anyway, we can ignore these now.
diff --git a/bin/.cherry-ignore b/bin/.cherry-ignore
index 80df7dc..ca1bc86 100644
--- a/bin/.cherry-ignore
+++ b/bin/.cherry-ignore
@@ -5,3 +5,14 @@ e6967270c75a5b669152127bb7a746d55f4407a6 i965: Fix depth
(array slices) computat
# This patch didn't have enough in the commit message to convince me it
# is a bug fix, (email sent to author asking for more information).
41d759d076737f94976f5294b734dbc437a12bae
+
+# These patch were already cherry-picked before the 10.2.4 release.
+#
+# But get-pick-list.sh doesn't realize that because the commit messages for
+# these on the stable branch reference commit IDs that don't actually appear
+# on master. I'm not sure what happened, (perhaps master was force-pushed at
+# some point?).
+2eaf3f670fea4ce4466340141244e41a45542c13
+e5adc560cc8544200faa3e04504202839626ab37
+cf1b5eee7f36af29d1d5caba3538ad4985e51f81
+
commit b9c5a8f869ae76ba560db88523779eae9014b826
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Mon Jul 28 18:30:55 2014 -0700
main/get_hash_params: Add GL_SAMPLE_SHADING_ARB
GL_SAMPLE_SHADING is specified as a valid pname for glGet in the
GL_ARB_sample_shading extension. It seems as if we forgot to add it to the
table of pnames.
Signed-off-by: Jason Ekstrand <jason.ekstr...@intel.com>
Reviewed-by: Matt Turner <matts...@gmail.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
Cc: mesa-sta...@lists.freedesktop.org
(cherry picked from commit 3ea922dd7ca773033a09068e397b34d8abd4c763)
diff --git a/src/mesa/main/get_hash_params.py b/src/mesa/main/get_hash_params.py
index c7a6e02..8ce47ff 100644
--- a/src/mesa/main/get_hash_params.py
+++ b/src/mesa/main/get_hash_params.py
@@ -84,6 +84,7 @@ descriptor=[
[ "SAMPLES_ARB", "BUFFER_INT(Visual.samples), extra_new_buffers" ],
# GL_ARB_sample_shading
+ [ "SAMPLE_SHADING_ARB", "CONTEXT_BOOL(Multisample.SampleShading),
extra_gl40_ARB_sample_shading" ],
[ "MIN_SAMPLE_SHADING_VALUE_ARB",
"CONTEXT_FLOAT(Multisample.MinSampleShadingValue),
extra_gl40_ARB_sample_shading" ],
# GL_SGIS_generate_mipmap
commit c84b367b18821e7790015cdb426abab1d9b544d0
Author: José Fonseca <jfons...@vmware.com>
Date: Thu Jul 24 15:50:56 2014 +0100
st/wgl: Clamp wglChoosePixelFormatARB's output nNumFormats to nMaxFormats.
While running https://github.com/nvMcJohn/apitest with apitrace I noticed
that Mesa was producing bogus results:
wglChoosePixelFormatARB(hdc, piAttribIList = {...}, pfAttribFList = &0,
nMaxFormats = 1, piFormats = {19, 65576, 37, 198656, 131075, 0, 402653184, 0,
0, 0, 0, -573575710}, nNumFormats = &12) = TRUE
However https://www.opengl.org/registry/specs/ARB/wgl_pixel_format.txt
states
<nNumFormats> returns the number of matching formats. The returned
value is guaranteed to be no larger than <nMaxFormats>.
Cc: "10.2" <mesa-sta...@lists.freedesktop.org>
Reviewed-by: Brian Paul <bri...@vmware.com>
(cherry picked from commit 66a1b3a1da5cbb75d727c9b4751a06bdd403f0f9)
diff --git a/src/gallium/state_trackers/wgl/stw_ext_pixelformat.c
b/src/gallium/state_trackers/wgl/stw_ext_pixelformat.c
index d303b01..91682d1 100644
--- a/src/gallium/state_trackers/wgl/stw_ext_pixelformat.c
+++ b/src/gallium/state_trackers/wgl/stw_ext_pixelformat.c
@@ -448,9 +448,11 @@ wglChoosePixelFormatARB(
*/
for (i = 0; i < count; i++) {
if (scores[i].points > 0) {
- if (*nNumFormats < nMaxFormats)
- piFormats[*nNumFormats] = scores[i].index + 1;
+ piFormats[*nNumFormats] = scores[i].index + 1;
(*nNumFormats)++;
+ if (*nNumFormats >= nMaxFormats) {
+ break;
+ }
}
}
commit 71102219ea97aaee0c6d8076d26857581340535d
Author: Marek Olšák <marek.ol...@amd.com>
Date: Sat Jul 26 17:15:39 2014 +0200
r600g,radeonsi: switch all occurences of array_size to util_max_layer
This fixes 3D texture support in all these cases, because array_size is 1
with 3D textures and depth0 actually contains the "array size".
util_max_layer is universal and returns the last layer index for any texture
target.
A lot of the cases below can't actually be hit with 3D textures, but let's
be consistent.
This fixes a failure in:
piglit layered-rendering/clear-color-all-types 3d single_level
for r600g and radeonsi, which was caused by an incorrect CMASK size
calculation.
Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Michel Dänzer <michel.daen...@amd.com>
(cherry picked from commit a9528cef6b6ff4875c9d125a60b7309a2ad24766)
diff --git a/src/gallium/drivers/r600/r600_blit.c
b/src/gallium/drivers/r600/r600_blit.c
index bbc64ac..6fab57c 100644
--- a/src/gallium/drivers/r600/r600_blit.c
+++ b/src/gallium/drivers/r600/r600_blit.c
@@ -430,7 +430,8 @@ static void r600_clear(struct pipe_context *ctx, unsigned
buffers,
* disable fast clear for texture array.
*/
/* Only use htile for first level */
- if (rtex->htile_buffer && !level && rtex->surface.array_size ==
1) {
+ if (rtex->htile_buffer && !level &&
+ util_max_layer(&rtex->resource.b.b, level) == 0) {
if (rtex->depth_clear_value != depth) {
rtex->depth_clear_value = depth;
rctx->db_state.atom.dirty = true;
@@ -837,7 +838,7 @@ static void r600_flush_resource(struct pipe_context *ctx,
if (!rtex->is_depth && rtex->cmask.size) {
r600_blit_decompress_color(ctx, rtex, 0, res->last_level,
- 0, res->array_size - 1);
+ 0, util_max_layer(res, 0));
}
}
diff --git a/src/gallium/drivers/radeon/r600_texture.c
b/src/gallium/drivers/radeon/r600_texture.c
index 519f099..0e59568 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -380,7 +380,8 @@ void r600_texture_get_cmask_info(struct r600_common_screen
*rscreen,
out->slice_tile_max = ((pitch_elements * height) / (128*128)) - 1;
out->alignment = MAX2(256, base_align);
- out->size = rtex->surface.array_size * align(slice_bytes, base_align);
+ out->size = (util_max_layer(&rtex->resource.b.b, 0) + 1) *
+ align(slice_bytes, base_align);
}
static void si_texture_get_cmask_info(struct r600_common_screen *rscreen,
@@ -427,7 +428,8 @@ static void si_texture_get_cmask_info(struct
r600_common_screen *rscreen,
out->slice_tile_max -= 1;
out->alignment = MAX2(256, base_align);
- out->size = rtex->surface.array_size * align(slice_bytes, base_align);
+ out->size = (util_max_layer(&rtex->resource.b.b, 0) + 1) *
+ align(slice_bytes, base_align);
}
static void r600_texture_allocate_cmask(struct r600_common_screen *rscreen,
@@ -523,7 +525,8 @@ static unsigned si_texture_htile_alloc_size(struct
r600_common_screen *rscreen,
pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
base_align = num_pipes * pipe_interleave_bytes;
- return rtex->surface.array_size * align(slice_bytes, base_align);
+ return (util_max_layer(&rtex->resource.b.b, 0) + 1) *
+ align(slice_bytes, base_align);
}
static unsigned r600_texture_htile_alloc_size(struct r600_common_screen
*rscreen,
diff --git a/src/gallium/drivers/radeonsi/si_blit.c
b/src/gallium/drivers/radeonsi/si_blit.c
index 1dfff49..ea10654 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -735,7 +735,7 @@ static void si_flush_resource(struct pipe_context *ctx,
if (!rtex->is_depth && rtex->cmask.size) {
si_blit_decompress_color(ctx, rtex, 0, res->last_level,
- 0, res->array_size - 1);
+ 0, util_max_layer(res, 0));
}
}
commit d26ac40bada800cce24ed7c988fbc31dff89681d
Author: Marek Olšák <marek.ol...@amd.com>
Date: Sat Jul 26 12:57:28 2014 +0200
radeonsi: fix occlusion queries on Hawaii
This was just a guess - and it worked!
Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
(cherry picked from commit 71ce92200e0314a0878088dec8c0c2a0270bc4dc)
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c
b/src/gallium/drivers/radeon/r600_pipe_common.c
index 70c4d1a..fcb8164 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -142,7 +142,13 @@ bool r600_common_context_init(struct r600_common_context
*rctx,
rctx->ws = rscreen->ws;
rctx->family = rscreen->family;
rctx->chip_class = rscreen->chip_class;
- rctx->max_db = rscreen->chip_class >= EVERGREEN ? 8 : 4;
+
+ if (rscreen->family == CHIP_HAWAII)
+ rctx->max_db = 16;
+ else if (rscreen->chip_class >= EVERGREEN)
+ rctx->max_db = 8;
+ else
+ rctx->max_db = 4;
rctx->b.transfer_map = u_transfer_map_vtbl;
rctx->b.transfer_flush_region = u_default_transfer_flush_region;
commit 50dcc2eb261b5a5f6e9446e6df12fde2395cbea4
Author: Marek Olšák <marek.ol...@amd.com>
Date: Sat Jul 26 12:37:03 2014 +0200
winsys/radeon: fix vram_size overflow with Hawaii
This fixes piglit spec/!OpenGL 3.1/minmax.
Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
(cherry picked from commit 156b7e244c93e82f5d6b19caae1ec25e7f0e91bb)
diff --git a/src/gallium/drivers/r300/r300_context.c
b/src/gallium/drivers/r300/r300_context.c
index 7ae3551..4e06fc4 100644
--- a/src/gallium/drivers/r300/r300_context.c
+++ b/src/gallium/drivers/r300/r300_context.c
@@ -37,6 +37,8 @@
#include "r300_screen_buffer.h"
#include "compiler/radeon_regalloc.h"
+#include <inttypes.h>
+
static void r300_release_referenced_objects(struct r300_context *r300)
{
struct pipe_framebuffer_state *fb =
@@ -482,7 +484,7 @@ struct pipe_context* r300_create_context(struct
pipe_screen* screen,
#endif
fprintf(stderr,
"r300: DRM version: %d.%d.%d, Name: %s, ID: 0x%04x, GB: %d, Z:
%d\n"
- "r300: GART size: %d MB, VRAM size: %d MB\n"
+ "r300: GART size: %"PRIu64" MB, VRAM size: %"PRIu64" MB\n"
"r300: AA compression RAM: %s, Z compression RAM: %s, HiZ RAM:
%s\n",
r300->screen->info.drm_major,
r300->screen->info.drm_minor,
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_cs.h
b/src/gallium/winsys/radeon/drm/radeon_drm_cs.h
index c601019..089494e 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_cs.h
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_cs.h
@@ -50,8 +50,8 @@ struct radeon_cs_context {
int reloc_indices_hashlist[512];
- unsigned used_vram;
- unsigned used_gart;
+ uint64_t used_vram;
+ uint64_t used_gart;
};
struct radeon_drm_cs {
diff --git a/src/gallium/winsys/radeon/drm/radeon_winsys.h
b/src/gallium/winsys/radeon/drm/radeon_winsys.h
index 2d13550..1106454 100644
--- a/src/gallium/winsys/radeon/drm/radeon_winsys.h
+++ b/src/gallium/winsys/radeon/drm/radeon_winsys.h
@@ -195,8 +195,8 @@ struct radeon_info {
uint32_t pci_id;
enum radeon_family family;
enum chip_class chip_class;
- uint32_t gart_size;
- uint32_t vram_size;
+ uint64_t gart_size;
+ uint64_t vram_size;
uint32_t max_sclk;
uint32_t drm_major; /* version */
commit 0dfcf5063970d0d47d9e0ea7529f572fdc16535d
Author: Marek Olšák <marek.ol...@amd.com>
Date: Sat Jul 26 03:16:22 2014 +0200
radeonsi: fix a hang with streamout on Hawaii
I actually couldn't reproduce this one, but internal docs recommend this
workaround. Better safe than sorry.
Also, the number of dwords for the sync packets is increased by 4 instead
of 2, because it wasn't bumped last time when a new packet was added there.
Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
(cherry picked from commit 0e7f56313d2a265cbdc2140f45dc4a0c6ae07e4e)
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h
b/src/gallium/drivers/radeon/r600_pipe_common.h
index bbfcdf9..e7f410d 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -72,6 +72,7 @@
#define R600_CONTEXT_WAIT_3D_IDLE (1 << 17)
#define R600_CONTEXT_WAIT_CP_DMA_IDLE (1 << 18)
#define R600_CONTEXT_VGT_FLUSH (1 << 19)
+#define R600_CONTEXT_VGT_STREAMOUT_SYNC (1 << 20)
/* Debug flags. */
/* logging */
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c
b/src/gallium/drivers/radeonsi/si_state_draw.c
index df0aed1..33e8e2a 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -916,11 +916,15 @@ void si_emit_cache_flush(struct r600_common_context
*sctx, struct r600_atom *ato
radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) |
EVENT_INDEX(0));
}
+ if (sctx->flags & R600_CONTEXT_VGT_STREAMOUT_SYNC) {
+ radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
+ radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) |
EVENT_INDEX(0));
+ }
sctx->flags = 0;
}
-const struct r600_atom si_atom_cache_flush = { si_emit_cache_flush, 13 }; /*
number of CS dwords */
+const struct r600_atom si_atom_cache_flush = { si_emit_cache_flush, 17 }; /*
number of CS dwords */
void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
{
@@ -999,6 +1003,14 @@ void si_draw_vbo(struct pipe_context *ctx, const struct
pipe_draw_info *info)
}
#endif
+ /* Workaround for a VGT hang when streamout is enabled.
+ * It must be done after drawing. */
+ if (sctx->b.family == CHIP_HAWAII &&
+ (sctx->b.streamout.streamout_enabled ||
+ sctx->b.streamout.prims_gen_query_enabled)) {
+ sctx->b.flags |= R600_CONTEXT_VGT_STREAMOUT_SYNC;
+ }
+
/* Set the depth buffer as dirty. */
if (sctx->framebuffer.state.zsbuf) {
struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
commit 6ff3da25090ff62d501653636100c7f470f6f290
Author: Marek Olšák <marek.ol...@amd.com>
Date: Sat Jul 26 02:56:00 2014 +0200
radeonsi: fix a hang with instancing on Hawaii
This fixes "piglit/bin/arb_transform_feedback2-draw-auto instanced".
Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
(cherry picked from commit 3d9e87406cfaf4a2bfef5b4bae50af94d1cc424f)
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c
b/src/gallium/drivers/radeonsi/si_state_draw.c
index 0676b15..df0aed1 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -33,6 +33,7 @@
#include "util/u_format.h"
#include "util/u_index_modify.h"
#include "util/u_memory.h"
+#include "util/u_prim.h"
#include "util/u_upload_mgr.h"
/*
@@ -425,11 +426,24 @@ static bool si_update_draw_info_state(struct si_context
*sctx,
(rs ? rs->line_stipple_enable : false);
/* If the WD switch is false, the IA switch must be false too.
*/
bool ia_switch_on_eop = wd_switch_on_eop;
+ unsigned primgroup_size = 64;
+
+ /* Hawaii hangs if instancing is enabled and each instance
+ * is smaller than a prim group and WD_SWITCH_ON_EOP is 0.
+ * We don't know that for indirect drawing, so treat it as
+ * always problematic. */
+ if (sctx->b.family == CHIP_HAWAII &&
+ (info->indirect ||
+ (info->instance_count > 1 &&
+ u_prims_for_vertices(info->mode, info->count) <
primgroup_size))) {
+ wd_switch_on_eop = true;
+ ia_switch_on_eop = true;
+ }
si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM,
S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
S_028AA8_PARTIAL_VS_WAVE_ON(1) |
- S_028AA8_PRIMGROUP_SIZE(63) |
+ S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1) |
S_028AA8_WD_SWITCH_ON_EOP(wd_switch_on_eop));
si_pm4_set_reg(pm4, R_028B74_VGT_DISPATCH_DRAW_INDEX,
ib->index_size == 4 ? 0xFC000000 : 0xFC00);
commit 378def4cab1b2aad070b51ba2e10d590d1ff1722
Author: Marek Olšák <marek.ol...@amd.com>
Date: Sat Jul 26 02:54:23 2014 +0200
gallium/util: add a helper for calculating primitive count from vertex count
This is needed by the following commit which is a candidate for stable too.
Cc: mesa-sta...@lists.freedesktop.org
(cherry picked from commit c7407b94a8eb329a45cdd0acb5255670d4c0e041)
diff --git a/src/gallium/auxiliary/util/u_prim.h
b/src/gallium/auxiliary/util/u_prim.h
index fd95c0b..cf1a18f 100644
--- a/src/gallium/auxiliary/util/u_prim.h
+++ b/src/gallium/auxiliary/util/u_prim.h
@@ -136,6 +136,21 @@ u_prim_vertex_count(unsigned prim)
return (likely(prim < PIPE_PRIM_MAX)) ? &prim_table[prim] : NULL;
}
+/**
+ * Given a vertex count, return the number of primitives.
+ * For polygons, return the number of triangles.
+ */
+static INLINE unsigned
+u_prims_for_vertices(unsigned prim, unsigned num)
+{
+ const struct u_prim_vertex_count *info = u_prim_vertex_count(prim);
+
+ if (num < info->min)
+ return 0;
+
+ return 1 + ((num - info->min) / info->incr);
+}
+
static INLINE boolean u_validate_pipe_prim( unsigned pipe_prim, unsigned nr )
{
const struct u_prim_vertex_count *count = u_prim_vertex_count(pipe_prim);
commit fcb6c0d2b8cb36c3d1b7cbbf3437aeb65a808682
Author: Marek Olšák <marek.ol...@amd.com>
Date: Sat Jul 26 00:48:48 2014 +0200
radeonsi: fix CMASK and HTILE calculations for Hawaii
This fixes the checkerboard pattern in glxgears and anything that triggers
fast color clear.
num_channels is always <= 8, but Hawaii has 16 pipes.
Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
(cherry picked from commit 9b046474c95f15338d4c748df9b62871bba6f36f)
diff --git a/src/gallium/drivers/radeon/r600_texture.c
b/src/gallium/drivers/radeon/r600_texture.c
index 3a37465..519f099 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -388,7 +388,7 @@ static void si_texture_get_cmask_info(struct
r600_common_screen *rscreen,
struct r600_cmask_info *out)
{
unsigned pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
- unsigned num_pipes = rscreen->tiling_info.num_channels;
+ unsigned num_pipes = rscreen->info.r600_num_tile_pipes;
unsigned cl_width, cl_height;
switch (num_pipes) {
@@ -485,7 +485,7 @@ static unsigned si_texture_htile_alloc_size(struct
r600_common_screen *rscreen,
{
unsigned cl_width, cl_height, width, height;
unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align;
- unsigned num_pipes = rscreen->tiling_info.num_channels;
+ unsigned num_pipes = rscreen->info.r600_num_tile_pipes;
/* HTILE is broken with 1D tiling on old kernels and CIK. */
if (rtex->surface.level[0].mode == RADEON_SURF_MODE_1D &&
commit d59406cdb763140037a75e119005a8c0815a1f72
Author: Marek Olšák <marek.ol...@amd.com>
Date: Wed Jul 23 19:22:30 2014 +0200
r600g: switch SNORM conversion to DX and GLES behavior
it also matches GL 4.2
further discussion:
http://lists.freedesktop.org/archives/mesa-dev/2013-August/042680.html
Cc: mesa-sta...@lists.freedesktop.org
(cherry picked from commit d5bcb5e8dea3dc949ff6b093af7f46585b94b63e)
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src/gallium/drivers/r600/evergreen_state.c
index f7a63a8..f0d4503 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -626,7 +626,6 @@ texture_buffer_sampler_view(struct r600_pipe_sampler_view
*view,
S_030008_DATA_FORMAT(format) |
S_030008_NUM_FORMAT_ALL(num_format) |
S_030008_FORMAT_COMP_ALL(format_comp) |
- S_030008_SRF_MODE_ALL(1) |
S_030008_ENDIAN_SWAP(endian);
view->tex_resource_words[3] = swizzle_res;
/*
@@ -805,7 +804,6 @@ evergreen_create_sampler_view_custom(struct pipe_context
*ctx,
}
view->tex_resource_words[4] = (word4 |
-
S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
S_030010_ENDIAN_SWAP(endian));
view->tex_resource_words[5] =
S_030014_BASE_ARRAY(state->u.tex.first_layer) |
S_030014_LAST_ARRAY(state->u.tex.last_layer);
diff --git a/src/gallium/drivers/r600/r600_asm.c
b/src/gallium/drivers/r600/r600_asm.c
index 67df2f2..0f00c35 100644
--- a/src/gallium/drivers/r600/r600_asm.c
+++ b/src/gallium/drivers/r600/r600_asm.c
@@ -2374,7 +2374,6 @@ void *r600_create_vertex_fetch_shader(struct pipe_context
*ctx,
vtx.data_format = format;
vtx.num_format_all = num_format;
vtx.format_comp_all = format_comp;
- vtx.srf_mode_all = 1;
vtx.offset = elements[i].src_offset;
vtx.endian = endian;
diff --git a/src/gallium/drivers/r600/r600_shader.c
b/src/gallium/drivers/r600/r600_shader.c
index 81d879a..b42ad96 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -851,7 +851,6 @@ static int tgsi_fetch_rel_const(struct r600_shader_ctx
*ctx, unsigned int cb_idx
vtx.data_format = FMT_32_32_32_32_FLOAT;
vtx.num_format_all = 2; /* NUM_FORMAT_SCALED */
vtx.format_comp_all = 1; /* FORMAT_COMP_SIGNED */
- vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
vtx.endian = r600_endian_swap(32);
if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
@@ -4309,7 +4308,6 @@ static int do_vtx_fetch_inst(struct r600_shader_ctx *ctx,
boolean src_requires_l
vtx.dst_sel_z = (inst->Dst[0].Register.WriteMask & 4) ? 2 : 7;
/* SEL_Z */
vtx.dst_sel_w = (inst->Dst[0].Register.WriteMask & 8) ? 3 : 7;
/* SEL_W */
vtx.use_const_fields = 1;
- vtx.srf_mode_all = 1; /* SRF_MODE_NO_ZERO */
if ((r = r600_bytecode_add_vtx(ctx->bc, &vtx)))
return r;
diff --git a/src/gallium/drivers/r600/r600_state.c
b/src/gallium/drivers/r600/r600_state.c
index a0ba131..dd2e423 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -609,7 +609,6 @@ texture_buffer_sampler_view(struct r600_pipe_sampler_view
*view,
S_038008_DATA_FORMAT(format) |
S_038008_NUM_FORMAT_ALL(num_format) |
S_038008_FORMAT_COMP_ALL(format_comp) |
- S_038008_SRF_MODE_ALL(1) |
S_038008_ENDIAN_SWAP(endian);
view->tex_resource_words[3] = 0;
/*
@@ -720,7 +719,6 @@ r600_create_sampler_view_custom(struct pipe_context *ctx,
view->tex_resource_words[3] = tmp->surface.level[offset_level +
1].offset >> 8;
}
view->tex_resource_words[4] = (word4 |
-
S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
S_038010_REQUEST_SIZE(1) |
S_038010_ENDIAN_SWAP(endian) |
S_038010_BASE_LEVEL(0));
commit f2023b8dc8807ceba0c9475c4020595729457924
Author: Ilia Mirkin <imir...@alum.mit.edu>
Date: Thu Jul 17 22:11:56 2014 -0400
nvc0: make sure that the local memory allocation is aligned to 0x10
Signed-off-by: Ilia Mirkin <imir...@alum.mit.edu>
Cc: <mesa-sta...@lists.freedesktop.org>
(cherry picked from commit 47e5a8d7a24b80fe1738d88bfffcb04431d612e8)
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
index 394e4a3..92580f7 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
--
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