debian/changelog | 9 +
debian/patches/add-more-reserved-hsw-ids.diff | 136 ++++++++++++++++++++++++++
debian/patches/fix-hsw-crw-ids.diff | 40 +++++++
debian/patches/fix-hsw-gt3-names.diff | 110 +++++++++++++++++++++
debian/patches/series | 3
5 files changed, 298 insertions(+)
New commits:
commit 7caaa49df616af70d139371aeb9056bd75ae5aa9
Author: Maarten Lankhorst <maarten.lankho...@canonical.com>
Date: Wed Jun 19 10:24:58 2013 +0200
merge sru from precise-propose
diff --git a/debian/changelog b/debian/changelog
index e405f09..1e477c7 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,3 +1,12 @@
+libdrm (2.4.43-0ubuntu0.0.2) precise-proposed; urgency=low
+
+ * Added patches to add/fix Haswell pci-id's (LP: #1175533)
+ - fix-hsw-crw-ids.diff
+ - fix-hsw-gt3-names.diff
+ - add-more-reserved-hsw-ids.diff
+
+ -- Maarten Lankhorst <maarten.lankho...@ubuntu.com> Wed, 19 Jun 2013
10:24:58 +0200
+
libdrm (2.4.43-0ubuntu0.0.1) precise-proposed; urgency=low
* Copy package from raring, and re-enable libdrm-nouveau1a. (LP: #1171340)
diff --git a/debian/patches/add-more-reserved-hsw-ids.diff
b/debian/patches/add-more-reserved-hsw-ids.diff
new file mode 100644
index 0000000..5586818
--- /dev/null
+++ b/debian/patches/add-more-reserved-hsw-ids.diff
@@ -0,0 +1,136 @@
+commit 1669a67d063e82a58dae4d906015172d471e9a2a
+Author: Rodrigo Vivi <rodrigo.v...@gmail.com>
+Date: Mon May 13 17:48:40 2013 -0300
+
+ intel: Adding more reserved PCI IDs for Haswell.
+
+ At DDX commit Chris mentioned the tendency we have of finding out more
+ PCI IDs only when users report. So Let's add all new reserved Haswell IDs.
+
+ Bugzilla: http://bugs.freedesktop.org/show_bug.cgi?id=63701
+ Signed-off-by: Rodrigo Vivi <rodrigo.v...@gmail.com>
+ Acked-by: Kenneth Graunke <kenn...@whitecape.org>
+
+diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
+index 3350def..aeb439e 100644
+--- a/intel/intel_chipset.h
++++ b/intel/intel_chipset.h
+@@ -97,6 +97,12 @@
+ #define PCI_CHIP_HASWELL_S_GT1 0x040A /* Server */
+ #define PCI_CHIP_HASWELL_S_GT2 0x041A
+ #define PCI_CHIP_HASWELL_S_GT3 0x042A
++#define PCI_CHIP_HASWELL_B_GT1 0x040B /* Reserved */
++#define PCI_CHIP_HASWELL_B_GT2 0x041B
++#define PCI_CHIP_HASWELL_B_GT3 0x042B
++#define PCI_CHIP_HASWELL_E_GT1 0x040E /* Reserved */
++#define PCI_CHIP_HASWELL_E_GT2 0x041E
++#define PCI_CHIP_HASWELL_E_GT3 0x042E
+ #define PCI_CHIP_HASWELL_SDV_GT1 0x0C02 /* Desktop */
+ #define PCI_CHIP_HASWELL_SDV_GT2 0x0C12
+ #define PCI_CHIP_HASWELL_SDV_GT3 0x0C22
+@@ -106,6 +112,12 @@
+ #define PCI_CHIP_HASWELL_SDV_S_GT1 0x0C0A /* Server */
+ #define PCI_CHIP_HASWELL_SDV_S_GT2 0x0C1A
+ #define PCI_CHIP_HASWELL_SDV_S_GT3 0x0C2A
++#define PCI_CHIP_HASWELL_SDV_B_GT1 0x0C0B /* Reserved */
++#define PCI_CHIP_HASWELL_SDV_B_GT2 0x0C1B
++#define PCI_CHIP_HASWELL_SDV_B_GT3 0x0C2B
++#define PCI_CHIP_HASWELL_SDV_E_GT1 0x0C0E /* Reserved */
++#define PCI_CHIP_HASWELL_SDV_E_GT2 0x0C1E
++#define PCI_CHIP_HASWELL_SDV_E_GT3 0x0C2E
+ #define PCI_CHIP_HASWELL_ULT_GT1 0x0A02 /* Desktop */
+ #define PCI_CHIP_HASWELL_ULT_GT2 0x0A12
+ #define PCI_CHIP_HASWELL_ULT_GT3 0x0A22
+@@ -115,6 +127,12 @@
+ #define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A /* Server */
+ #define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A
+ #define PCI_CHIP_HASWELL_ULT_S_GT3 0x0A2A
++#define PCI_CHIP_HASWELL_ULT_B_GT1 0x0A0B /* Reserved */
++#define PCI_CHIP_HASWELL_ULT_B_GT2 0x0A1B
++#define PCI_CHIP_HASWELL_ULT_B_GT3 0x0A2B
++#define PCI_CHIP_HASWELL_ULT_E_GT1 0x0A0E /* Reserved */
++#define PCI_CHIP_HASWELL_ULT_E_GT2 0x0A1E
++#define PCI_CHIP_HASWELL_ULT_E_GT3 0x0A2E
+ #define PCI_CHIP_HASWELL_CRW_GT1 0x0D02 /* Desktop */
+ #define PCI_CHIP_HASWELL_CRW_GT2 0x0D12
+ #define PCI_CHIP_HASWELL_CRW_GT3 0x0D22
+@@ -124,6 +142,12 @@
+ #define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D0A /* Server */
+ #define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D1A
+ #define PCI_CHIP_HASWELL_CRW_S_GT3 0x0D2A
++#define PCI_CHIP_HASWELL_CRW_B_GT1 0x0D0B /* Reserved */
++#define PCI_CHIP_HASWELL_CRW_B_GT2 0x0D1B
++#define PCI_CHIP_HASWELL_CRW_B_GT3 0x0D2B
++#define PCI_CHIP_HASWELL_CRW_E_GT1 0x0D0E /* Reserved */
++#define PCI_CHIP_HASWELL_CRW_E_GT2 0x0D1E
++#define PCI_CHIP_HASWELL_CRW_E_GT3 0x0D2E
+
+ #define PCI_CHIP_VALLEYVIEW_PO 0x0f30 /* VLV PO board */
+ #define PCI_CHIP_VALLEYVIEW_1 0x0f31
+@@ -210,39 +234,63 @@
+ #define IS_HSW_GT1(devid) ((devid) == PCI_CHIP_HASWELL_GT1 || \
+ (devid) == PCI_CHIP_HASWELL_M_GT1 || \
+ (devid) == PCI_CHIP_HASWELL_S_GT1 || \
++ (devid) == PCI_CHIP_HASWELL_B_GT1 || \
++ (devid) == PCI_CHIP_HASWELL_E_GT1 || \
+ (devid) == PCI_CHIP_HASWELL_SDV_GT1 || \
+ (devid) == PCI_CHIP_HASWELL_SDV_M_GT1 || \
+ (devid) == PCI_CHIP_HASWELL_SDV_S_GT1 || \
++ (devid) == PCI_CHIP_HASWELL_SDV_B_GT1 || \
++ (devid) == PCI_CHIP_HASWELL_SDV_E_GT1 || \
+ (devid) == PCI_CHIP_HASWELL_ULT_GT1 || \
+ (devid) == PCI_CHIP_HASWELL_ULT_M_GT1 || \
+ (devid) == PCI_CHIP_HASWELL_ULT_S_GT1 || \
++ (devid) == PCI_CHIP_HASWELL_ULT_B_GT1 || \
++ (devid) == PCI_CHIP_HASWELL_ULT_E_GT1 || \
+ (devid) == PCI_CHIP_HASWELL_CRW_GT1 || \
+ (devid) == PCI_CHIP_HASWELL_CRW_M_GT1 || \
+- (devid) == PCI_CHIP_HASWELL_CRW_S_GT1)
++ (devid) == PCI_CHIP_HASWELL_CRW_S_GT1 || \
++ (devid) == PCI_CHIP_HASWELL_CRW_B_GT1 || \
++ (devid) == PCI_CHIP_HASWELL_CRW_E_GT1)
+ #define IS_HSW_GT2(devid) ((devid) == PCI_CHIP_HASWELL_GT2 || \
+ (devid) == PCI_CHIP_HASWELL_M_GT2 || \
+ (devid) == PCI_CHIP_HASWELL_S_GT2 || \
++ (devid) == PCI_CHIP_HASWELL_B_GT2 || \
++ (devid) == PCI_CHIP_HASWELL_E_GT2 || \
+ (devid) == PCI_CHIP_HASWELL_SDV_GT2 || \
+ (devid) == PCI_CHIP_HASWELL_SDV_M_GT2 || \
+ (devid) == PCI_CHIP_HASWELL_SDV_S_GT2 || \
++ (devid) == PCI_CHIP_HASWELL_SDV_B_GT2 || \
++ (devid) == PCI_CHIP_HASWELL_SDV_E_GT2 || \
+ (devid) == PCI_CHIP_HASWELL_ULT_GT2 || \
+ (devid) == PCI_CHIP_HASWELL_ULT_M_GT2 || \
+ (devid) == PCI_CHIP_HASWELL_ULT_S_GT2 || \
++ (devid) == PCI_CHIP_HASWELL_ULT_B_GT2 || \
++ (devid) == PCI_CHIP_HASWELL_ULT_E_GT2 || \
+ (devid) == PCI_CHIP_HASWELL_CRW_GT2 || \
+ (devid) == PCI_CHIP_HASWELL_CRW_M_GT2 || \
+- (devid) == PCI_CHIP_HASWELL_CRW_S_GT2)
++ (devid) == PCI_CHIP_HASWELL_CRW_S_GT2 || \
++ (devid) == PCI_CHIP_HASWELL_CRW_B_GT2 || \
++ (devid) == PCI_CHIP_HASWELL_CRW_E_GT2)
+ #define IS_HSW_GT3(devid) ((devid) == PCI_CHIP_HASWELL_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_M_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_S_GT3 || \
++ (devid) == PCI_CHIP_HASWELL_B_GT3 || \
++ (devid) == PCI_CHIP_HASWELL_E_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_SDV_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_SDV_M_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_SDV_S_GT3 || \
++ (devid) == PCI_CHIP_HASWELL_SDV_B_GT3 || \
++ (devid) == PCI_CHIP_HASWELL_SDV_E_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_ULT_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_ULT_M_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_ULT_S_GT3 || \
++ (devid) == PCI_CHIP_HASWELL_ULT_B_GT3 || \
++ (devid) == PCI_CHIP_HASWELL_ULT_E_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_CRW_GT3 || \
+ (devid) == PCI_CHIP_HASWELL_CRW_M_GT3 || \
+- (devid) == PCI_CHIP_HASWELL_CRW_S_GT3)
++ (devid) == PCI_CHIP_HASWELL_CRW_S_GT3 || \
++ (devid) == PCI_CHIP_HASWELL_CRW_B_GT3 || \
++ (devid) == PCI_CHIP_HASWELL_CRW_E_GT3)
+
+ #define IS_HASWELL(devid) (IS_HSW_GT1(devid) || \
+ IS_HSW_GT2(devid) || \
diff --git a/debian/patches/fix-hsw-crw-ids.diff
b/debian/patches/fix-hsw-crw-ids.diff
new file mode 100644
index 0000000..5798236
--- /dev/null
+++ b/debian/patches/fix-hsw-crw-ids.diff
@@ -0,0 +1,40 @@
+commit ca678bc073462623cfc89dea80271bc361f1655f
+Author: Kenneth Graunke <kenn...@whitecape.org>
+Date: Fri Mar 1 15:37:01 2013 -0800
+
+ intel: Fix Haswell CRW PCI IDs.
+
+ The second digit was off by one, which meant we accidentally treated
+ GT(n) as GT(n-1). This also meant no support for GT1 at all.
+
+ Signed-off-by: Kenneth Graunke <kenn...@whitecape.org>
+
+diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
+index 2760dc8..5aea3f2 100644
+--- a/intel/intel_chipset.h
++++ b/intel/intel_chipset.h
+@@ -115,15 +115,15 @@
+ #define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A /* Server */
+ #define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A
+ #define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS 0x0A2A
+-#define PCI_CHIP_HASWELL_CRW_GT1 0x0D12 /* Desktop */
+-#define PCI_CHIP_HASWELL_CRW_GT2 0x0D22
+-#define PCI_CHIP_HASWELL_CRW_GT2_PLUS 0x0D32
+-#define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D16 /* Mobile */
+-#define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D26
+-#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D36
+-#define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D1A /* Server */
+-#define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D2A
+-#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D3A
++#define PCI_CHIP_HASWELL_CRW_GT1 0x0D02 /* Desktop */
++#define PCI_CHIP_HASWELL_CRW_GT2 0x0D12
++#define PCI_CHIP_HASWELL_CRW_GT2_PLUS 0x0D22
++#define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D06 /* Mobile */
++#define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D16
++#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D26
++#define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D0A /* Server */
++#define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D1A
++#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D2A
+
+ #define PCI_CHIP_VALLEYVIEW_PO 0x0f30 /* VLV PO board */
+ #define PCI_CHIP_VALLEYVIEW_1 0x0f31
diff --git a/debian/patches/fix-hsw-gt3-names.diff
b/debian/patches/fix-hsw-gt3-names.diff
new file mode 100644
index 0000000..fc59e02
--- /dev/null
+++ b/debian/patches/fix-hsw-gt3-names.diff
@@ -0,0 +1,110 @@
+commit 150c3555e7ba53f6ad2d3970cca8e4d5970410aa
+Author: Rodrigo Vivi <rodrigo.v...@gmail.com>
+Date: Mon May 13 17:48:39 2013 -0300
+
+ intel: Fix Haswell GT3 names.
+
+ When publishing first HSW ids we weren't allowed to use "GT3" codname.
+ But this is the correct codname and Mesa is using it already.
+ So to avoid people getting confused why in Mesa it is called GT3 and here
+ it is called GT2_PLUS let's fix this name in a standard and correct way.
+
+ Signed-off-by: Rodrigo Vivi <rodrigo.v...@gmail.com>
+ Reviewed-by: Chad Versace <chad.vers...@linux.intel.com>
+ Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
+
+diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
+index 5aea3f2..3350def 100644
+--- a/intel/intel_chipset.h
++++ b/intel/intel_chipset.h
+@@ -90,40 +90,40 @@
+
+ #define PCI_CHIP_HASWELL_GT1 0x0402 /* Desktop */
+ #define PCI_CHIP_HASWELL_GT2 0x0412
+-#define PCI_CHIP_HASWELL_GT2_PLUS 0x0422
++#define PCI_CHIP_HASWELL_GT3 0x0422
+ #define PCI_CHIP_HASWELL_M_GT1 0x0406 /* Mobile */
+ #define PCI_CHIP_HASWELL_M_GT2 0x0416
+-#define PCI_CHIP_HASWELL_M_GT2_PLUS 0x0426
++#define PCI_CHIP_HASWELL_M_GT3 0x0426
+ #define PCI_CHIP_HASWELL_S_GT1 0x040A /* Server */
+ #define PCI_CHIP_HASWELL_S_GT2 0x041A
+-#define PCI_CHIP_HASWELL_S_GT2_PLUS 0x042A
++#define PCI_CHIP_HASWELL_S_GT3 0x042A
+ #define PCI_CHIP_HASWELL_SDV_GT1 0x0C02 /* Desktop */
+ #define PCI_CHIP_HASWELL_SDV_GT2 0x0C12
+-#define PCI_CHIP_HASWELL_SDV_GT2_PLUS 0x0C22
++#define PCI_CHIP_HASWELL_SDV_GT3 0x0C22
+ #define PCI_CHIP_HASWELL_SDV_M_GT1 0x0C06 /* Mobile */
+ #define PCI_CHIP_HASWELL_SDV_M_GT2 0x0C16
+-#define PCI_CHIP_HASWELL_SDV_M_GT2_PLUS 0x0C26
++#define PCI_CHIP_HASWELL_SDV_M_GT3 0x0C26
+ #define PCI_CHIP_HASWELL_SDV_S_GT1 0x0C0A /* Server */
+ #define PCI_CHIP_HASWELL_SDV_S_GT2 0x0C1A
+-#define PCI_CHIP_HASWELL_SDV_S_GT2_PLUS 0x0C2A
++#define PCI_CHIP_HASWELL_SDV_S_GT3 0x0C2A
+ #define PCI_CHIP_HASWELL_ULT_GT1 0x0A02 /* Desktop */
+ #define PCI_CHIP_HASWELL_ULT_GT2 0x0A12
+-#define PCI_CHIP_HASWELL_ULT_GT2_PLUS 0x0A22
++#define PCI_CHIP_HASWELL_ULT_GT3 0x0A22
+ #define PCI_CHIP_HASWELL_ULT_M_GT1 0x0A06 /* Mobile */
+ #define PCI_CHIP_HASWELL_ULT_M_GT2 0x0A16
+-#define PCI_CHIP_HASWELL_ULT_M_GT2_PLUS 0x0A26
++#define PCI_CHIP_HASWELL_ULT_M_GT3 0x0A26
+ #define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A /* Server */
+ #define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A
+-#define PCI_CHIP_HASWELL_ULT_S_GT2_PLUS 0x0A2A
++#define PCI_CHIP_HASWELL_ULT_S_GT3 0x0A2A
+ #define PCI_CHIP_HASWELL_CRW_GT1 0x0D02 /* Desktop */
+ #define PCI_CHIP_HASWELL_CRW_GT2 0x0D12
+-#define PCI_CHIP_HASWELL_CRW_GT2_PLUS 0x0D22
++#define PCI_CHIP_HASWELL_CRW_GT3 0x0D22
+ #define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D06 /* Mobile */
+ #define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D16
+-#define PCI_CHIP_HASWELL_CRW_M_GT2_PLUS 0x0D26
++#define PCI_CHIP_HASWELL_CRW_M_GT3 0x0D26
+ #define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D0A /* Server */
+ #define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D1A
+-#define PCI_CHIP_HASWELL_CRW_S_GT2_PLUS 0x0D2A
++#define PCI_CHIP_HASWELL_CRW_S_GT3 0x0D2A
+
+ #define PCI_CHIP_VALLEYVIEW_PO 0x0f30 /* VLV PO board */
+ #define PCI_CHIP_VALLEYVIEW_1 0x0f31
+@@ -230,22 +230,23 @@
+ (devid) == PCI_CHIP_HASWELL_ULT_S_GT2 || \
+ (devid) == PCI_CHIP_HASWELL_CRW_GT2 || \
+ (devid) == PCI_CHIP_HASWELL_CRW_M_GT2 || \
+- (devid) == PCI_CHIP_HASWELL_CRW_S_GT2 || \
+- (devid) == PCI_CHIP_HASWELL_GT2_PLUS || \
+- (devid) == PCI_CHIP_HASWELL_M_GT2_PLUS || \
+- (devid) == PCI_CHIP_HASWELL_S_GT2_PLUS || \
+- (devid) == PCI_CHIP_HASWELL_SDV_GT2_PLUS || \
+- (devid) == PCI_CHIP_HASWELL_SDV_M_GT2_PLUS || \
+- (devid) == PCI_CHIP_HASWELL_SDV_S_GT2_PLUS || \
+- (devid) == PCI_CHIP_HASWELL_ULT_GT2_PLUS || \
+- (devid) == PCI_CHIP_HASWELL_ULT_M_GT2_PLUS || \
+- (devid) == PCI_CHIP_HASWELL_ULT_S_GT2_PLUS || \
+- (devid) == PCI_CHIP_HASWELL_CRW_GT2_PLUS || \
+- (devid) == PCI_CHIP_HASWELL_CRW_M_GT2_PLUS || \
+- (devid) == PCI_CHIP_HASWELL_CRW_S_GT2_PLUS)
++ (devid) == PCI_CHIP_HASWELL_CRW_S_GT2)
++#define IS_HSW_GT3(devid) ((devid) == PCI_CHIP_HASWELL_GT3 || \
++ (devid) == PCI_CHIP_HASWELL_M_GT3 || \
++ (devid) == PCI_CHIP_HASWELL_S_GT3 || \
++ (devid) == PCI_CHIP_HASWELL_SDV_GT3 || \
++ (devid) == PCI_CHIP_HASWELL_SDV_M_GT3 || \
++ (devid) == PCI_CHIP_HASWELL_SDV_S_GT3 || \
++ (devid) == PCI_CHIP_HASWELL_ULT_GT3 || \
++ (devid) == PCI_CHIP_HASWELL_ULT_M_GT3 || \
++ (devid) == PCI_CHIP_HASWELL_ULT_S_GT3 || \
++ (devid) == PCI_CHIP_HASWELL_CRW_GT3 || \
++ (devid) == PCI_CHIP_HASWELL_CRW_M_GT3 || \
++ (devid) == PCI_CHIP_HASWELL_CRW_S_GT3)
+
+ #define IS_HASWELL(devid) (IS_HSW_GT1(devid) || \
+- IS_HSW_GT2(devid))
++ IS_HSW_GT2(devid) || \
++ IS_HSW_GT3(devid))
+
+ #define IS_9XX(dev) (IS_GEN3(dev) || \
+ IS_GEN4(dev) || \
diff --git a/debian/patches/series b/debian/patches/series
index c17390c..cf85191 100644
--- a/debian/patches/series
+++ b/debian/patches/series
@@ -1,3 +1,6 @@
01_default_perms.diff
03_build_against_librt.diff
04_libdrm-2.4.37-nouveau-1.diff
+fix-hsw-crw-ids.diff
+fix-hsw-gt3-names.diff
+add-more-reserved-hsw-ids.diff
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