Makefile.am | 2
bin/.cherry-ignore | 3
configure.ac | 38 +-
docs/relnotes-9.1.html | 1
src/egl/drivers/dri2/platform_wayland.c | 8
src/gallium/auxiliary/util/u_surface.c | 4
src/gallium/drivers/r600/evergreen_state.c | 31 +
src/gallium/drivers/r600/r600_asm.c | 8
src/gallium/drivers/r600/r600_llvm.c | 2
src/gallium/drivers/r600/r600_state.c | 41 +-
src/gallium/drivers/r600/r600_state_common.c | 5
src/gallium/drivers/radeonsi/radeonsi_pipe.c | 2
src/gallium/drivers/radeonsi/radeonsi_shader.c | 67 +++
src/gallium/drivers/radeonsi/si_state.c | 67 ++-
src/gallium/drivers/softpipe/sp_tex_sample.c | 1
src/gallium/drivers/svga/svga_state_rss.c | 11
src/gallium/state_trackers/egl/Makefile.am | 1
src/gallium/state_trackers/xorg/xorg_exa.c | 2
src/gallium/winsys/radeon/drm/radeon_drm_bo.c | 7
src/glsl/ast_to_hir.cpp | 58 ++-
src/glsl/builtin_compiler/Makefile.am | 43 +-
src/glsl/glsl_types.cpp | 18 +
src/glsl/glsl_types.h | 6
src/glsl/link_uniform_blocks.cpp | 6
src/glsl/link_uniforms.cpp | 24 -
src/glsl/link_varyings.cpp | 227 ++++++++-----
src/glsl/link_varyings.h | 59 +++
src/glsl/linker.cpp | 59 +++
src/glsl/linker.h | 33 -
src/glsl/program.h | 4
src/glx/dri2_glx.c | 8
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 114 +++++-
src/mesa/drivers/dri/i965/brw_context.c | 19 +
src/mesa/drivers/dri/i965/brw_context.h | 8
src/mesa/drivers/dri/i965/brw_fs.cpp | 35 +-
src/mesa/drivers/dri/i965/brw_fs.h | 1
src/mesa/drivers/dri/i965/brw_fs_emit.cpp | 4
src/mesa/drivers/dri/i965/brw_fs_schedule_instructions.cpp | 9
src/mesa/drivers/dri/i965/brw_primitive_restart.c | 4
src/mesa/drivers/dri/i965/brw_state.h | 5
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 20 -
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 18 -
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 19 +
src/mesa/drivers/dri/i965/gen6_sf_state.c | 69 ++-
src/mesa/drivers/dri/i965/gen7_sampler_state.c | 2
src/mesa/drivers/dri/i965/gen7_sf_state.c | 36 +-
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 3
src/mesa/drivers/dri/intel/intel_extensions.c | 4
src/mesa/drivers/dri/intel/intel_fbo.c | 30 +
src/mesa/drivers/dri/intel/intel_fbo.h | 4
src/mesa/drivers/dri/intel/intel_tex_copy.c | 32 +
src/mesa/drivers/osmesa/osmesa.c | 3
src/mesa/drivers/x11/xm_dd.c | 3
src/mesa/main/bufferobj.c | 7
src/mesa/main/extensions.c | 1
src/mesa/main/get_hash_params.py | 4
src/mesa/main/glformats.c | 12
src/mesa/main/pack.c | 26 +
src/mesa/main/renderbuffer.h | 8
src/mesa/main/shaderapi.c | 14
src/mesa/main/texgetimage.c | 92 ++++-
src/mesa/main/teximage.c | 42 +-
src/mesa/main/uniform_query.cpp | 85 +---
src/mesa/main/uniforms.h | 4
src/mesa/main/version.h | 2
src/mesa/program/ir_to_mesa.cpp | 4
src/mesa/state_tracker/st_cb_drawpixels.c | 6
src/mesa/state_tracker/st_cb_texture.c | 2
src/mesa/state_tracker/st_extensions.c | 12
src/mesa/state_tracker/st_format.c | 29 +
src/mesa/state_tracker/st_format.h | 2
src/mesa/state_tracker/st_texture.c | 3
72 files changed, 1196 insertions(+), 447 deletions(-)
New commits:
commit 456cdb6d01bd317e46c4e528f7565269a20001d4
Author: Ian Romanick <ian.d.roman...@intel.com>
Date: Sun Feb 17 14:49:02 2013 -0800
mesa: Bump version to 9.1-rc2
Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
diff --git a/Makefile.am b/Makefile.am
index cc94111..be42097 100644
--- a/Makefile.am
+++ b/Makefile.am
@@ -36,7 +36,7 @@ check-local:
# Rules for making release tarballs
-PACKAGE_VERSION=9.1-rc1
+PACKAGE_VERSION=9.1-rc2
PACKAGE_DIR = Mesa-$(PACKAGE_VERSION)
PACKAGE_NAME = MesaLib-$(PACKAGE_VERSION)
diff --git a/src/mesa/main/version.h b/src/mesa/main/version.h
index 9834560..a99381a 100644
--- a/src/mesa/main/version.h
+++ b/src/mesa/main/version.h
@@ -35,7 +35,7 @@ struct gl_context;
#define MESA_MAJOR 9
#define MESA_MINOR 1
#define MESA_PATCH 0
-#define MESA_VERSION_STRING "9.1-rc1"
+#define MESA_VERSION_STRING "9.1-rc2"
/* To make version comparison easy */
#define MESA_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c))
commit aaee8623052f55fd0237a360784c98dfc10e26f5
Author: Eric Anholt <e...@anholt.net>
Date: Tue Feb 5 15:36:18 2013 -0800
i965/fs: Use a helper function for checking for flow control instructions.
In 2 of our checks, we were missing BREAK and CONTINUE.
NOTE: Candidate for the stable branches.
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
(cherry picked from commit bf91f0b03942d966cf453201dc52c4aa4049f8fa)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 8e57eb0..8dab431 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -328,6 +328,23 @@ fs_inst::is_math()
}
bool
+fs_inst::is_control_flow()
+{
+ switch (opcode) {
+ case BRW_OPCODE_DO:
+ case BRW_OPCODE_WHILE:
+ case BRW_OPCODE_IF:
+ case BRW_OPCODE_ELSE:
+ case BRW_OPCODE_ENDIF:
+ case BRW_OPCODE_BREAK:
+ case BRW_OPCODE_CONTINUE:
+ return true;
+ default:
+ return false;
+ }
+}
+
+bool
fs_inst::is_send_from_grf()
{
return (opcode == FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7 ||
@@ -2070,16 +2087,12 @@ fs_visitor::compute_to_mrf()
break;
}
- /* We don't handle flow control here. Most computation of
+ /* We don't handle control flow here. Most computation of
* values that end up in MRFs are shortly before the MRF
* write anyway.
*/
- if (scan_inst->opcode == BRW_OPCODE_DO ||
- scan_inst->opcode == BRW_OPCODE_WHILE ||
- scan_inst->opcode == BRW_OPCODE_ELSE ||
- scan_inst->opcode == BRW_OPCODE_ENDIF) {
+ if (scan_inst->is_control_flow() && scan_inst->opcode != BRW_OPCODE_IF)
break;
- }
/* You can't read from an MRF, so if someone else reads our
* MRF's source GRF that we wanted to rewrite, that stops us.
@@ -2163,16 +2176,8 @@ fs_visitor::remove_duplicate_mrf_writes()
foreach_list_safe(node, &this->instructions) {
fs_inst *inst = (fs_inst *)node;
- switch (inst->opcode) {
- case BRW_OPCODE_DO:
- case BRW_OPCODE_WHILE:
- case BRW_OPCODE_IF:
- case BRW_OPCODE_ELSE:
- case BRW_OPCODE_ENDIF:
+ if (inst->is_control_flow()) {
memset(last_mrf_move, 0, sizeof(last_mrf_move));
- continue;
- default:
- break;
}
if (inst->opcode == BRW_OPCODE_MOV &&
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b/src/mesa/drivers/dri/i965/brw_fs.h
index d332502..88fecb9 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -178,6 +178,7 @@ public:
bool overwrites_reg(const fs_reg ®);
bool is_tex();
bool is_math();
+ bool is_control_flow();
bool is_send_from_grf();
fs_reg dst;
diff --git a/src/mesa/drivers/dri/i965/brw_fs_schedule_instructions.cpp
b/src/mesa/drivers/dri/i965/brw_fs_schedule_instructions.cpp
index 3fbca6c..c125928 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_schedule_instructions.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_schedule_instructions.cpp
@@ -816,15 +816,8 @@ fs_visitor::schedule_instructions(bool post_reg_alloc)
next_block_header = (fs_inst *)next_block_header->next;
sched.add_inst(inst);
- if (inst->opcode == BRW_OPCODE_IF ||
- inst->opcode == BRW_OPCODE_ELSE ||
- inst->opcode == BRW_OPCODE_ENDIF ||
- inst->opcode == BRW_OPCODE_DO ||
- inst->opcode == BRW_OPCODE_WHILE ||
- inst->opcode == BRW_OPCODE_BREAK ||
- inst->opcode == BRW_OPCODE_CONTINUE) {
+ if (inst->is_control_flow())
break;
- }
}
sched.calculate_deps();
sched.schedule_instructions(next_block_header);
commit b84d9aa0c661753d486bc87bc22198c5798947a8
Author: bma <bo...@windriver.com>
Date: Tue Feb 12 08:42:36 2013 +0200
shaderapi: Fix AttachShader error
Detect a duplicate Shader type as and error instead of silently allowing
it, restrict to ES2 API.
v2: Tapani Pälli <tapani.pa...@intel.com>
- make the check run time instead of compile time
v3: chadv
- Quote spec on which error to generate.
Signed-off-by: bma <bo...@windriver.com>
Signed-off-by: Tapani Pälli <tapani.pa...@intel.com>
Reviewed-and-tested-by: Chad Versace <chad.vers...@linux.intel.com>
(cherry picked from commit ce3dfa19ab27871d7eecd5664c1674e467b736bc)
diff --git a/src/mesa/main/shaderapi.c b/src/mesa/main/shaderapi.c
index 2590abe..be69467 100644
--- a/src/mesa/main/shaderapi.c
+++ b/src/mesa/main/shaderapi.c
@@ -207,6 +207,8 @@ attach_shader(struct gl_context *ctx, GLuint program,
GLuint shader)
struct gl_shader *sh;
GLuint i, n;
+ const bool same_type_disallowed = _mesa_is_gles(ctx);
+
shProg = _mesa_lookup_shader_program_err(ctx, program, "glAttachShader");
if (!shProg)
return;
@@ -227,6 +229,18 @@ attach_shader(struct gl_context *ctx, GLuint program,
GLuint shader)
*/
_mesa_error(ctx, GL_INVALID_OPERATION, "glAttachShader");
return;
+ } else if (same_type_disallowed &&
+ shProg->Shaders[i]->Type == sh->Type) {
+ /* Shader with the same type is already attached to this program,
+ * OpenGL ES 2.0 and 3.0 specs say:
+ *
+ * "Multiple shader objects of the same type may not be attached
+ * to a single program object. [...] The error INVALID_OPERATION
+ * is generated if [...] another shader object of the same type
+ * as shader is already attached to program."
+ */
+ _mesa_error(ctx, GL_INVALID_OPERATION, "glAttachShader");
+ return;
}
}
commit bb4b1494e32b85dc5caa777c391b30b3dda5c785
Author: Eric Anholt <e...@anholt.net>
Date: Wed Feb 6 15:22:45 2013 -0800
i965: Re-enable the -RHW workaround for original gen4 chips.
Fixes broken clipping in supertuxkart and presumably many other
applications.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=51471
NOTE: Candidate for the stable branches.
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
(cherry picked from commit cb4616d32dc85e60dba08d86581dbb0d6d1b7ffa)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index 1863fe5..ae4cf7d 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -2420,18 +2420,14 @@ vec4_visitor::emit_psiz_and_flags(struct brw_reg reg)
* clipped against all fixed planes.
*/
if (brw->has_negative_rhw_bug) {
-#if 0
- /* FINISHME */
- brw_CMP(p,
- vec8(brw_null_reg()),
- BRW_CONDITIONAL_L,
- brw_swizzle1(output_reg[BRW_VERT_RESULT_NDC], 3),
- brw_imm_f(0));
-
- brw_OR(p, brw_writemask(header1, WRITEMASK_W), header1,
brw_imm_ud(1<<6));
- brw_MOV(p, output_reg[BRW_VERT_RESULT_NDC], brw_imm_f(0));
- brw_set_predicate_control(p, BRW_PREDICATE_NONE);
-#endif
+ src_reg ndc_w = src_reg(output_reg[BRW_VERT_RESULT_NDC]);
+ ndc_w.swizzle = BRW_SWIZZLE_WWWW;
+ emit(CMP(dst_null_f(), ndc_w, src_reg(0.0f), BRW_CONDITIONAL_L));
+ vec4_instruction *inst;
+ inst = emit(OR(header1_w, src_reg(header1_w), src_reg(1u << 6)));
+ inst->predicate = BRW_PREDICATE_NORMAL;
+ inst = emit(MOV(output_reg[BRW_VERT_RESULT_NDC], src_reg(0.0f)));
+ inst->predicate = BRW_PREDICATE_NORMAL;
}
emit(MOV(retype(reg, BRW_REGISTER_TYPE_UD), src_reg(header1)));
commit 321abaaa8d6afe56c5de69d32e914a893259e0bc
Author: Eric Anholt <e...@anholt.net>
Date: Tue Feb 5 17:39:35 2013 -0800
i965/gen4: Work around missing sRGB RGB DXT1 support.
The hardware just doesn't support it. I suspect this was a regression from
the move to fixed MESA_FORMATs for compressed textures and that previously
we
were storing uncompressed for this or something.
Fixes GPU hangs in piglit "texwrap GL_EXT_texture_sRGB-s3tc bordercolor
swizzled" on my GM965.
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
(cherry picked from commit ddc2b453d02f2a9460efcc6c6198f56ba89e87fe)
diff --git a/src/mesa/drivers/dri/i965/brw_state.h
b/src/mesa/drivers/dri/i965/brw_state.h
index adc64e3..ecc61c4 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -197,7 +197,8 @@ uint32_t brw_format_for_mesa_format(gl_format mesa_format);
GLuint translate_tex_target(GLenum target);
-GLuint translate_tex_format(gl_format mesa_format,
+GLuint translate_tex_format(struct intel_context *intel,
+ gl_format mesa_format,
GLenum internal_format,
GLenum depth_mode,
GLenum srgb_decode);
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 7f7b7eb..6ec7d71 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -622,7 +622,8 @@ brw_render_target_supported(struct intel_context *intel,
}
GLuint
-translate_tex_format(gl_format mesa_format,
+translate_tex_format(struct intel_context *intel,
+ gl_format mesa_format,
GLenum internal_format,
GLenum depth_mode,
GLenum srgb_decode)
@@ -651,6 +652,17 @@ translate_tex_format(gl_format mesa_format,
*/
return BRW_SURFACEFORMAT_R32G32B32A32_FLOAT;
+ case MESA_FORMAT_SRGB_DXT1:
+ if (intel->gen == 4 && !intel->is_g4x) {
+ /* Work around missing SRGB DXT1 support on original gen4 by just
+ * skipping SRGB decode. It's not worth not supporting sRGB in
+ * general to prevent this.
+ */
+ WARN_ONCE(true, "Demoting sRGB DXT1 texture to non-sRGB\n");
+ mesa_format = MESA_FORMAT_RGB_DXT1;
+ }
+ return brw_format_for_mesa_format(mesa_format);
+
default:
assert(brw_format_for_mesa_format(mesa_format) != 0);
return brw_format_for_mesa_format(mesa_format);
@@ -829,6 +841,7 @@ brw_update_texture_surface(struct gl_context *ctx,
uint32_t *binding_table,
unsigned surf_index)
{
+ struct intel_context *intel = intel_context(ctx);
struct brw_context *brw = brw_context(ctx);
struct gl_texture_object *tObj = ctx->Texture.Unit[unit]._Current;
struct intel_texture_object *intelObj = intel_texture_object(tObj);
@@ -851,7 +864,8 @@ brw_update_texture_surface(struct gl_context *ctx,
surf[0] = (translate_tex_target(tObj->Target) << BRW_SURFACE_TYPE_SHIFT |
BRW_SURFACE_MIPMAPLAYOUT_BELOW << BRW_SURFACE_MIPLAYOUT_SHIFT |
BRW_SURFACE_CUBEFACE_ENABLES |
- (translate_tex_format(mt->format,
+ (translate_tex_format(intel,
+ mt->format,
firstImage->InternalFormat,
tObj->DepthMode,
sampler->sRGBDecode) <<
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index 236d50c..24f1b9c 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -308,7 +308,8 @@ gen7_update_texture_surface(struct gl_context *ctx,
8 * 4, 32, &binding_table[surf_index]);
memset(surf, 0, 8 * 4);
- uint32_t tex_format = translate_tex_format(mt->format,
+ uint32_t tex_format = translate_tex_format(intel,
+ mt->format,
firstImage->InternalFormat,
tObj->DepthMode,
sampler->sRGBDecode);
commit 95f1203a7c4471ba72a5e153659b515c52fefc53
Author: Ian Romanick <ian.d.roman...@intel.com>
Date: Sun Feb 17 14:16:22 2013 -0800
mesa: Add .cherry-ignore for 9.1
Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
diff --git a/bin/.cherry-ignore b/bin/.cherry-ignore
new file mode 100644
index 0000000..829fab9
--- /dev/null
+++ b/bin/.cherry-ignore
@@ -0,0 +1,3 @@
+d60da27273d2cdb68bc32cae2ca66718dab15f27 st/mesa: set ctx->Const.MaxSamples =
0, not 1
+5c86a728d4f688c0fe7fbf9f4b8f88060b65c4ee r600g: fix htile buffer leak
+496928a442cec980b534bc5da2523b3632b21b61 CopyTexImage: Don't check sRGB vs
LINEAR for desktop GL
commit 96fb4d61fb0aee76faad8b8b063ae9a833b2aeab
Author: Christopher James Halse Rogers <r...@ubuntu.com>
Date: Sat Feb 16 16:39:07 2013 +1100
i965: Fix leak in blorp CopyTexSubImage2D
_mesa_delete_renderbuffer does not call the driver-specific
renderbuffer delete function, so the blorp code was leaking the
Intel-specific bits, including some GEM objects.
Call the renderbuffer's ->Delete() method instead, which does the
right thing.
Fixes Unity rapidly sending the machine into the arms of the OOM-killer
Note: This is a candidate for the 9.1 branch.
Reviewed-by: Eric Anholt <e...@anholt.net>
(cherry picked from commit dd599188d2868838541859a76800a8420958d358)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index 3615b09..d1ab7cb 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -337,7 +337,7 @@ brw_blorp_copytexsubimage(struct intel_context *intel,
GLbitfield buffer_bit = 0;
if (!formats_match(buffer_bit, src_irb, dst_irb)) {
- _mesa_delete_renderbuffer(ctx, dst_rb);
+ dst_rb->Delete(ctx, dst_rb);
return false;
}
@@ -387,7 +387,7 @@ brw_blorp_copytexsubimage(struct intel_context *intel,
srcX0, srcY0, dstX0, dstY0, dstX1, dstY1, false, mirror_y);
}
- _mesa_delete_renderbuffer(ctx, dst_rb);
+ dst_rb->Delete(ctx, dst_rb);
return true;
}
commit d8a0439c65ab4fcc87ee1607b98b6efb18491117
Author: Brian Paul <bri...@vmware.com>
Date: Thu Feb 14 12:24:02 2013 -0700
st/mesa: fix format query for GL_ARB_texture_rg
The GL_ARB_texture_rg spec says that we need to support both texturing
and rendering for the GL_RED and GL_RG formats. So move the format
check up into the rendertarget_mapping[] list. Also, add
PIPE_FORMAT_R8_UNORM to the list of formats required.
Note: This is a candidate for the stable branches.
Reviewed-by: Marek Olšák <mar...@gmail.com>
(cherry picked from commit 4be5a067527107a383596c28f14bd76492c1cb4b)
diff --git a/src/mesa/state_tracker/st_extensions.c
b/src/mesa/state_tracker/st_extensions.c
index 8f4bc91..5f03cec 100644
--- a/src/mesa/state_tracker/st_extensions.c
+++ b/src/mesa/state_tracker/st_extensions.c
@@ -421,6 +421,10 @@ void st_init_extensions(struct st_context *st)
{ { o(EXT_texture_integer) },
{ PIPE_FORMAT_R32G32B32A32_UINT,
PIPE_FORMAT_R32G32B32A32_SINT } },
+
+ { { o(ARB_texture_rg) },
+ { PIPE_FORMAT_R8_UNORM,
+ PIPE_FORMAT_R8G8_UNORM } },
};
/* Required: depth stencil and sampler support */
@@ -444,9 +448,6 @@ void st_init_extensions(struct st_context *st)
PIPE_FORMAT_RGTC2_UNORM,
PIPE_FORMAT_RGTC2_SNORM } },
- { { o(ARB_texture_rg) },
- { PIPE_FORMAT_R8G8_UNORM } },
-
{ { o(EXT_texture_compression_latc) },
{ PIPE_FORMAT_LATC1_UNORM,
PIPE_FORMAT_LATC1_SNORM,
commit c785315f3d6b957c6124ce9efafdd47c8d8526a6
Author: Eric Anholt <e...@anholt.net>
Date: Wed Feb 13 21:21:45 2013 -0800
i965/gen7: Set up all samplers even if samplers are sparsely used.
In GLSL, sampler indices are allocated contiguously from 0. But in the
case of ARB_fragment_program (and possibly fixed function), an app that
uses texture 0 and 2 will use sampler indices 0 and 2, so we were only
allocating space for samplers 0 and 1 and setting up sampler 0. We
would read garbage for sampler 2, resulting in flickering textures and
an angry simulator.
Fixes bad rendering in 0 A.D. and ETQW. This was fixed for pre-gen7 by
28f4be9eb91b12a2c6b1db6660cca71a98c486ec
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=25201
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=58680
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
NOTE: This is a candidate for stable branches.
(cherry picked from commit 5bb05c6e6d596d66c177e42a36128d2ca2e300aa)
diff --git a/src/mesa/drivers/dri/i965/gen7_sampler_state.c
b/src/mesa/drivers/dri/i965/gen7_sampler_state.c
index 6f0a757..1fb947f 100644
--- a/src/mesa/drivers/dri/i965/gen7_sampler_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_sampler_state.c
@@ -196,7 +196,7 @@ gen7_upload_samplers(struct brw_context *brw)
GLbitfield SamplersUsed = vs->SamplersUsed | fs->SamplersUsed;
- brw->sampler.count = _mesa_bitcount(SamplersUsed);
+ brw->sampler.count = _mesa_fls(SamplersUsed);
if (brw->sampler.count == 0)
return;
commit 0e3c755ca3b0bcb1fa83fa82165f008f4d1dfafd
Author: Kenneth Graunke <kenn...@whitecape.org>
Date: Sun Feb 10 16:55:19 2013 -0800
i965: Use derived state for Haswell's 3DSTATE_VF packet.
Otherwise, we fail to correctly handle GL_PRIMITIVE_RESTART_FIXED_INDEX.
Fixes gles3conform's primitive_restart_mode test.
NOTE: This is a candidate for the 9.1 branch.
Signed-off-by: Kenneth Graunke <kenn...@whitecape.org>
Reviewed-by: Eric Anholt <e...@anholt.net>
(cherry picked from commit 8cabe26f5dc4c66ae59649cfd7b25f761cda250b)
diff --git a/src/mesa/drivers/dri/i965/brw_primitive_restart.c
b/src/mesa/drivers/dri/i965/brw_primitive_restart.c
index 8c7219d..e6902b4 100644
--- a/src/mesa/drivers/dri/i965/brw_primitive_restart.c
+++ b/src/mesa/drivers/dri/i965/brw_primitive_restart.c
@@ -196,11 +196,11 @@ haswell_upload_cut_index(struct brw_context *brw)
return;
const unsigned cut_index_setting =
- ctx->Array.PrimitiveRestart ? HSW_CUT_INDEX_ENABLE : 0;
+ ctx->Array._PrimitiveRestart ? HSW_CUT_INDEX_ENABLE : 0;
BEGIN_BATCH(2);
OUT_BATCH(_3DSTATE_VF << 16 | cut_index_setting | (2 - 2));
- OUT_BATCH(ctx->Array.RestartIndex);
+ OUT_BATCH(ctx->Array._RestartIndex);
ADVANCE_BATCH();
}
commit 4d11454e902a8ea5132bb767af6540e63b912f81
Author: Brian Paul <bri...@vmware.com>
Date: Mon Feb 11 16:39:42 2013 -0700
util: fix incorrect Z bit masking in util_clear_depth_stencil()
For PIPE_FORMAT_Z24_UNORM_S8_UINT, the Z bits are in the 24
least significant bits.
Fixes http://bugs.freedesktop.org/show_bug.cgi?id=60527
and http://bugs.freedesktop.org/show_bug.cgi?id=60524
and http://bugs.freedesktop.org/show_bug.cgi?id=60047
Note: This is a candidate for the stable branches.
Reviewed-by: Jose Fonseca <jfons...@vmware.com>
(cherry picked from commit 4bfdef87e66bfb2459af570351798d7754ddfb9f)
diff --git a/src/gallium/auxiliary/util/u_surface.c
b/src/gallium/auxiliary/util/u_surface.c
index 37f4815..b948b46 100644
--- a/src/gallium/auxiliary/util/u_surface.c
+++ b/src/gallium/auxiliary/util/u_surface.c
@@ -421,10 +421,10 @@ util_clear_depth_stencil(struct pipe_context *pipe,
else {
uint32_t dst_mask;
if (format == PIPE_FORMAT_Z24_UNORM_S8_UINT)
- dst_mask = 0xffffff00;
+ dst_mask = 0x00ffffff;
else {
assert(format == PIPE_FORMAT_S8_UINT_Z24_UNORM);
- dst_mask = 0xffffff;
+ dst_mask = 0xffffff00;
}
if (clear_flags & PIPE_CLEAR_DEPTH)
dst_mask = ~dst_mask;
commit 9838215f3ce94358a4276fc83fe315b92a33102f
Author: Marek Olšák <mar...@gmail.com>
Date: Wed Feb 6 22:39:53 2013 +0100
mesa: fix GetTexImage if mesa format and internal format don't match
Tested with softpipe only exposing RGBA formats.
NOTE: This is a candidate for the stable branches.
Reviewed-by: Brian Paul <bri...@vmware.com>
(cherry picked from commit cb6470775c0139323bf889d2df2facdbc06a2b09)
diff --git a/src/mesa/main/pack.c b/src/mesa/main/pack.c
index e00ae63..d976e5a 100644
--- a/src/mesa/main/pack.c
+++ b/src/mesa/main/pack.c
@@ -6027,6 +6027,20 @@ _mesa_rebase_rgba_float(GLuint n, GLfloat rgba[][4],
GLenum baseFormat)
rgba[i][ACOMP] = 1.0F;
}
break;
+ case GL_RG:
+ for (i = 0; i < n; i++) {
+ rgba[i][BCOMP] = 0.0F;
+ rgba[i][ACOMP] = 1.0F;
+ }
+ break;
+ case GL_RED:
+ for (i = 0; i < n; i++) {
+ rgba[i][GCOMP] = 0.0F;
+ rgba[i][BCOMP] = 0.0F;
+ rgba[i][ACOMP] = 1.0F;
+ }
+ break;
+
default:
/* no-op */
;
@@ -6070,6 +6084,18 @@ _mesa_rebase_rgba_uint(GLuint n, GLuint rgba[][4],
GLenum baseFormat)
rgba[i][ACOMP] = 1;
}
break;
+ case GL_RG:
+ for (i = 0; i < n; i++) {
+ rgba[i][BCOMP] = 0;
+ rgba[i][ACOMP] = 1;
+ }
+ break;
+ case GL_RED:
+ for (i = 0; i < n; i++) {
+ rgba[i][GCOMP] = 0;
+ rgba[i][BCOMP] = 0;
+ rgba[i][ACOMP] = 1;
+ }
default:
/* no-op */
;
diff --git a/src/mesa/main/texgetimage.c b/src/mesa/main/texgetimage.c
index d1c00e8..7299a4b 100644
--- a/src/mesa/main/texgetimage.c
+++ b/src/mesa/main/texgetimage.c
@@ -367,6 +367,7 @@ get_tex_rgba_uncompressed(struct gl_context *ctx, GLuint
dimensions,
GLuint (*rgba_uint)[4];
GLboolean tex_is_integer =
_mesa_is_format_integer_color(texImage->TexFormat);
GLboolean tex_is_uint = _mesa_is_format_unsigned(texImage->TexFormat);
+ GLenum texBaseFormat = _mesa_get_format_base_format(texImage->TexFormat);
/* Allocate buffer for one row of texels */
rgba = malloc(4 * width * sizeof(GLfloat));
@@ -403,6 +404,50 @@ get_tex_rgba_uncompressed(struct gl_context *ctx, GLuint
dimensions,
*/
rebaseFormat = GL_LUMINANCE_ALPHA; /* this covers GL_LUMINANCE too */
}
+ else if (texImage->_BaseFormat != texBaseFormat) {
+ /* The internal format and the real format differ, so we can't rely
+ * on the unpack functions setting the correct constant values.
+ * (e.g. reading back GL_RGB8 which is actually RGBA won't set alpha=1)
+ */
+ switch (texImage->_BaseFormat) {
+ case GL_RED:
+ if ((texBaseFormat == GL_RGBA ||
+ texBaseFormat == GL_RGB ||
+ texBaseFormat == GL_RG) &&
+ (destBaseFormat == GL_RGBA ||
+ destBaseFormat == GL_RGB ||
+ destBaseFormat == GL_RG ||
+ destBaseFormat == GL_GREEN)) {
+ rebaseFormat = texImage->_BaseFormat;
+ break;
+ }
+ /* fall through */
+ case GL_RG:
+ if ((texBaseFormat == GL_RGBA ||
+ texBaseFormat == GL_RGB) &&
+ (destBaseFormat == GL_RGBA ||
+ destBaseFormat == GL_RGB ||
+ destBaseFormat == GL_BLUE)) {
+ rebaseFormat = texImage->_BaseFormat;
+ break;
+ }
+ /* fall through */
+ case GL_RGB:
+ if (texBaseFormat == GL_RGBA &&
+ (destBaseFormat == GL_RGBA ||
+ destBaseFormat == GL_ALPHA ||
+ destBaseFormat == GL_LUMINANCE_ALPHA)) {
+ rebaseFormat = texImage->_BaseFormat;
+ }
+ break;
+
+ case GL_ALPHA:
+ if (destBaseFormat != GL_ALPHA) {
+ rebaseFormat = texImage->_BaseFormat;
+ }
+ break;
+ }
+ }
for (img = 0; img < depth; img++) {
GLubyte *srcMap;
commit 2e4473d9e324550b6563ac20d6081028bf58cf82
Author: Marek Olšák <mar...@gmail.com>
Date: Wed Feb 6 22:33:55 2013 +0100
mesa: don't use memcpy fast path for GetTexImage if base format is different
The Mesa format can be RGBA8888_REV, the format/type can be
GL_RGBA/GL_UNSIGNED_BYTE, but the actual texture internal format can be
LUMINANCE_ALPHA, INTENSITY, etc. Therefore we should look at the base
internal format as well.
NOTE: This is a candidate for the stable branches.
Reviewed-by: Brian Paul <bri...@vmware.com>
(cherry picked from commit c8379204ab0af97558871fffccdd74c60a41776a)
diff --git a/src/mesa/main/texgetimage.c b/src/mesa/main/texgetimage.c
index 031e04d..d1c00e8 100644
--- a/src/mesa/main/texgetimage.c
+++ b/src/mesa/main/texgetimage.c
@@ -502,16 +502,18 @@ get_tex_memcpy(struct gl_context *ctx, GLenum format,
GLenum type,
{
const GLenum target = texImage->TexObject->Target;
GLboolean memCopy = GL_FALSE;
+ GLenum texBaseFormat = _mesa_get_format_base_format(texImage->TexFormat);
/*
* Check if we can use memcpy to copy from the hardware texture
* format to the user's format/type.
* Note that GL's pixel transfer ops don't apply to glGetTexImage()
*/
- if (target == GL_TEXTURE_1D ||
- target == GL_TEXTURE_2D ||
- target == GL_TEXTURE_RECTANGLE ||
- _mesa_is_cube_face(target)) {
+ if ((target == GL_TEXTURE_1D ||
+ target == GL_TEXTURE_2D ||
+ target == GL_TEXTURE_RECTANGLE ||
+ _mesa_is_cube_face(target)) &&
+ texBaseFormat == texImage->_BaseFormat) {
memCopy = _mesa_format_matches_format_and_type(texImage->TexFormat,
format, type,
ctx->Pack.SwapBytes);
commit 11eb644cc98803b0d04184c62cad6ea1653a42fe
Author: Marek Olšák <mar...@gmail.com>
Date: Wed Feb 6 22:31:44 2013 +0100
mesa: don't use _mesa_base_tex_format for format parameter of GetTexImage
_mesa_base_tex_format doesn't accept GL_BGR and GL_ABGR_EXT, etc.
v2: add a (now hopefully complete) helper function to deal with this
NOTE: This is a candidate for the stable branches.
Reviewed-by: Brian Paul <bri...@vmware.com>
(cherry picked from commit 09a99867abcc65e208959995c794457da6193967)
diff --git a/src/mesa/main/texgetimage.c b/src/mesa/main/texgetimage.c
index 3a550d9..031e04d 100644
--- a/src/mesa/main/texgetimage.c
+++ b/src/mesa/main/texgetimage.c
@@ -311,6 +311,41 @@ get_tex_rgba_compressed(struct gl_context *ctx, GLuint
dimensions,
/**
+ * Return a base GL format given the user-requested format
+ * for glGetTexImage().
+ */
+static GLenum
+_mesa_base_pack_format(GLenum format)
+{
+ switch (format) {
+ case GL_ABGR_EXT:
+ case GL_BGRA:
+ case GL_BGRA_INTEGER:
+ case GL_RGBA_INTEGER:
+ return GL_RGBA;
+ case GL_BGR:
+ case GL_BGR_INTEGER:
+ case GL_RGB_INTEGER:
+ return GL_RGB;
+ case GL_RED_INTEGER:
+ return GL_RED;
+ case GL_GREEN_INTEGER:
+ return GL_GREEN;
+ case GL_BLUE_INTEGER:
+ return GL_BLUE;
+ case GL_ALPHA_INTEGER:
+ return GL_ALPHA;
+ case GL_LUMINANCE_INTEGER_EXT:
+ return GL_LUMINANCE;
+ case GL_LUMINANCE_ALPHA_INTEGER_EXT:
+ return GL_LUMINANCE_ALPHA;
+ default:
+ return format;
+ }
+}
+
+
+/**
* Get an uncompressed color texture image.
*/
static void
@@ -323,7 +358,7 @@ get_tex_rgba_uncompressed(struct gl_context *ctx, GLuint
dimensions,
const gl_format texFormat =
_mesa_get_srgb_format_linear(texImage->TexFormat);
const GLuint width = texImage->Width;
- const GLenum destBaseFormat = _mesa_base_tex_format(ctx, format);
+ GLenum destBaseFormat = _mesa_base_pack_format(format);
GLenum rebaseFormat = GL_NONE;
GLuint height = texImage->Height;
GLuint depth = texImage->Depth;
commit 60bad0ddc3481c4f33b836804a7c9df0b284d7e1
Author: Ian Romanick <ian.d.roman...@intel.com>
Date: Fri Feb 8 18:03:33 2013 -0800
intel: Do not expose OES_compressed_ETC1_RGB8_texture or
ARB_texture_rgb10_a2ui pre-GEN4
Older hardware cannot do ARB_texture_rgb10_a2ui, and the translation
code for OES_compressed_ETC1_RGB8_texture was never implemented in the
i915 driver.
NOTE: This is a candidate for all stable branches.
Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Anuj Phogat <anuj.pho...@gmail.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
(cherry picked from commit 0e2f26d5ea26febd16173aa8bbf7427b090e320f)
diff --git a/src/mesa/drivers/dri/intel/intel_extensions.c
b/src/mesa/drivers/dri/intel/intel_extensions.c
index 6b5f678..4040ac6 100755
--- a/src/mesa/drivers/dri/intel/intel_extensions.c
+++ b/src/mesa/drivers/dri/intel/intel_extensions.c
@@ -86,8 +86,6 @@ intelInitExtensions(struct gl_context *ctx)
ctx->Extensions.TDFX_texture_compression_FXT1 = true;
ctx->Extensions.OES_EGL_image = true;
ctx->Extensions.OES_draw_texture = true;
- ctx->Extensions.OES_compressed_ETC1_RGB8_texture = true;
- ctx->Extensions.ARB_texture_rgb10_a2ui = true;
if (intel->gen >= 6)
ctx->Const.GLSLVersion = 140;
@@ -144,6 +142,7 @@ intelInitExtensions(struct gl_context *ctx)
ctx->Extensions.EXT_packed_float = true;
ctx->Extensions.ARB_texture_compression_rgtc = true;
ctx->Extensions.ARB_texture_rg = true;
+ ctx->Extensions.ARB_texture_rgb10_a2ui = true;
ctx->Extensions.ARB_vertex_type_2_10_10_10_rev = true;
ctx->Extensions.EXT_draw_buffers2 = true;
ctx->Extensions.EXT_framebuffer_sRGB = true;
@@ -157,6 +156,7 @@ intelInitExtensions(struct gl_context *ctx)
ctx->Extensions.ATI_envmap_bumpmap = true;
ctx->Extensions.MESA_texture_array = true;
ctx->Extensions.NV_conditional_render = true;
+ ctx->Extensions.OES_compressed_ETC1_RGB8_texture = true;
ctx->Extensions.OES_standard_derivatives = true;
}
commit d41e9b4d14dab2d1d6633bb461de4074e33fb130
Author: Roland Scheidegger <srol...@vmware.com>
Date: Wed Feb 6 09:29:55 2013 -0800
softpipe: fix using optimized filter function
This optimized filter (when using repeat wrap modes,
linear min/mag/mip filters, pot textures) only applies to 2d textures,
but nothing prevented it from being used for other textures (likely
leading to very bogus sample results).
Note: This is a candidate for the 9.0 branch.
Reviewed-by: Jose Fonseca <jfons...@vmware.com>
(cherry picked from commit 66b6d5121475ecdd6b76ff660e28dfa6cc3f727c)
diff --git a/src/gallium/drivers/softpipe/sp_tex_sample.c
b/src/gallium/drivers/softpipe/sp_tex_sample.c
index ab03290..7f7e5aa 100644
--- a/src/gallium/drivers/softpipe/sp_tex_sample.c
+++ b/src/gallium/drivers/softpipe/sp_tex_sample.c
@@ -2963,6 +2963,7 @@ sp_create_sampler_variant( const struct
pipe_sampler_state *sampler,
case PIPE_TEX_MIPFILTER_LINEAR:
if (key.bits.is_pot &&
+ key.bits.target == PIPE_TEXTURE_2D &&
sampler->min_img_filter == sampler->mag_img_filter &&
sampler->normalized_coords &&
sampler->wrap_s == PIPE_TEX_WRAP_REPEAT &&
commit 60f05f0eef85b2d4cad96ab36e79d980dafcfafc
Author: Kristian Høgsberg <k...@bitplanet.net>
Date: Wed Feb 6 15:41:54 2013 -0500
egl-wayland: Make sure we allocate a back buffer even if nothing was
rendered
At eglSwapBuffer time, we blindly assume we have a back buffer, but the
back buffer only gets allocated when somebody tries to render something.
NOTE: This is a candidate for the 9.0 and 9.1 branches.
https://bugs.freedesktop.org/show_bug.cgi?id=60086
(cherry picked from commit 1fe007399c1ed28b8cef9d4f040164480423f2c9)
diff --git a/src/egl/drivers/dri2/platform_wayland.c
b/src/egl/drivers/dri2/platform_wayland.c
index e9a66af..99d8729 100644
--- a/src/egl/drivers/dri2/platform_wayland.c
+++ b/src/egl/drivers/dri2/platform_wayland.c
@@ -446,6 +446,7 @@ dri2_swap_buffers(_EGLDriver *drv, _EGLDisplay *disp,
_EGLSurface *draw)
{
struct dri2_egl_display *dri2_dpy = dri2_egl_display(disp);
struct dri2_egl_surface *dri2_surf = dri2_egl_surface(draw);
+ __DRIbuffer buffer;
int i, ret = 0;
while (dri2_surf->frame_callback && ret != -1)
@@ -463,6 +464,13 @@ dri2_swap_buffers(_EGLDriver *drv, _EGLDisplay *disp,
_EGLSurface *draw)
if (dri2_surf->color_buffers[i].age > 0)
dri2_surf->color_buffers[i].age++;
+ /* Make sure we have a back buffer in case we're swapping without ever
+ * rendering. */
+ if (get_back_bo(dri2_surf, &buffer) < 0) {
+ _eglError(EGL_BAD_ALLOC, "dri2_swap_buffers");
+ return EGL_FALSE;
+ }
+
dri2_surf->back->age = 1;
dri2_surf->current = dri2_surf->back;
dri2_surf->back = NULL;
commit 714d8b3f8cdfdd1a37cc017b05f469edacc58ffb
Author: Brian Paul <bri...@vmware.com>
Date: Tue Feb 5 12:20:39 2013 -0700
svga: fix sRGB rendering
We weren't emitting the SVGA_RS_OUTPUTGAMMA state so sRGB rendering
didn't work properly.
Fixes piglit's framebuffer-srgb test.
Note: This is a candidate for the stable branches.
Reviewed-by: Jose Fonseca <jfons...@vmware.com>
(cherry picked from commit ff605091579a0dfbb6a6b3ea0e46d6fed28a278b)
diff --git a/src/gallium/drivers/svga/svga_state_rss.c
b/src/gallium/drivers/svga/svga_state_rss.c
index 6a73924..51d36b7 100644
--- a/src/gallium/drivers/svga/svga_state_rss.c
+++ b/src/gallium/drivers/svga/svga_state_rss.c
@@ -23,6 +23,7 @@
*
**********************************************************/
--
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