ChangeLog | 156 +
NEWS | 18
configure.ac | 2
debian/changelog | 6
src/i965_3d.c | 4
src/i965_render.c | 32
src/i965_video.c | 6
src/intel_batchbuffer.c | 6
src/intel_dri.c | 10
src/intel_driver.c | 14
src/intel_driver.h | 8
src/intel_hwmc.c | 6
src/intel_memory.c | 6
src/intel_module.c | 30
src/intel_uxa.c | 8
src/intel_video.c | 48
src/sna/Makefile.am | 1
src/sna/brw/brw_disasm.c | 43
src/sna/brw/brw_eu.c | 2
src/sna/brw/brw_eu.h | 4
src/sna/brw/brw_eu_emit.c | 132 -
src/sna/brw/brw_wm.c | 64
src/sna/g4x_render.c | 3695 -------------------------------------------
src/sna/gen2_render.c | 6
src/sna/gen4_render.c | 284 +--
src/sna/gen5_render.c | 40
src/sna/gen6_render.c | 14
src/sna/gen7_render.c | 20
src/sna/kgem.c | 103 -
src/sna/kgem.h | 6
src/sna/kgem_debug.c | 34
src/sna/kgem_debug_gen6.c | 8
src/sna/sna.h | 2
src/sna/sna_accel.c | 61
src/sna/sna_blt.c | 44
src/sna/sna_display.c | 33
src/sna/sna_dri.c | 4
src/sna/sna_driver.c | 19
src/sna/sna_glyphs.c | 4
src/sna/sna_io.c | 8
src/sna/sna_render.c | 2
src/sna/sna_render.h | 1
src/sna/sna_video.c | 6
src/sna/sna_video_hwmc.c | 16
src/sna/sna_video_overlay.c | 8
src/sna/sna_video_sprite.c | 2
src/sna/sna_video_textured.c | 2
47 files changed, 730 insertions(+), 4298 deletions(-)
New commits:
commit e83eda4e08916a996d1055c7604bb711e74a7702
Author: Timo Aaltonen <tjaal...@ubuntu.com>
Date: Fri Dec 7 10:01:04 2012 +0200
update the changelogs
diff --git a/ChangeLog b/ChangeLog
index ae97de6..fd1c096 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,159 @@
+commit 6f675eeaeade4728af566891b2afbe5b44fbdc2e
+Author: Chris Wilson <ch...@chris-wilson.co.uk>
+Date: Mon Dec 3 10:47:35 2012 +0000
+
+ 2.20.15 release
+
+ Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
+
+commit 37eb7343be1aeeb90a860096756603a577df1a77
+Author: Chris Wilson <ch...@chris-wilson.co.uk>
+Date: Sat Dec 1 09:40:11 2012 +0000
+
+ sna/gen5: Inspired by gen4, reorder the flushing
+
+ This may not be totally safe, but it is a nicer explanation for random
+ single character corruption.
+
+ References: https://bugs.freedesktop.org/show_bug.cgi?id=51422
+ Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
+
+commit a8a99428c14c8aed2082853cc60d0f98a1fa2d86
+Author: Chris Wilson <ch...@chris-wilson.co.uk>
+Date: Sat Dec 1 09:44:49 2012 +0000
+
+ sna/dri: Unknown generations are given the max value and presume
i965_dri.so
+
+ Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
+
+commit 382bb7bf77fca412fdefd7c304f395d1fe9483b5
+Author: Chris Wilson <ch...@chris-wilson.co.uk>
+Date: Fri Nov 30 16:24:30 2012 +0000
+
+ sna/gen6+: Only apply the BLT w/a for self-copies
+
+ Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
+
+commit 1aee8acacfe5869a072d9f20f3b8290b16683260
+Author: Chris Wilson <ch...@chris-wilson.co.uk>
+Date: Fri Nov 30 12:17:25 2012 +0000
+
+ sna: Unify gen4 acceleration again
+
+ After disabling render-to-Y, 965g seems just as happy with the new code
+ paths as g4x.
+
+ Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
+
+commit 5d6dd9c5a7eeb1f879525430ad89ab74d427e469
+Author: Chris Wilson <ch...@chris-wilson.co.uk>
+Date: Fri Nov 30 12:12:49 2012 +0000
+
+ Convert generation counter to octal
+
+ Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
+
+commit 131600020638ef15166361214cd5e1a0c08c2ea6
+Author: Chris Wilson <ch...@chris-wilson.co.uk>
+Date: Fri Nov 30 11:43:56 2012 +0000
+
+ sna: Prevent gen4 from rendering to I915_TILING_Y
+
+ It always seems to end up in a hang...
+
+ Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
+
+commit ee4d1873ff504c2150b51d13864164b02b85dd53
+Author: Chris Wilson <ch...@chris-wilson.co.uk>
+Date: Fri Nov 30 09:52:49 2012 +0000
+
+ sna/g4x: And remove one more flush point
+
+ Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
+
+commit 1b6c1a30723b1d13e9bd3df0b59a8d75639c89be
+Author: Chris Wilson <ch...@chris-wilson.co.uk>
+Date: Fri Nov 30 09:27:57 2012 +0000
+
+ sna: Increase tiling alignment to an even tile
+
+ Seems to help g4x.
+
+ Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
+
+commit 6aeb6fdf75fa322d8f5ffe393337d8195d7a6a62
+Author: Chris Wilson <ch...@chris-wilson.co.uk>
+Date: Fri Nov 30 09:03:53 2012 +0000
+
+ sna/g4x: Remove the flush before the pipelined pointer changes
+
+ This one appears unneeded. Hopefully.
+
+ Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
+
+commit 8be2c6695509809c0ab0c5c014e11dc733f73006
+Author: Chris Wilson <ch...@chris-wilson.co.uk>
+Date: Thu Nov 29 19:56:15 2012 +0000
+
+ sna/g4x: Emit the flush prior to changing pipelined state
+
+ Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
+
+commit 2d5d55702bb8eced32d5b8cb3c0cd125fd99d6dc
+Author: Chris Wilson <ch...@chris-wilson.co.uk>
+Date: Wed Nov 28 15:46:29 2012 +0000
+
+ sna/gen6+: Override PTE cacheability bits for reads
+
+ This is primarily useful for enabling the render cache for reads from
+ scanouts.
+
+ Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
+
+commit 3ed87945c9e83fefcbda053b616856658bf2ac8e
+Author: Chris Wilson <ch...@chris-wilson.co.uk>
+Date: Wed Nov 28 11:05:40 2012 +0000
+
+ sna/gen5+: Disable max-vbo address
+
+ As we do not use this feature, disable it and save the relocation.
+
+ Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
+
+commit b2c9e9da639a134577485f83e0f66f54e2371b98
+Author: Chris Wilson <ch...@chris-wilson.co.uk>
+Date: Tue Nov 27 11:32:11 2012 +0000
+
+ sna/blt: Avoid clobbering common state before converting to a BLT
+
+ In case we need to continue on with the render operation, we need to
+ preserve the existing state.
+
+ Reported-by: Jiri Slaby <jirisl...@gmail.com>
+ References: https://bugs.freedesktop.org/show_bug.cgi?id=57601
+ Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
+
+commit 1e06d19a00f5a5a05369deeb3c5ae15b282c0f92
+Author: Chris Wilson <ch...@chris-wilson.co.uk>
+Date: Mon Nov 26 15:30:09 2012 +0000
+
+ sna: Disable shadow tracking upon regen
+
+ References: https://bugs.freedesktop.org/show_bug.cgi?id=56608
+ References: https://bugs.freedesktop.org/show_bug.cgi?id=52255
+ Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
+
+commit d21ed3a6aba5ae227cc5ecd164f3c18bc48c69af
+Author: Chris Wilson <ch...@chris-wilson.co.uk>
+Date: Mon Nov 26 10:34:28 2012 +0000
+
+ sna: Use a single execobject flag to mark read/write domains
+
+ Slight modification to the proposed API to only pass the simplified
+ domain tracking now performed by the kernel.
+
+ Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
+
commit 7a904ce839933d57176e013cdad147533c33ca2f
Author: Chris Wilson <ch...@chris-wilson.co.uk>
Date: Mon Nov 26 08:48:31 2012 +0000
diff --git a/debian/changelog b/debian/changelog
index e698316..e532d3f 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,3 +1,9 @@
+xserver-xorg-video-intel (2:2.20.15-1) UNRELEASED; urgency=low
+
+ * New upstream release.
+
+ -- Timo Aaltonen <tjaal...@ubuntu.com> Fri, 07 Dec 2012 09:33:39 +0200
+
xserver-xorg-video-intel (2:2.20.14-1) experimental; urgency=low
[ Timo Aaltonen ]
commit 6f675eeaeade4728af566891b2afbe5b44fbdc2e
Author: Chris Wilson <ch...@chris-wilson.co.uk>
Date: Mon Dec 3 10:47:35 2012 +0000
2.20.15 release
Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
diff --git a/NEWS b/NEWS
index 8e48fbb..2809dcb 100644
--- a/NEWS
+++ b/NEWS
@@ -1,3 +1,21 @@
+Release 2.20.15 (2012-12-03)
+============================
+And lo, enabling more of the common acceleration paths for gen4 revealed
+another lurking bug - something is wrong with how we prepare Y-tiling
+surfaces for rendering. For the time being, we can surreptiously disable
+them for gen4 and avoid hitting GPU hangs.
+
+ * Avoid clobbering the render state after failing to convert the
+ operation to use the blitter.
+ https://bugs.freedesktop.org/show_bug.cgi?id=57601
+
+ * Disable shadow tracking upon server regeneration, and so fix a crash
+ if you restart the server whilst a RandR transform (e.g. rotation) is
+ in effect.
+ https://bugs.freedesktop.org/show_bug.cgi?id=52255
+ https://bugs.freedesktop.org/show_bug.cgi?id=56608
+
+
Release 2.20.14 (2012-11-26)
============================
The highlight of this release is gen4, from 965g to gm45. Quite an old
diff --git a/configure.ac b/configure.ac
index 9004ce5..8ada660 100644
--- a/configure.ac
+++ b/configure.ac
@@ -23,7 +23,7 @@
# Initialize Autoconf
AC_PREREQ([2.60])
AC_INIT([xf86-video-intel],
- [2.20.14],
+ [2.20.15],
[https://bugs.freedesktop.org/enter_bug.cgi?product=xorg],
[xf86-video-intel])
AC_CONFIG_SRCDIR([Makefile.am])
commit 37eb7343be1aeeb90a860096756603a577df1a77
Author: Chris Wilson <ch...@chris-wilson.co.uk>
Date: Sat Dec 1 09:40:11 2012 +0000
sna/gen5: Inspired by gen4, reorder the flushing
This may not be totally safe, but it is a nicer explanation for random
single character corruption.
References: https://bugs.freedesktop.org/show_bug.cgi?id=51422
Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
diff --git a/src/sna/gen5_render.c b/src/sna/gen5_render.c
index 7dd6dee..17c221e 100644
--- a/src/sna/gen5_render.c
+++ b/src/sna/gen5_render.c
@@ -1206,12 +1206,12 @@ gen5_align_vertex(struct sna *sna, const struct
sna_composite_op *op)
}
}
-static bool
+static void
gen5_emit_binding_table(struct sna *sna, uint16_t offset)
{
if (!DBG_NO_STATE_CACHE &&
sna->render_state.gen5.surface_table == offset)
- return false;
+ return;
sna->render_state.gen5.surface_table = offset;
@@ -1223,8 +1223,6 @@ gen5_emit_binding_table(struct sna *sna, uint16_t offset)
OUT_BATCH(0); /* sf */
/* Only the PS uses the binding table */
OUT_BATCH(offset*4);
-
- return true;
}
static bool
@@ -1371,23 +1369,21 @@ gen5_emit_state(struct sna *sna,
const struct sna_composite_op *op,
uint16_t offset)
{
- bool flush;
+ if (kgem_bo_is_dirty(op->src.bo) || kgem_bo_is_dirty(op->mask.bo)) {
+ DBG(("%s: flushing dirty (%d, %d)\n", __FUNCTION__,
+ kgem_bo_is_dirty(op->src.bo),
+ kgem_bo_is_dirty(op->mask.bo)));
+ OUT_BATCH(MI_FLUSH);
+ kgem_clear_dirty(&sna->kgem);
+ kgem_bo_mark_dirty(op->dst.bo);
+ }
/* drawrect must be first for Ironlake BLT workaround */
gen5_emit_drawing_rectangle(sna, op);
-
- flush = gen5_emit_binding_table(sna, offset);
- if (gen5_emit_pipelined_pointers(sna, op, op->op,
op->u.gen5.wm_kernel)) {
+ gen5_emit_binding_table(sna, offset);
+ if (gen5_emit_pipelined_pointers(sna, op, op->op, op->u.gen5.wm_kernel))
gen5_emit_urb(sna);
- flush = true;
- }
gen5_emit_vertex_elements(sna, op);
-
- if (flush || kgem_bo_is_dirty(op->src.bo) ||
kgem_bo_is_dirty(op->mask.bo)) {
- OUT_BATCH(MI_FLUSH);
- kgem_clear_dirty(&sna->kgem);
- kgem_bo_mark_dirty(op->dst.bo);
- }
}
static void gen5_bind_surfaces(struct sna *sna,
commit a8a99428c14c8aed2082853cc60d0f98a1fa2d86
Author: Chris Wilson <ch...@chris-wilson.co.uk>
Date: Sat Dec 1 09:44:49 2012 +0000
sna/dri: Unknown generations are given the max value and presume i965_dri.so
Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
diff --git a/src/sna/sna_dri.c b/src/sna/sna_dri.c
index 2568c6b..6976143 100644
--- a/src/sna/sna_dri.c
+++ b/src/sna/sna_dri.c
@@ -2419,7 +2419,7 @@ static const char *dri_driver_name(struct sna *sna)
Bool dummy;
if (s == NULL || xf86getBoolValue(&dummy, s))
- return (sna->kgem.gen && sna->kgem.gen < 040) ? "i915" : "i965";
+ return sna->kgem.gen < 040 ? "i915" : "i965";
return s;
}
commit 382bb7bf77fca412fdefd7c304f395d1fe9483b5
Author: Chris Wilson <ch...@chris-wilson.co.uk>
Date: Fri Nov 30 16:24:30 2012 +0000
sna/gen6+: Only apply the BLT w/a for self-copies
Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
diff --git a/src/sna/sna_blt.c b/src/sna/sna_blt.c
index ef8b4f1..2248c4d 100644
--- a/src/sna/sna_blt.c
+++ b/src/sna/sna_blt.c
@@ -1256,7 +1256,7 @@ prepare_blt_copy(struct sna *sna,
DBG(("%s\n", __FUNCTION__));
- if (sna->kgem.gen >= 060)
+ if (sna->kgem.gen >= 060 && op->dst.bo == bo)
op->done = gen6_blt_copy_done;
else
op->done = nop_done;
@@ -1942,7 +1942,7 @@ static void convert_done(struct sna *sna, const struct
sna_composite_op *op)
{
struct kgem *kgem = &sna->kgem;
- if (kgem->gen >= 060 && kgem_check_batch(kgem, 3)) {
+ if (kgem->gen >= 060 && op->src.bo == op->dst.bo &&
kgem_check_batch(kgem, 3)) {
uint32_t *b = kgem->batch + kgem->nbatch;
b[0] = XY_SETUP_CLIP;
b[1] = b[2] = 0;
@@ -2185,7 +2185,7 @@ bool sna_blt_copy(struct sna *sna, uint8_t alu,
return false;
op->blt = sna_blt_copy_op_blt;
- if (sna->kgem.gen >= 060)
+ if (sna->kgem.gen >= 060 && src == dst)
op->done = gen6_blt_copy_op_done;
else
op->done = sna_blt_copy_op_done;
commit 1aee8acacfe5869a072d9f20f3b8290b16683260
Author: Chris Wilson <ch...@chris-wilson.co.uk>
Date: Fri Nov 30 12:17:25 2012 +0000
sna: Unify gen4 acceleration again
After disabling render-to-Y, 965g seems just as happy with the new code
paths as g4x.
Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
diff --git a/src/sna/Makefile.am b/src/sna/Makefile.am
index 9f3d579..306996b 100644
--- a/src/sna/Makefile.am
+++ b/src/sna/Makefile.am
@@ -72,7 +72,6 @@ libsna_la_SOURCES = \
gen3_render.c \
gen3_render.h \
gen4_render.c \
- g4x_render.c \
gen4_render.h \
gen5_render.c \
gen5_render.h \
diff --git a/src/sna/g4x_render.c b/src/sna/g4x_render.c
deleted file mode 100644
index 70faab7..0000000
--- a/src/sna/g4x_render.c
+++ /dev/null
@@ -1,3693 +0,0 @@
-/*
- * Copyright © 2006,2008,2011 Intel Corporation
- * Copyright © 2007 Red Hat, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM,
- * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE
- * SOFTWARE.
- *
- * Authors:
- * Wang Zhenyu <zhenyu.z.w...@sna.com>
- * Eric Anholt <e...@anholt.net>
- * Carl Worth <cwo...@redhat.com>
- * Keith Packard <kei...@keithp.com>
- * Chris Wilson <ch...@chris-wilson.co.uk>
- *
- */
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include "sna.h"
-#include "sna_reg.h"
-#include "sna_render.h"
-#include "sna_render_inline.h"
-#include "sna_video.h"
-
-#include "brw/brw.h"
-#include "gen4_render.h"
-
-/* gen4 has a serious issue with its shaders that we need to flush
- * after every rectangle... So until that is resolved, prefer
- * the BLT engine.
- */
-#define PREFER_BLT 1
-#define FORCE_SPANS 0
-
-#define NO_COMPOSITE 0
-#define NO_COMPOSITE_SPANS 0
-#define NO_COPY 0
-#define NO_COPY_BOXES 0
-#define NO_FILL 0
-#define NO_FILL_ONE 0
-#define NO_FILL_BOXES 0
-#define NO_VIDEO 0
-
-#define GEN4_GRF_BLOCKS(nreg) ((nreg + 15) / 16 - 1)
-
-/* Set up a default static partitioning of the URB, which is supposed to
- * allow anything we would want to do, at potentially lower performance.
- */
-#define URB_CS_ENTRY_SIZE 1
-#define URB_CS_ENTRIES 0
-
-#define URB_VS_ENTRY_SIZE 1
-#define URB_VS_ENTRIES 32
-
-#define URB_GS_ENTRY_SIZE 0
-#define URB_GS_ENTRIES 0
-
-#define URB_CLIP_ENTRY_SIZE 0
-#define URB_CLIP_ENTRIES 0
-
-#define URB_SF_ENTRY_SIZE 2
-#define URB_SF_ENTRIES 64
-
-/*
- * this program computes dA/dx and dA/dy for the texture coordinates along
- * with the base texture coordinate. It was extracted from the Mesa driver
- */
-
-#define SF_KERNEL_NUM_GRF 16
-#define PS_KERNEL_NUM_GRF 32
-
-#define G4X_MAX_SF_THREADS 24
-#define G4X_MAX_WM_THREADS 50
-
-static const uint32_t ps_kernel_packed_static[][4] = {
-#include "exa_wm_xy.g4b"
-#include "exa_wm_src_affine.g4b"
-#include "exa_wm_src_sample_argb.g4b"
-#include "exa_wm_yuv_rgb.g4b"
-#include "exa_wm_write.g4b"
-};
-
-static const uint32_t ps_kernel_planar_static[][4] = {
-#include "exa_wm_xy.g4b"
-#include "exa_wm_src_affine.g4b"
-#include "exa_wm_src_sample_planar.g4b"
-#include "exa_wm_yuv_rgb.g4b"
-#include "exa_wm_write.g4b"
-};
-
-#define NOKERNEL(kernel_enum, func, masked) \
- [kernel_enum] = {func, 0, masked}
-#define KERNEL(kernel_enum, kernel, masked) \
- [kernel_enum] = {&kernel, sizeof(kernel), masked}
-static const struct wm_kernel_info {
- const void *data;
- unsigned int size;
- bool has_mask;
-} wm_kernels[] = {
- NOKERNEL(WM_KERNEL, brw_wm_kernel__affine, false),
- NOKERNEL(WM_KERNEL_P, brw_wm_kernel__projective, false),
-
- NOKERNEL(WM_KERNEL_MASK, brw_wm_kernel__affine_mask, true),
- NOKERNEL(WM_KERNEL_MASK_P, brw_wm_kernel__projective_mask, true),
-
- NOKERNEL(WM_KERNEL_MASKCA, brw_wm_kernel__affine_mask_ca, true),
- NOKERNEL(WM_KERNEL_MASKCA_P, brw_wm_kernel__projective_mask_ca, true),
-
- NOKERNEL(WM_KERNEL_MASKSA, brw_wm_kernel__affine_mask_sa, true),
- NOKERNEL(WM_KERNEL_MASKSA_P, brw_wm_kernel__projective_mask_sa, true),
-
- NOKERNEL(WM_KERNEL_OPACITY, brw_wm_kernel__affine_opacity, true),
- NOKERNEL(WM_KERNEL_OPACITY_P, brw_wm_kernel__projective_opacity, true),
-
- KERNEL(WM_KERNEL_VIDEO_PLANAR, ps_kernel_planar_static, false),
- KERNEL(WM_KERNEL_VIDEO_PACKED, ps_kernel_packed_static, false),
-};
-#undef KERNEL
-
-static const struct blendinfo {
- bool src_alpha;
- uint32_t src_blend;
- uint32_t dst_blend;
-} g4x_blend_op[] = {
- /* Clear */ {0, GEN4_BLENDFACTOR_ZERO, GEN4_BLENDFACTOR_ZERO},
- /* Src */ {0, GEN4_BLENDFACTOR_ONE, GEN4_BLENDFACTOR_ZERO},
- /* Dst */ {0, GEN4_BLENDFACTOR_ZERO, GEN4_BLENDFACTOR_ONE},
- /* Over */ {1, GEN4_BLENDFACTOR_ONE,
GEN4_BLENDFACTOR_INV_SRC_ALPHA},
- /* OverReverse */ {0, GEN4_BLENDFACTOR_INV_DST_ALPHA,
GEN4_BLENDFACTOR_ONE},
- /* In */ {0, GEN4_BLENDFACTOR_DST_ALPHA, GEN4_BLENDFACTOR_ZERO},
- /* InReverse */ {1, GEN4_BLENDFACTOR_ZERO, GEN4_BLENDFACTOR_SRC_ALPHA},
- /* Out */ {0, GEN4_BLENDFACTOR_INV_DST_ALPHA,
GEN4_BLENDFACTOR_ZERO},
- /* OutReverse */ {1, GEN4_BLENDFACTOR_ZERO,
GEN4_BLENDFACTOR_INV_SRC_ALPHA},
- /* Atop */ {1, GEN4_BLENDFACTOR_DST_ALPHA,
GEN4_BLENDFACTOR_INV_SRC_ALPHA},
- /* AtopReverse */ {1, GEN4_BLENDFACTOR_INV_DST_ALPHA,
GEN4_BLENDFACTOR_SRC_ALPHA},
- /* Xor */ {1, GEN4_BLENDFACTOR_INV_DST_ALPHA,
GEN4_BLENDFACTOR_INV_SRC_ALPHA},
- /* Add */ {0, GEN4_BLENDFACTOR_ONE, GEN4_BLENDFACTOR_ONE},
-};
-
-/**
- * Highest-valued BLENDFACTOR used in g4x_blend_op.
- *
- * This leaves out GEN4_BLENDFACTOR_INV_DST_COLOR,
- * GEN4_BLENDFACTOR_INV_CONST_{COLOR,ALPHA},
- * GEN4_BLENDFACTOR_INV_SRC1_{COLOR,ALPHA}
- */
-#define GEN4_BLENDFACTOR_COUNT (GEN4_BLENDFACTOR_INV_DST_ALPHA + 1)
-
-#define BLEND_OFFSET(s, d) \
- (((s) * GEN4_BLENDFACTOR_COUNT + (d)) * 64)
-
-#define SAMPLER_OFFSET(sf, se, mf, me, k) \
- ((((((sf) * EXTEND_COUNT + (se)) * FILTER_COUNT + (mf)) * EXTEND_COUNT
+ (me)) * KERNEL_COUNT + (k)) * 64)
-
-static void
-g4x_emit_pipelined_pointers(struct sna *sna,
- const struct sna_composite_op *op,
- int blend, int kernel);
-
-#define OUT_BATCH(v) batch_emit(sna, v)
-#define OUT_VERTEX(x,y) vertex_emit_2s(sna, x,y)
-#define OUT_VERTEX_F(v) vertex_emit(sna, v)
-
-#define GEN4_MAX_3D_SIZE 8192
-
-static inline bool too_large(int width, int height)
-{
- return width > GEN4_MAX_3D_SIZE || height > GEN4_MAX_3D_SIZE;
-}
-
-static int
-g4x_choose_composite_kernel(int op, bool has_mask, bool is_ca, bool is_affine)
-{
- int base;
-
- if (has_mask) {
- if (is_ca) {
- if (g4x_blend_op[op].src_alpha)
- base = WM_KERNEL_MASKSA;
- else
- base = WM_KERNEL_MASKCA;
- } else
- base = WM_KERNEL_MASK;
- } else
- base = WM_KERNEL;
-
- return base + !is_affine;
-}
-
-static void g4x_magic_ca_pass(struct sna *sna,
- const struct sna_composite_op *op)
-{
- struct gen4_render_state *state = &sna->render_state.gen4;
-
- if (!op->need_magic_ca_pass)
- return;
-
- DBG(("%s: CA fixup\n", __FUNCTION__));
- assert(op->mask.bo != NULL);
- assert(op->has_component_alpha);
-
- g4x_emit_pipelined_pointers(sna, op, PictOpAdd,
- g4x_choose_composite_kernel(PictOpAdd,
- true, true,
op->is_affine));
-
- OUT_BATCH(GEN4_3DPRIMITIVE |
- GEN4_3DPRIMITIVE_VERTEX_SEQUENTIAL |
- (_3DPRIM_RECTLIST << GEN4_3DPRIMITIVE_TOPOLOGY_SHIFT) |
- (0 << 9) |
- 4);
- OUT_BATCH(sna->render.vertex_index - sna->render.vertex_start);
- OUT_BATCH(sna->render.vertex_start);
- OUT_BATCH(1); /* single instance */
- OUT_BATCH(0); /* start instance location */
- OUT_BATCH(0); /* index buffer offset, ignored */
-
- state->last_primitive = sna->kgem.nbatch;
-}
-
-static void g4x_vertex_flush(struct sna *sna)
-{
- if (sna->render_state.gen4.vertex_offset == 0)
- return;
-
- DBG(("%s[%x] = %d\n", __FUNCTION__,
- 4*sna->render_state.gen4.vertex_offset,
- sna->render.vertex_index - sna->render.vertex_start));
- sna->kgem.batch[sna->render_state.gen4.vertex_offset] =
- sna->render.vertex_index - sna->render.vertex_start;
- sna->render_state.gen4.vertex_offset = 0;
-}
-
-static int g4x_vertex_finish(struct sna *sna)
-{
- struct kgem_bo *bo;
- unsigned int i;
-
- assert(sna->render.vertex_used);
- assert(sna->render.nvertex_reloc);
-
- /* Note: we only need dword alignment (currently) */
-
- bo = sna->render.vbo;
- if (bo) {
- g4x_vertex_flush(sna);
-
- for (i = 0; i < sna->render.nvertex_reloc; i++) {
- DBG(("%s: reloc[%d] = %d\n", __FUNCTION__,
- i, sna->render.vertex_reloc[i]));
-
- sna->kgem.batch[sna->render.vertex_reloc[i]] =
- kgem_add_reloc(&sna->kgem,
- sna->render.vertex_reloc[i], bo,
- I915_GEM_DOMAIN_VERTEX << 16,
- 0);
- }
-
- sna->render.vbo = NULL;
- sna->render.nvertex_reloc = 0;
- sna->render.vertex_used = 0;
- sna->render.vertex_index = 0;
- sna->render_state.gen4.vb_id = 0;
-
- kgem_bo_destroy(&sna->kgem, bo);
- }
-
- sna->render.vertices = NULL;
- sna->render.vbo = kgem_create_linear(&sna->kgem,
- 256*1024, CREATE_GTT_MAP);
- if (sna->render.vbo)
- sna->render.vertices = kgem_bo_map(&sna->kgem, sna->render.vbo);
- if (sna->render.vertices == NULL) {
- if (sna->render.vbo)
- kgem_bo_destroy(&sna->kgem, sna->render.vbo);
- sna->render.vbo = NULL;
- return 0;
- }
-
- if (sna->render.vertex_used) {
- memcpy(sna->render.vertices,
- sna->render.vertex_data,
- sizeof(float)*sna->render.vertex_used);
- }
- sna->render.vertex_size = 64 * 1024 - 1;
- return sna->render.vertex_size - sna->render.vertex_used;
-}
-
-static void g4x_vertex_close(struct sna *sna)
-{
- struct kgem_bo *bo, *free_bo = NULL;
- unsigned int i, delta = 0;
-
- assert(sna->render_state.gen4.vertex_offset == 0);
- if (!sna->render_state.gen4.vb_id)
- return;
-
- DBG(("%s: used=%d, vbo active? %d\n",
- __FUNCTION__, sna->render.vertex_used, sna->render.vbo != NULL));
-
- bo = sna->render.vbo;
- if (bo) {
- if (sna->render.vertex_size - sna->render.vertex_used < 64) {
- DBG(("%s: discarding full vbo\n", __FUNCTION__));
- sna->render.vbo = NULL;
- sna->render.vertices = sna->render.vertex_data;
- sna->render.vertex_size =
ARRAY_SIZE(sna->render.vertex_data);
- free_bo = bo;
- } else if (IS_CPU_MAP(bo->map)) {
- DBG(("%s: converting CPU map to GTT\n", __FUNCTION__));
- sna->render.vertices =
- kgem_bo_map__gtt(&sna->kgem, sna->render.vbo);
- if (sna->render.vertices == NULL) {
- sna->render.vbo = NULL;
- sna->render.vertices = sna->render.vertex_data;
- sna->render.vertex_size =
ARRAY_SIZE(sna->render.vertex_data);
- free_bo = bo;
- }
- }
- } else {
- if (sna->kgem.nbatch + sna->render.vertex_used <=
sna->kgem.surface) {
- DBG(("%s: copy to batch: %d @ %d\n", __FUNCTION__,
- sna->render.vertex_used, sna->kgem.nbatch));
- memcpy(sna->kgem.batch + sna->kgem.nbatch,
- sna->render.vertex_data,
- sna->render.vertex_used * 4);
- delta = sna->kgem.nbatch * 4;
- bo = NULL;
- sna->kgem.nbatch += sna->render.vertex_used;
- } else {
- bo = kgem_create_linear(&sna->kgem,
- 4*sna->render.vertex_used, 0);
- if (bo && !kgem_bo_write(&sna->kgem, bo,
- sna->render.vertex_data,
- 4*sna->render.vertex_used)) {
- kgem_bo_destroy(&sna->kgem, bo);
- bo = NULL;
- }
- DBG(("%s: new vbo: %d\n", __FUNCTION__,
- sna->render.vertex_used));
- free_bo = bo;
- }
- }
-
- assert(sna->render.nvertex_reloc);
- for (i = 0; i < sna->render.nvertex_reloc; i++) {
- DBG(("%s: reloc[%d] = %d\n", __FUNCTION__,
- i, sna->render.vertex_reloc[i]));
-
- sna->kgem.batch[sna->render.vertex_reloc[i]] =
- kgem_add_reloc(&sna->kgem,
- sna->render.vertex_reloc[i], bo,
- I915_GEM_DOMAIN_VERTEX << 16,
- delta);
- }
- sna->render.nvertex_reloc = 0;
-
- if (sna->render.vbo == NULL) {
- sna->render.vertex_used = 0;
- sna->render.vertex_index = 0;
- }
-
- if (free_bo)
- kgem_bo_destroy(&sna->kgem, free_bo);
-}
-
-
-static uint32_t g4x_get_blend(int op,
- bool has_component_alpha,
- uint32_t dst_format)
-{
- uint32_t src, dst;
-
- src = g4x_blend_op[op].src_blend;
- dst = g4x_blend_op[op].dst_blend;
-
- /* If there's no dst alpha channel, adjust the blend op so that we'll
treat
- * it as always 1.
- */
- if (PICT_FORMAT_A(dst_format) == 0) {
- if (src == GEN4_BLENDFACTOR_DST_ALPHA)
- src = GEN4_BLENDFACTOR_ONE;
- else if (src == GEN4_BLENDFACTOR_INV_DST_ALPHA)
- src = GEN4_BLENDFACTOR_ZERO;
- }
-
- /* If the source alpha is being used, then we should only be in a
- * case where the source blend factor is 0, and the source blend
- * value is the mask channels multiplied by the source picture's alpha.
- */
- if (has_component_alpha && g4x_blend_op[op].src_alpha) {
- if (dst == GEN4_BLENDFACTOR_SRC_ALPHA)
- dst = GEN4_BLENDFACTOR_SRC_COLOR;
- else if (dst == GEN4_BLENDFACTOR_INV_SRC_ALPHA)
- dst = GEN4_BLENDFACTOR_INV_SRC_COLOR;
- }
-
- DBG(("blend op=%d, dst=%x [A=%d] => src=%d, dst=%d => offset=%x\n",
- op, dst_format, PICT_FORMAT_A(dst_format),
- src, dst, BLEND_OFFSET(src, dst)));
- return BLEND_OFFSET(src, dst);
-}
-
-static uint32_t g4x_get_card_format(PictFormat format)
-{
- switch (format) {
- default:
- return -1;
- case PICT_a8r8g8b8:
- return GEN4_SURFACEFORMAT_B8G8R8A8_UNORM;
- case PICT_x8r8g8b8:
- return GEN4_SURFACEFORMAT_B8G8R8X8_UNORM;
- case PICT_a8b8g8r8:
- return GEN4_SURFACEFORMAT_R8G8B8A8_UNORM;
- case PICT_x8b8g8r8:
- return GEN4_SURFACEFORMAT_R8G8B8X8_UNORM;
- case PICT_a2r10g10b10:
- return GEN4_SURFACEFORMAT_B10G10R10A2_UNORM;
- case PICT_x2r10g10b10:
- return GEN4_SURFACEFORMAT_B10G10R10X2_UNORM;
- case PICT_r8g8b8:
- return GEN4_SURFACEFORMAT_R8G8B8_UNORM;
- case PICT_r5g6b5:
- return GEN4_SURFACEFORMAT_B5G6R5_UNORM;
- case PICT_a1r5g5b5:
- return GEN4_SURFACEFORMAT_B5G5R5A1_UNORM;
- case PICT_a8:
- return GEN4_SURFACEFORMAT_A8_UNORM;
- case PICT_a4r4g4b4:
- return GEN4_SURFACEFORMAT_B4G4R4A4_UNORM;
- }
-}
-
-static uint32_t g4x_get_dest_format(PictFormat format)
-{
- switch (format) {
- default:
- return -1;
- case PICT_a8r8g8b8:
- case PICT_x8r8g8b8:
- return GEN4_SURFACEFORMAT_B8G8R8A8_UNORM;
- case PICT_a8b8g8r8:
- case PICT_x8b8g8r8:
- return GEN4_SURFACEFORMAT_R8G8B8A8_UNORM;
- case PICT_a2r10g10b10:
- case PICT_x2r10g10b10:
- return GEN4_SURFACEFORMAT_B10G10R10A2_UNORM;
- case PICT_r5g6b5:
- return GEN4_SURFACEFORMAT_B5G6R5_UNORM;
- case PICT_x1r5g5b5:
- case PICT_a1r5g5b5:
- return GEN4_SURFACEFORMAT_B5G5R5A1_UNORM;
- case PICT_a8:
- return GEN4_SURFACEFORMAT_A8_UNORM;
- case PICT_a4r4g4b4:
- case PICT_x4r4g4b4:
- return GEN4_SURFACEFORMAT_B4G4R4A4_UNORM;
- }
-}
-
-static bool g4x_check_dst_format(PictFormat format)
-{
- if (g4x_get_dest_format(format) != -1)
- return true;
-
- DBG(("%s: unhandled format: %x\n", __FUNCTION__, (int)format));
- return false;
-}
-
-static bool g4x_check_format(uint32_t format)
-{
- if (g4x_get_card_format(format) != -1)
- return true;
-
- DBG(("%s: unhandled format: %x\n", __FUNCTION__, (int)format));
- return false;
-}
-
-typedef struct gen4_surface_state_padded {
- struct gen4_surface_state state;
- char pad[32 - sizeof(struct gen4_surface_state)];
-} gen4_surface_state_padded;
-
-static void null_create(struct sna_static_stream *stream)
-{
- /* A bunch of zeros useful for legacy border color and depth-stencil */
- sna_static_stream_map(stream, 64, 64);
-}
-
-static void
-sampler_state_init(struct gen4_sampler_state *sampler_state,
- sampler_filter_t filter,
- sampler_extend_t extend)
-{
- sampler_state->ss0.lod_preclamp = 1; /* GL mode */
-
- /* We use the legacy mode to get the semantics specified by
- * the Render extension. */
- sampler_state->ss0.border_color_mode = GEN4_BORDER_COLOR_MODE_LEGACY;
-
- switch (filter) {
- default:
- case SAMPLER_FILTER_NEAREST:
- sampler_state->ss0.min_filter = GEN4_MAPFILTER_NEAREST;
- sampler_state->ss0.mag_filter = GEN4_MAPFILTER_NEAREST;
- break;
- case SAMPLER_FILTER_BILINEAR:
- sampler_state->ss0.min_filter = GEN4_MAPFILTER_LINEAR;
- sampler_state->ss0.mag_filter = GEN4_MAPFILTER_LINEAR;
- break;
- }
-
- switch (extend) {
- default:
- case SAMPLER_EXTEND_NONE:
- sampler_state->ss1.r_wrap_mode = GEN4_TEXCOORDMODE_CLAMP_BORDER;
- sampler_state->ss1.s_wrap_mode = GEN4_TEXCOORDMODE_CLAMP_BORDER;
- sampler_state->ss1.t_wrap_mode = GEN4_TEXCOORDMODE_CLAMP_BORDER;
- break;
- case SAMPLER_EXTEND_REPEAT:
- sampler_state->ss1.r_wrap_mode = GEN4_TEXCOORDMODE_WRAP;
- sampler_state->ss1.s_wrap_mode = GEN4_TEXCOORDMODE_WRAP;
- sampler_state->ss1.t_wrap_mode = GEN4_TEXCOORDMODE_WRAP;
- break;
- case SAMPLER_EXTEND_PAD:
- sampler_state->ss1.r_wrap_mode = GEN4_TEXCOORDMODE_CLAMP;
- sampler_state->ss1.s_wrap_mode = GEN4_TEXCOORDMODE_CLAMP;
- sampler_state->ss1.t_wrap_mode = GEN4_TEXCOORDMODE_CLAMP;
- break;
- case SAMPLER_EXTEND_REFLECT:
- sampler_state->ss1.r_wrap_mode = GEN4_TEXCOORDMODE_MIRROR;
- sampler_state->ss1.s_wrap_mode = GEN4_TEXCOORDMODE_MIRROR;
- sampler_state->ss1.t_wrap_mode = GEN4_TEXCOORDMODE_MIRROR;
- break;
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