ChangeLog | 273 ++
configure.ac | 4
debian/README.source | 6
debian/changelog | 8
debian/libdrm-intel1.symbols | 7
debian/libdrm2.symbols | 5
debian/rules | 4
include/drm/Makefile.am | 1
include/drm/drm.h | 4
include/drm/drm_fourcc.h | 130 +
include/drm/drm_mode.h | 64
include/drm/i915_drm.h | 6
intel/.gitignore | 1
intel/Makefile.am | 30
intel/intel_bufmgr.h | 14
intel/intel_bufmgr_gem.c | 19
intel/intel_chipset.h | 112 -
intel/intel_decode.c | 3691 ++++++++++++++++++++++++++++++++++++++
intel/test_decode.c | 191 +
intel/tests/.gitignore | 1
intel/tests/gen4-3d.batch |binary
intel/tests/gen4-3d.batch-ref.txt | 488 +++++
intel/tests/gen4-3d.batch.sh | 1
intel/tests/gen5-3d.batch |binary
intel/tests/gen5-3d.batch-ref.txt | 512 +++++
intel/tests/gen5-3d.batch.sh | 1
intel/tests/gen6-3d.batch |binary
intel/tests/gen6-3d.batch-ref.txt | 990 ++++++++++
intel/tests/gen6-3d.batch.sh | 1
intel/tests/gen7-3d.batch |binary
intel/tests/gen7-3d.batch-ref.txt | 1350 +++++++++++++
intel/tests/gen7-3d.batch.sh | 1
intel/tests/gm45-3d.batch |binary
intel/tests/gm45-3d.batch-ref.txt | 488 +++++
intel/tests/gm45-3d.batch.sh | 1
intel/tests/test-batch.sh | 20
tests/gem_flink.c | 7
xf86drmMode.c | 153 +
xf86drmMode.h | 33
39 files changed, 8565 insertions(+), 52 deletions(-)
New commits:
commit e91400b4219caf5d63a59e40c4585308ed30326c
Author: Cyril Brulebois <k...@debian.org>
Date: Fri Jan 6 20:04:48 2012 +0100
Upload to unstable.
diff --git a/debian/changelog b/debian/changelog
index 9f24159..3b92e88 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,10 +1,10 @@
-libdrm (2.4.30-1) UNRELEASED; urgency=low
+libdrm (2.4.30-1) unstable; urgency=low
* New upstream release.
* Bump libdrm2's and libdrm-intel1's symbols and shlibs accordingly.
* Document the symlink dance when building from git in README.source.
- -- Cyril Brulebois <k...@debian.org> Fri, 06 Jan 2012 19:47:07 +0100
+ -- Cyril Brulebois <k...@debian.org> Fri, 06 Jan 2012 20:04:37 +0100
libdrm (2.4.29-1) unstable; urgency=low
commit f40e3394471d158b4af5780e258813b3d2ed8764
Author: Cyril Brulebois <k...@debian.org>
Date: Fri Jan 6 20:04:25 2012 +0100
Document the symlink dance when building from git in README.source.
diff --git a/debian/README.source b/debian/README.source
index 4ecd5e6..f9bb7c6 100644
--- a/debian/README.source
+++ b/debian/README.source
@@ -14,6 +14,12 @@ Quick Guide To Patching This Package For The Impatient
Alternatively, instead of using quilt directly, you can drop the patch in to
debian/patches and add the name of the patch to debian/patches/series.
+While building from git, dpkg-source can complain about symlinks vs.
+normal files mismatches. To work around this issue, before uploading,
+and without committing:
+
+ find -type l | while read dest; do src=$(readlink -f $dest); rm $dest; cp
$src $dest; done
+
------------------------------------
Guide To The X Strike Force Packages
------------------------------------
diff --git a/debian/changelog b/debian/changelog
index d6a0c18..9f24159 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -2,6 +2,7 @@ libdrm (2.4.30-1) UNRELEASED; urgency=low
* New upstream release.
* Bump libdrm2's and libdrm-intel1's symbols and shlibs accordingly.
+ * Document the symlink dance when building from git in README.source.
-- Cyril Brulebois <k...@debian.org> Fri, 06 Jan 2012 19:47:07 +0100
commit 9ce84e5c243f6403f0d39e2e5cf13c8ced51b471
Author: Cyril Brulebois <k...@debian.org>
Date: Fri Jan 6 19:57:02 2012 +0100
Bump libdrm2's and libdrm-intel1's symbols and shlibs accordingly.
diff --git a/debian/changelog b/debian/changelog
index d714a4a..d6a0c18 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,6 +1,7 @@
libdrm (2.4.30-1) UNRELEASED; urgency=low
* New upstream release.
+ * Bump libdrm2's and libdrm-intel1's symbols and shlibs accordingly.
-- Cyril Brulebois <k...@debian.org> Fri, 06 Jan 2012 19:47:07 +0100
diff --git a/debian/libdrm-intel1.symbols b/debian/libdrm-intel1.symbols
index 36d102d..c4af4d2 100644
--- a/debian/libdrm-intel1.symbols
+++ b/debian/libdrm-intel1.symbols
@@ -39,6 +39,13 @@ libdrm_intel.so.1 libdrm-intel1 #MINVER#
drm_intel_bufmgr_gem_init@Base 2.4.1
drm_intel_bufmgr_gem_set_vma_cache_size@Base 2.4.29
drm_intel_bufmgr_set_debug@Base 2.4.1
+ drm_intel_decode@Base 2.4.30
+ drm_intel_decode_context_alloc@Base 2.4.30
+ drm_intel_decode_context_free@Base 2.4.30
+ drm_intel_decode_set_batch_pointer@Base 2.4.30
+ drm_intel_decode_set_dump_past_end@Base 2.4.30
+ drm_intel_decode_set_head_tail@Base 2.4.30
+ drm_intel_decode_set_output_file@Base 2.4.30
drm_intel_gem_bo_clear_relocs@Base 2.4.27
drm_intel_gem_bo_get_reloc_count@Base 2.4.27
drm_intel_gem_bo_map_gtt@Base 2.4.3
diff --git a/debian/libdrm2.symbols b/debian/libdrm2.symbols
index 31a23da..29ce302 100644
--- a/debian/libdrm2.symbols
+++ b/debian/libdrm2.symbols
@@ -76,6 +76,7 @@ libdrm.so.2 libdrm2 #MINVER#
drmMap@Base 2.3.1
drmMapBufs@Base 2.3.1
drmMarkBufs@Base 2.3.1
+ drmModeAddFB2@Base 2.4.30
drmModeAddFB@Base 2.4.3
drmModeAttachMode@Base 2.4.3
drmModeConnectorSetProperty@Base 2.4.3
@@ -88,6 +89,7 @@ libdrm.so.2 libdrm2 #MINVER#
drmModeFreeEncoder@Base 2.4.3
drmModeFreeFB@Base 2.4.3
drmModeFreeModeInfo@Base 2.4.3
+ drmModeFreePlane@Base 2.4.30
drmModeFreeProperty@Base 2.4.3
drmModeFreePropertyBlob@Base 2.4.3
drmModeFreeResources@Base 2.4.3
@@ -95,6 +97,8 @@ libdrm.so.2 libdrm2 #MINVER#
drmModeGetCrtc@Base 2.4.3
drmModeGetEncoder@Base 2.4.3
drmModeGetFB@Base 2.4.3
+ drmModeGetPlane@Base 2.4.30
+ drmModeGetPlaneResources@Base 2.4.30
drmModeGetProperty@Base 2.4.3
drmModeGetPropertyBlob@Base 2.4.3
drmModeGetResources@Base 2.4.3
@@ -103,6 +107,7 @@ libdrm.so.2 libdrm2 #MINVER#
drmModeRmFB@Base 2.4.3
drmModeSetCrtc@Base 2.4.3
drmModeSetCursor@Base 2.4.3
+ drmModeSetPlane@Base 2.4.30
drmMsg@Base 2.4.1
drmOpen@Base 2.3.1
drmOpenControl@Base 2.4.3
diff --git a/debian/rules b/debian/rules
index 188f43d..a620ec7 100755
--- a/debian/rules
+++ b/debian/rules
@@ -75,9 +75,9 @@ endif
dh_strip -s --remaining-packages
override_dh_makeshlibs:
- dh_makeshlibs -plibdrm2 -V'libdrm2 (>= 2.4.25)' -- -c4
+ dh_makeshlibs -plibdrm2 -V'libdrm2 (>= 2.4.30)' -- -c4
ifeq ($(INTEL), yes)
- dh_makeshlibs -plibdrm-intel1 -V'libdrm-intel1 (>= 2.4.29)' -- -c4
+ dh_makeshlibs -plibdrm-intel1 -V'libdrm-intel1 (>= 2.4.30)' -- -c4
endif
ifeq ($(NOUVEAU), yes)
dh_makeshlibs -plibdrm-nouveau1a -V'libdrm-nouveau1a (>= 2.4.23)' -- -c4
commit 42c8c2b9627a7dc537e5bfb2fddb0c48baeb4eee
Author: Cyril Brulebois <k...@debian.org>
Date: Fri Jan 6 19:47:14 2012 +0100
Bump changelogs.
diff --git a/ChangeLog b/ChangeLog
index e7c92cf..fe7581a 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,276 @@
+commit adf1428915bfd0ee24758a3cbd56ce9b64f6eefb
+Author: Eric Anholt <e...@anholt.net>
+Date: Fri Jan 6 08:50:31 2012 -0800
+
+ configure: Bump version for 2.4.30
+
+commit 9fb83a49cb7e3db2f168aac5172fafb6fa0d69c8
+Author: Eric Anholt <e...@anholt.net>
+Date: Thu Dec 29 17:40:45 2011 -0800
+
+ intel: Update for new i915_drm.h defines.
+
+commit 683855f65523c978562ead56f9d68f50ffdca1a2
+Author: Eric Anholt <e...@anholt.net>
+Date: Tue Jan 3 14:32:18 2012 -0800
+
+ intel: Add regression tests for batch decode.
+
+ The .batch was generated using the dump-a-batch branch of
+
+ git://people.freedesktop.org/~anholt/mesa
+
+ using glxgears on gen7 hardware, using INTEL_DEVID_OVERRIDE for
+ non-gen7 (this means that offsets in the buffers for non-gen7 are 0!).
+ The .ref was generated by:
+
+ ./test_decode tests/gen7-3d.batch -dump.
+
+ The .sh exists because you can't supply arguments to tests using the
+ simple automake tests driver. Something reasonable could be done
+ using automake's parallel-tests driver (in fact, a previous version of
+ the patch did that), but I was concerned that:
+
+ 1) The parallel-tests driver is documented to be unstable -- they may
+ change interfaces on us later.
+ 2) The parallel-tests driver hides the output of tests in .log files
+ scattered all over the tree, which was ugly and more painful to
+ work with.
+
+ v2: Actually add the batch files, add a .gitignore for the *-new.txt
+ files added after failures, and fix failure mode for undetected
+ chipset name.
+ Reviewed-by: Daniel Vetter <daniel.vet...@ffwll.ch> (v1)
+
+commit ccbc40340b7b472939a90ae8afc0a82b358ce189
+Author: Eric Anholt <e...@anholt.net>
+Date: Tue Jan 3 12:33:37 2012 -0800
+
+ intel: Add a regression test program for intel_decode.c.
+
+ Reviewed-by: Daniel Vetter <daniel.vet...@ffwll.ch>
+
+commit ea33a231d530540ddcb9e0bac08ef15f625f744a
+Author: Eric Anholt <e...@anholt.net>
+Date: Tue Jan 3 13:05:57 2012 -0800
+
+ intel: Add an interface for setting the output file for decode.
+
+ Consumers often want to choose stdout vs stderr, and for testing I
+ want to output to an open_memstream file.
+
+ Reviewed-by: Daniel Vetter <daniel.vet...@ffwll.ch>
+
+commit a9dd34a7ee9d03d357e15f045ab85a12f6f6e4b8
+Author: Johannes Obermayr <johannesoberm...@gmx.de>
+Date: Sat Dec 31 01:45:32 2011 +0100
+
+ intel/intel_decode.c: Remove #include "intel_decode.h".
+
+ Signed-off-by: Chad Versace <chad.vers...@linux.intel.com>
+
+commit 4149faf3370c92e85533093bf764e773ebc41d88
+Author: Eric Anholt <e...@anholt.net>
+Date: Tue Dec 20 14:32:27 2011 -0800
+
+ intel: Disable unused decode_logic_op().
+
+ It was producing an unused code warning. I'm tempted to just remove
+ it, since it's unused, but I *might* use it soon.
+
+ Acked-by: Daniel Vetter <daniel.vet...@ffwll.ch>
+ Acked-by: Eugeni Dodonov <eug...@dodonov.net>
+
+commit 88cffcc899b6951c422aafbe7ae3069e3e795922
+Author: Eric Anholt <e...@anholt.net>
+Date: Tue Dec 20 14:28:03 2011 -0800
+
+ intel: Turn on normal warnings for intel_decode.c build.
+
+ Acked-by: Daniel Vetter <daniel.vet...@ffwll.ch>
+ Acked-by: Eugeni Dodonov <eug...@dodonov.net>
+
+commit 7b483188067c00014c5d263784d5140032a16cb6
+Author: Eric Anholt <e...@anholt.net>
+Date: Tue Dec 20 14:27:17 2011 -0800
+
+ intel: Remove c99ish variable declarations.
+
+ I'd rather be able to use c99 variable declarations (there's a lot of
+ awful code layout due to being c90ish), but I'll leave that for later.
+
+ Acked-by: Daniel Vetter <daniel.vet...@ffwll.ch>
+ Acked-by: Eugeni Dodonov <eug...@dodonov.net>
+
+commit 0c46f020c8a75a906f974dedb6628ed7eadb0b97
+Author: Eric Anholt <e...@anholt.net>
+Date: Tue Dec 20 14:23:15 2011 -0800
+
+ intel: Fix printf format warnings for intel_decode.
+
+ There was plenty of dropped useful data, and some horribly
+ mis-formatted data.
+
+ Acked-by: Daniel Vetter <daniel.vet...@ffwll.ch>
+ Acked-by: Eugeni Dodonov <eug...@dodonov.net>
+
+commit 39a06acfbdd834bcd365de08c7c14cfa39b18eab
+Author: Eric Anholt <e...@anholt.net>
+Date: Tue Dec 20 12:01:19 2011 -0800
+
+ intel: Add printflike warnings for instr_out.
+
+ Acked-by: Daniel Vetter <daniel.vet...@ffwll.ch>
+ Acked-by: Eugeni Dodonov <eug...@dodonov.net>
+
+commit 1db55a80a9f3f74df716c14d3cbfc1507f084221
+Author: Eric Anholt <e...@anholt.net>
+Date: Tue Dec 20 12:00:28 2011 -0800
+
+ intel: Fix a ton of signed vs unsigned and const char *warnings
+
+ We've got a different (better) set of warning flags in place in this
+ tree.
+
+ Acked-by: Daniel Vetter <daniel.vet...@ffwll.ch>
+ Acked-by: Eugeni Dodonov <eug...@dodonov.net>
+
+commit 07768babb81bf8b9b993c41e7dca1e011fd6bd69
+Author: Eric Anholt <e...@anholt.net>
+Date: Tue Dec 20 13:46:23 2011 -0800
+
+ intel: Fix Wsigned-compare warnings (soon to be enabled).
+
+ Acked-by: Daniel Vetter <daniel.vet...@ffwll.ch>
+ Acked-by: Eugeni Dodonov <eug...@dodonov.net>
+
+commit 71066abe1e32d906f65141c34ecfd9ffbf89ebde
+Author: Eric Anholt <e...@anholt.net>
+Date: Tue Dec 20 13:06:16 2011 -0800
+
+ intel: Get intel_decode.c minimally building.
+
+ My plan is to use this drm_intel_dump_batchbuffer() interface for the
+ current GPU tools, and the current Mesa batch dumping usage, while
+ eventually building more interesting interfaces for other uses.
+
+ Warnings are currently suppressed by using a helper lib with CFLAGS
+ set manually, because the code is totally not ready for libdrm's warnings
+ setup.
+
+ Acked-by: Daniel Vetter <daniel.vet...@ffwll.ch>
+ Acked-by: Eugeni Dodonov <eug...@dodonov.net>
+
+commit bbdda928d3c0fa2e5b38adc4c3f7763f957b5207
+Author: Eric Anholt <e...@anholt.net>
+Date: Tue Dec 20 11:44:36 2011 -0800
+
+ intel: Minor style tweaks after Lindent.
+
+ Some comments weren't wrapped, and for some reason uint32_t *data got
+ an extra space (while other instances of "type *identifier" didn't),
+ and the indentation of the opcode-list structs got trashed.
+
+ Acked-by: Daniel Vetter <daniel.vet...@ffwll.ch>
+ Acked-by: Eugeni Dodonov <eug...@dodonov.net>
+
+commit 193fa138d74f8d857b01b5ca8624f4ca79d9a91e
+Author: Eric Anholt <e...@anholt.net>
+Date: Tue Dec 20 11:36:07 2011 -0800
+
+ intel: Reformat intel_decode.c from intel-gpu-tools using Lindent.
+
+ We generally go for kernel style in this tree, and this 4-space indent
+ stuff was bothering me. The new results have some ugly bits, but
+ they're in places where we desperately want to be using helper
+ functions anyway.
+
+ Acked-by: Daniel Vetter <daniel.vet...@ffwll.ch>
+ Acked-by: Eugeni Dodonov <eug...@dodonov.net>
+
+commit 1d318e2a79c3ae02fa886bcba79ac68b5222e1a3
+Author: Eric Anholt <e...@anholt.net>
+Date: Tue Dec 20 13:03:37 2011 -0800
+
+ intel: intel: Add IS_GEN[567] macros.
+
+ These will be used by intel_decode.c, and were taken from intel-gpu-tools.
+
+ Acked-by: Daniel Vetter <daniel.vet...@ffwll.ch>
+ Acked-by: Eugeni Dodonov <eug...@dodonov.net>
+
+commit 078bc5b6ee24ea786c465f5e29dcb8b0d2f81b2e
+Author: Eric Anholt <e...@anholt.net>
+Date: Tue Dec 20 13:10:36 2011 -0800
+
+ intel: Make intel_chipset handle devid directly.
+
+ This will make these macros reusable from intel_decode.c, which
+ doesn't have a bufmgr_gem context, without faking the struct. We
+ should generally only be using these macros from bufmgr_gem context
+ setup anyway.
+
+ Acked-by: Daniel Vetter <daniel.vet...@ffwll.ch>
+ Acked-by: Eugeni Dodonov <eug...@dodonov.net>
+
+commit 8c4a2c884846caca517b49e2026661e57924d9e1
+Author: Eric Anholt <e...@anholt.net>
+Date: Tue Dec 20 11:25:20 2011 -0800
+
+ intel: Import intel_decode.c from intel-gpu-tools.
+
+ This is from commit dd9a5b4f7fb07c78db4e7481bedca1b981030e3f.
+ We've been sharing this file between that repo and Mesa, and it's time
+ to build a real interface using it. I'm also hoping to apply some of
+ its packet-walking logic for AUB dumping and batch validation
+ purposes.
+
+ Acked-by: Daniel Vetter <daniel.vet...@ffwll.ch>
+ Acked-by: Eugeni Dodonov <eug...@dodonov.net>
+
+commit ef20301a11afae50bfe127002913dbd0b81ddccc
+Author: Chris Wilson <ch...@chris-wilson.co.uk>
+Date: Sun Dec 18 13:58:57 2011 +0000
+
+ tests/gem_flink: Check for MASTER before proceeding
+
+ gem_flink|gem_open are DRM_AUTH ioctl, and being lazy we do not
+ establish ourselves as authenticated before testing the ioctls. So
+ instead of aborting, skip the test unless we have root privileges (and
+ so DRM_MASTER and the DRM_AUTH restriction no longer applies).
+
+ A future test could assert that the flink fails without proper
+ authentication.
+
+ Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=43924
+ Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
+
+commit 0ab2251b70d49a294d24f3ef54982e95226c104a
+Author: Chris Wilson <ch...@chris-wilson.co.uk>
+Date: Wed Dec 14 08:20:10 2011 +0000
+
+ intel: Reset vma list upon purge
+
+ During free we unconditionally delete the bo from the vma cache. This
+ relies on the its list member being kept in a sane state. This fails
+ after the object is purged, as the purge operation performs a pure
+ deletion and doesn't reset the list member, leaving a pair of dangling
+ pointers.
+
+ Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
+
+commit ac168bf2a068761b591187e6a0a52083d456280b
+Author: Jesse Barnes <jbar...@virtuousgeek.org>
+Date: Fri Apr 29 08:53:53 2011 -0700
+
+ libdrm: update drm headers from kernel, including new overlay ioctls &
structs
+
+ Add structs and functions necessary for the new plane and fb handling code,
+ including a new header, drm_fourcc.h, that includes the surface formats
+ supported by various DRM drivers.
+
+ Signed-off-by: Jesse Barnes <jbar...@virtuousgeek.org>
+
commit 7fd1678110b78d9324723a54dfd5049496b9e3cf
Author: Chris Wilson <ch...@chris-wilson.co.uk>
Date: Mon Dec 5 23:09:20 2011 +0000
diff --git a/debian/changelog b/debian/changelog
index 3deadfe..d714a4a 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,3 +1,9 @@
+libdrm (2.4.30-1) UNRELEASED; urgency=low
+
+ * New upstream release.
+
+ -- Cyril Brulebois <k...@debian.org> Fri, 06 Jan 2012 19:47:07 +0100
+
libdrm (2.4.29-1) unstable; urgency=low
* New upstream release:
commit adf1428915bfd0ee24758a3cbd56ce9b64f6eefb
Author: Eric Anholt <e...@anholt.net>
Date: Fri Jan 6 08:50:31 2012 -0800
configure: Bump version for 2.4.30
diff --git a/configure.ac b/configure.ac
index 540622f..773167f 100644
--- a/configure.ac
+++ b/configure.ac
@@ -20,7 +20,7 @@
AC_PREREQ([2.63])
AC_INIT([libdrm],
- [2.4.29],
+ [2.4.30],
[https://bugs.freedesktop.org/enter_bug.cgi?product=DRI],
[libdrm])
commit 9fb83a49cb7e3db2f168aac5172fafb6fa0d69c8
Author: Eric Anholt <e...@anholt.net>
Date: Thu Dec 29 17:40:45 2011 -0800
intel: Update for new i915_drm.h defines.
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index adc2392..846897c 100644
--- a/include/drm/i915_drm.h
+++ b/include/drm/i915_drm.h
@@ -228,7 +228,7 @@ typedef struct _drm_i915_sarea {
#define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE +
DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
#define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE +
DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id)
#define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE +
DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)
-#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE +
DRM_IOCTL_I915_OVERLAY_ATTRS, struct drm_intel_overlay_put_image)
+#define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE +
DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image)
#define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE +
DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)
/* Allow drivers to submit batchbuffers directly to hardware, relying
@@ -282,6 +282,7 @@ typedef struct drm_i915_irq_wait {
#define I915_PARAM_HAS_COHERENT_RINGS 13
#define I915_PARAM_HAS_EXEC_CONSTANTS 14
#define I915_PARAM_HAS_RELAXED_DELTA 15
+#define I915_PARAM_HAS_GEN7_SOL_RESET 16
typedef struct drm_i915_getparam {
int param;
@@ -644,6 +645,9 @@ struct drm_i915_gem_execbuffer2 {
__u64 rsvd2;
};
+/** Resets the SO write offset registers for transform feedback on gen7. */
+#define I915_EXEC_GEN7_SOL_RESET (1<<8)
+
struct drm_i915_gem_pin {
/** Handle of the buffer to be pinned. */
__u32 handle;
commit 683855f65523c978562ead56f9d68f50ffdca1a2
Author: Eric Anholt <e...@anholt.net>
Date: Tue Jan 3 14:32:18 2012 -0800
intel: Add regression tests for batch decode.
The .batch was generated using the dump-a-batch branch of
git://people.freedesktop.org/~anholt/mesa
using glxgears on gen7 hardware, using INTEL_DEVID_OVERRIDE for
non-gen7 (this means that offsets in the buffers for non-gen7 are 0!).
The .ref was generated by:
./test_decode tests/gen7-3d.batch -dump.
The .sh exists because you can't supply arguments to tests using the
simple automake tests driver. Something reasonable could be done
using automake's parallel-tests driver (in fact, a previous version of
the patch did that), but I was concerned that:
1) The parallel-tests driver is documented to be unstable -- they may
change interfaces on us later.
2) The parallel-tests driver hides the output of tests in .log files
scattered all over the tree, which was ugly and more painful to
work with.
v2: Actually add the batch files, add a .gitignore for the *-new.txt
files added after failures, and fix failure mode for undetected
chipset name.
Reviewed-by: Daniel Vetter <daniel.vet...@ffwll.ch> (v1)
diff --git a/intel/Makefile.am b/intel/Makefile.am
index 2d3d8c4..581c8c0 100644
--- a/intel/Makefile.am
+++ b/intel/Makefile.am
@@ -57,6 +57,23 @@ libdrm_intelinclude_HEADERS = intel_bufmgr.h \
# This may be interesting even outside of "make check", due to the -dump
option.
noinst_PROGRAMS = test_decode
+BATCHES = \
+ tests/gen4-3d.batch \
+ tests/gm45-3d.batch \
+ tests/gen5-3d.batch \
+ tests/gen6-3d.batch \
+ tests/gen7-3d.batch
+
+TESTS = \
+ $(BATCHES:.batch=.batch.sh)
+
+EXTRA_DIST = \
+ $(BATCHES) \
+ $(BATCHES:.batch=.batch.sh) \
+ $(BATCHES:.batch=.batch-ref.txt) \
+ $(BATCHES:.batch=.batch-ref.txt) \
+ tests/test-batch.sh
+
test_decode_LDADD = libdrm_intel.la
pkgconfig_DATA = libdrm_intel.pc
diff --git a/intel/test_decode.c b/intel/test_decode.c
index d41b0b2..c9ab7ad 100644
--- a/intel/test_decode.c
+++ b/intel/test_decode.c
@@ -144,6 +144,7 @@ infer_devid(const char *batch_filename)
{ "gen5", PCI_CHIP_ILD_G },
{ "gen6", PCI_CHIP_SANDYBRIDGE_GT2 },
{ "gen7", PCI_CHIP_IVYBRIDGE_GT2 },
+ { NULL, 0 },
};
int i;
diff --git a/intel/tests/.gitignore b/intel/tests/.gitignore
new file mode 100644
index 0000000..e9d01ec
--- /dev/null
+++ b/intel/tests/.gitignore
@@ -0,0 +1 @@
+*-new.txt
diff --git a/intel/tests/gen4-3d.batch b/intel/tests/gen4-3d.batch
new file mode 100644
index 0000000..e6911a4
Binary files /dev/null and b/intel/tests/gen4-3d.batch differ
diff --git a/intel/tests/gen4-3d.batch-ref.txt
b/intel/tests/gen4-3d.batch-ref.txt
new file mode 100644
index 0000000..20aa1d4
--- /dev/null
+++ b/intel/tests/gen4-3d.batch-ref.txt
@@ -0,0 +1,488 @@
+0x12300000: 0x61040000: 3DSTATE_PIPELINE_SELECT
+0x12300004: 0x79090000: 3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP
+0x12300008: 0x00000000: dword 1
+0x1230000c: 0x61020000: STATE_SIP
+0x12300010: 0x00000000: dword 1
+0x12300014: 0x780b0000: 3DSTATE_VF_STATISTICS
+0x12300018: 0x61010004: STATE_BASE_ADDRESS
+0x1230001c: 0x00000001: general state base address 0x00000000
+0x12300020: 0x00000001: surface state base address 0x00000000
+0x12300024: 0x00000001: indirect state base address 0x00000000
+0x12300028: 0x00000001: general state upper bound disabled
+0x1230002c: 0x00000001: indirect state upper bound disabled
+0x12300030: 0x78010004: 3DSTATE_BINDING_TABLE_POINTERS
+0x12300034: 0x00007e20: VS binding table
+0x12300038: 0x00000000: GS binding table
+0x1230003c: 0x00000000: Clip binding table
+0x12300040: 0x00000000: SF binding table
+0x12300044: 0x00007e20: WM binding table
+0x12300048: 0x79010003: 3DSTATE_CONSTANT_COLOR
+0x1230004c: 0x00000000: dword 1
+0x12300050: 0x00000000: dword 2
+0x12300054: 0x00000000: dword 3
+0x12300058: 0x00000000: dword 4
+0x1230005c: 0x79050003: 3DSTATE_DEPTH_BUFFER
+0x12300060: 0x2c0805ff: 2D, z24s8, pitch = 1536 bytes, tiled
+0x12300064: 0x00000000: depth offset
+0x12300068: 0x09584ac0: 300x300
+0x1230006c: 0x00000000: volume depth
+0x12300070: 0x78000005: 3DSTATE_PIPELINED_POINTERS
+0x12300074: 0x00007d60: VS state
+0x12300078: 0x00000000: GS state
+0x1230007c: 0x00007d21: Clip state
+0x12300080: 0x00007d80: SF state
+0x12300084: 0x00007de0: WM state
+0x12300088: 0x00007fc0: CC state
+0x1230008c: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs
+0x12300090: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40
+0x12300094: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256
+0x12300098: 0x60010000: CS_URB_STATE
+0x1230009c: 0x00000024: entry_size: 2 [192 bytes], n_entries: 4
+0x123000a0: 0x79000002: 3DSTATE_DRAWING_RECTANGLE
+0x123000a4: 0x00000000: top left: 0,0
+0x123000a8: 0x012b012b: bottom right: 299,299
+0x123000ac: 0x00000000: origin: 0,0
+0x123000b0: 0x78080003: 3DSTATE_VERTEX_BUFFERS
+0x123000b4: 0x0000000c: buffer 0: sequential, pitch 12b
+0x123000b8: 0x00000000: buffer address
+0x123000bc: 0x00000000: max index
+0x123000c0: 0x00000000: mbz
+0x123000c4: 0x78090001: 3DSTATE_VERTEX_ELEMENTS
+0x123000c8: 0x04400000: buffer 0: valid, type 0x0040, src offset
0x0000 bytes
+0x123000cc: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes
+0x123000d0: 0x60020100: CONSTANT_BUFFER: valid
+0x123000d4: 0x00000001: offset: 0x00000000, length: 128 bytes
+0x123000d8: 0x7b001804: 3DPRIMITIVE: tri fan sequential
+0x123000dc: 0x00000004: vertex count
+0x123000e0: 0x00000000: start vertex
+0x123000e4: 0x00000001: instance count
+0x123000e8: 0x00000000: start instance
+0x123000ec: 0x00000000: index bias
+0x123000f0: 0x78010004: 3DSTATE_BINDING_TABLE_POINTERS
+0x123000f4: 0x00007b40: VS binding table
+0x123000f8: 0x00000000: GS binding table
+0x123000fc: 0x00000000: Clip binding table
+0x12300100: 0x00000000: SF binding table
+0x12300104: 0x00007b40: WM binding table
+0x12300108: 0x78000005: 3DSTATE_PIPELINED_POINTERS
+0x1230010c: 0x00007aa0: VS state
+0x12300110: 0x00007a41: GS state
+0x12300114: 0x00007a61: Clip state
+0x12300118: 0x00007ac0: SF state
+0x1230011c: 0x00007b00: WM state
+0x12300120: 0x00007cc0: CC state
+0x12300124: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs
+0x12300128: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40
+0x1230012c: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256
+0x12300130: 0x78080003: 3DSTATE_VERTEX_BUFFERS
+0x12300134: 0x0000000c: buffer 0: sequential, pitch 12b
+0x12300138: 0x00000000: buffer address
+0x1230013c: 0x00000000: max index
+0x12300140: 0x00000000: mbz
+0x12300144: 0x60020100: CONSTANT_BUFFER: valid
+0x12300148: 0x00000082: offset: 0x00000080, length: 192 bytes
+0x1230014c: 0x7b002004: 3DPRIMITIVE: quad strip sequential
+0x12300150: 0x00000052: vertex count
+0x12300154: 0x00000000: start vertex
+0x12300158: 0x00000001: instance count
+0x1230015c: 0x00000000: start instance
+0x12300160: 0x00000000: index bias
+0x12300164: 0x78000005: 3DSTATE_PIPELINED_POINTERS
+0x12300168: 0x00007aa0: VS state
+0x1230016c: 0x00007a21: GS state
+0x12300170: 0x00007a61: Clip state
+0x12300174: 0x00007ac0: SF state
+0x12300178: 0x00007b00: WM state
+0x1230017c: 0x00007cc0: CC state
+0x12300180: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs
+0x12300184: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40
+0x12300188: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256
+0x1230018c: 0x60020100: CONSTANT_BUFFER: valid
+0x12300190: 0x00000082: offset: 0x00000080, length: 192 bytes
+0x12300194: 0x7b001c04: 3DPRIMITIVE: quad list sequential
+0x12300198: 0x00000050: vertex count
+0x1230019c: 0x00000052: start vertex
+0x123001a0: 0x00000001: instance count
+0x123001a4: 0x00000000: start instance
+0x123001a8: 0x00000000: index bias
+0x123001ac: 0x78000005: 3DSTATE_PIPELINED_POINTERS
+0x123001b0: 0x00007aa0: VS state
+0x123001b4: 0x00007a01: GS state
+0x123001b8: 0x00007a61: Clip state
+0x123001bc: 0x00007ac0: SF state
+0x123001c0: 0x00007b00: WM state
+0x123001c4: 0x00007cc0: CC state
+0x123001c8: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs
+0x123001cc: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40
+0x123001d0: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256
+0x123001d4: 0x60020100: CONSTANT_BUFFER: valid
+0x123001d8: 0x00000142: offset: 0x00000140, length: 192 bytes
+0x123001dc: 0x7b002004: 3DPRIMITIVE: quad strip sequential
+0x123001e0: 0x00000052: vertex count
+0x123001e4: 0x000000a2: start vertex
+0x123001e8: 0x00000001: instance count
+0x123001ec: 0x00000000: start instance
+0x123001f0: 0x00000000: index bias
+0x123001f4: 0x78000005: 3DSTATE_PIPELINED_POINTERS
+0x123001f8: 0x00007aa0: VS state
+0x123001fc: 0x000079e1: GS state
+0x12300200: 0x00007a61: Clip state
+0x12300204: 0x00007ac0: SF state
+0x12300208: 0x00007b00: WM state
+0x1230020c: 0x00007cc0: CC state
+0x12300210: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs
+0x12300214: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40
+0x12300218: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256
+0x1230021c: 0x60020100: CONSTANT_BUFFER: valid
+0x12300220: 0x00000142: offset: 0x00000140, length: 192 bytes
+0x12300224: 0x7b001c04: 3DPRIMITIVE: quad list sequential
+0x12300228: 0x00000050: vertex count
+0x1230022c: 0x000000f4: start vertex
+0x12300230: 0x00000001: instance count
+0x12300234: 0x00000000: start instance
+0x12300238: 0x00000000: index bias
+0x1230023c: 0x78000005: 3DSTATE_PIPELINED_POINTERS
+0x12300240: 0x00007aa0: VS state
+0x12300244: 0x000079c1: GS state
+0x12300248: 0x00007a61: Clip state
+0x1230024c: 0x00007ac0: SF state
+0x12300250: 0x00007b00: WM state
+0x12300254: 0x00007cc0: CC state
+0x12300258: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs
+0x1230025c: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40
+0x12300260: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256
+0x12300264: 0x60020100: CONSTANT_BUFFER: valid
+0x12300268: 0x00000142: offset: 0x00000140, length: 192 bytes
+0x1230026c: 0x78000005: 3DSTATE_PIPELINED_POINTERS
+0x12300270: 0x000079a0: VS state
+0x12300274: 0x000079c1: GS state
+0x12300278: 0x00007a61: Clip state
+0x1230027c: 0x00007ac0: SF state
+0x12300280: 0x00007b00: WM state
+0x12300284: 0x00007cc0: CC state
+0x12300288: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs
+0x1230028c: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40
+0x12300290: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256
+0x12300294: 0x78080003: 3DSTATE_VERTEX_BUFFERS
+0x12300298: 0x00000018: buffer 0: sequential, pitch 24b
+0x1230029c: 0x00000f48: buffer address
+0x123002a0: 0x00000000: max index
+0x123002a4: 0x00000000: mbz
+0x123002a8: 0x78090003: 3DSTATE_VERTEX_ELEMENTS
+0x123002ac: 0x04400000: buffer 0: valid, type 0x0040, src offset
0x0000 bytes
+0x123002b0: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes
+0x123002b4: 0x0440000c: buffer 0: valid, type 0x0040, src offset
0x000c bytes
+0x123002b8: 0x11130004: (X, Y, Z, 1.0), dst offset 0x10 bytes
+0x123002bc: 0x60020100: CONSTANT_BUFFER: valid
+0x123002c0: 0x00000202: offset: 0x00000200, length: 192 bytes
+0x123002c4: 0x7b002004: 3DPRIMITIVE: quad strip sequential
+0x123002c8: 0x000000a2: vertex count
+0x123002cc: 0x00000000: start vertex
+0x123002d0: 0x00000001: instance count
+0x123002d4: 0x00000000: start instance
+0x123002d8: 0x00000000: index bias
+0x123002dc: 0x78000005: 3DSTATE_PIPELINED_POINTERS
+0x123002e0: 0x000079a0: VS state
+0x123002e4: 0x00000000: GS state
+0x123002e8: 0x00007901: Clip state
+0x123002ec: 0x00007940: SF state
+0x123002f0: 0x00007960: WM state
+0x123002f4: 0x00007cc0: CC state
+0x123002f8: 0x00000000: MI_NOOP
+0x123002fc: 0x00000000: MI_NOOP
+0x12300300: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs
+0x12300304: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40
+0x12300308: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256
+0x1230030c: 0x60020100: CONSTANT_BUFFER: valid
+0x12300310: 0x00000202: offset: 0x00000200, length: 192 bytes
+0x12300314: 0x7b001404: 3DPRIMITIVE: tri strip sequential
+0x12300318: 0x0000002a: vertex count
+0x1230031c: 0x000000a2: start vertex
+0x12300320: 0x00000001: instance count
+0x12300324: 0x00000000: start instance
+0x12300328: 0x00000000: index bias
+0x1230032c: 0x78000005: 3DSTATE_PIPELINED_POINTERS
+0x12300330: 0x00007860: VS state
+0x12300334: 0x00007801: GS state
+0x12300338: 0x00007821: Clip state
+0x1230033c: 0x00007880: SF state
+0x12300340: 0x000078a0: WM state
+0x12300344: 0x00007cc0: CC state
+0x12300348: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs
+0x1230034c: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40
+0x12300350: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256
+0x12300354: 0x78080003: 3DSTATE_VERTEX_BUFFERS
+0x12300358: 0x0000000c: buffer 0: sequential, pitch 12b
+0x1230035c: 0x00002268: buffer address
+0x12300360: 0x00000000: max index
+0x12300364: 0x00000000: mbz
+0x12300368: 0x78090001: 3DSTATE_VERTEX_ELEMENTS
+0x1230036c: 0x04400000: buffer 0: valid, type 0x0040, src offset
0x0000 bytes
+0x12300370: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes
+0x12300374: 0x60020100: CONSTANT_BUFFER: valid
+0x12300378: 0x000002c2: offset: 0x000002c0, length: 192 bytes
+0x1230037c: 0x7b002004: 3DPRIMITIVE: quad strip sequential
+0x12300380: 0x0000002a: vertex count
+0x12300384: 0x00000000: start vertex
+0x12300388: 0x00000001: instance count
+0x1230038c: 0x00000000: start instance
+0x12300390: 0x00000000: index bias
+0x12300394: 0x78000005: 3DSTATE_PIPELINED_POINTERS
+0x12300398: 0x00007860: VS state
+0x1230039c: 0x000077e1: GS state
+0x123003a0: 0x00007821: Clip state
+0x123003a4: 0x00007880: SF state
+0x123003a8: 0x000078a0: WM state
+0x123003ac: 0x00007cc0: CC state
+0x123003b0: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs
+0x123003b4: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40
+0x123003b8: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256
+0x123003bc: 0x60020100: CONSTANT_BUFFER: valid
+0x123003c0: 0x000002c2: offset: 0x000002c0, length: 192 bytes
+0x123003c4: 0x7b001c04: 3DPRIMITIVE: quad list sequential
+0x123003c8: 0x00000028: vertex count
+0x123003cc: 0x0000002a: start vertex
+0x123003d0: 0x00000001: instance count
+0x123003d4: 0x00000000: start instance
+0x123003d8: 0x00000000: index bias
+0x123003dc: 0x78000005: 3DSTATE_PIPELINED_POINTERS
+0x123003e0: 0x00007860: VS state
+0x123003e4: 0x000077c1: GS state
+0x123003e8: 0x00007821: Clip state
+0x123003ec: 0x00007880: SF state
+0x123003f0: 0x000078a0: WM state
+0x123003f4: 0x00007cc0: CC state
+0x123003f8: 0x00000000: MI_NOOP
+0x123003fc: 0x00000000: MI_NOOP
+0x12300400: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs
+0x12300404: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40
+0x12300408: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256
+0x1230040c: 0x60020100: CONSTANT_BUFFER: valid
+0x12300410: 0x00000382: offset: 0x00000380, length: 192 bytes
+0x12300414: 0x7b002004: 3DPRIMITIVE: quad strip sequential
+0x12300418: 0x0000002a: vertex count
+0x1230041c: 0x00000052: start vertex
+0x12300420: 0x00000001: instance count
+0x12300424: 0x00000000: start instance
+0x12300428: 0x00000000: index bias
+0x1230042c: 0x78000005: 3DSTATE_PIPELINED_POINTERS
+0x12300430: 0x00007860: VS state
+0x12300434: 0x000077a1: GS state
+0x12300438: 0x00007821: Clip state
+0x1230043c: 0x00007880: SF state
+0x12300440: 0x000078a0: WM state
+0x12300444: 0x00007cc0: CC state
+0x12300448: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs
+0x1230044c: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40
+0x12300450: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256
+0x12300454: 0x60020100: CONSTANT_BUFFER: valid
+0x12300458: 0x00000382: offset: 0x00000380, length: 192 bytes
+0x1230045c: 0x7b001c04: 3DPRIMITIVE: quad list sequential
+0x12300460: 0x00000028: vertex count
+0x12300464: 0x0000007c: start vertex
+0x12300468: 0x00000001: instance count
+0x1230046c: 0x00000000: start instance
+0x12300470: 0x00000000: index bias
+0x12300474: 0x78000005: 3DSTATE_PIPELINED_POINTERS
+0x12300478: 0x00007860: VS state
+0x1230047c: 0x00007781: GS state
+0x12300480: 0x00007821: Clip state
+0x12300484: 0x00007880: SF state
+0x12300488: 0x000078a0: WM state
+0x1230048c: 0x00007cc0: CC state
+0x12300490: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs
+0x12300494: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40
+0x12300498: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256
+0x1230049c: 0x60020100: CONSTANT_BUFFER: valid
+0x123004a0: 0x00000382: offset: 0x00000380, length: 192 bytes
+0x123004a4: 0x78000005: 3DSTATE_PIPELINED_POINTERS
+0x123004a8: 0x00007760: VS state
+0x123004ac: 0x00007781: GS state
+0x123004b0: 0x00007821: Clip state
+0x123004b4: 0x00007880: SF state
+0x123004b8: 0x000078a0: WM state
+0x123004bc: 0x00007cc0: CC state
+0x123004c0: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs
+0x123004c4: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40
+0x123004c8: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256
+0x123004cc: 0x78080003: 3DSTATE_VERTEX_BUFFERS
+0x123004d0: 0x00000018: buffer 0: sequential, pitch 24b
+0x123004d4: 0x00002a30: buffer address
+0x123004d8: 0x00000000: max index
+0x123004dc: 0x00000000: mbz
+0x123004e0: 0x78090003: 3DSTATE_VERTEX_ELEMENTS
+0x123004e4: 0x04400000: buffer 0: valid, type 0x0040, src offset
0x0000 bytes
+0x123004e8: 0x11130000: (X, Y, Z, 1.0), dst offset 0x00 bytes
+0x123004ec: 0x0440000c: buffer 0: valid, type 0x0040, src offset
0x000c bytes
+0x123004f0: 0x11130004: (X, Y, Z, 1.0), dst offset 0x10 bytes
+0x123004f4: 0x60020100: CONSTANT_BUFFER: valid
+0x123004f8: 0x00000442: offset: 0x00000440, length: 192 bytes
+0x123004fc: 0x7b002004: 3DPRIMITIVE: quad strip sequential
+0x12300500: 0x00000052: vertex count
+0x12300504: 0x00000000: start vertex
+0x12300508: 0x00000001: instance count
+0x1230050c: 0x00000000: start instance
+0x12300510: 0x00000000: index bias
+0x12300514: 0x78000005: 3DSTATE_PIPELINED_POINTERS
+0x12300518: 0x00007760: VS state
+0x1230051c: 0x00000000: GS state
+0x12300520: 0x000076c1: Clip state
+0x12300524: 0x00007700: SF state
+0x12300528: 0x00007720: WM state
+0x1230052c: 0x00007cc0: CC state
+0x12300530: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs
+0x12300534: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40
+0x12300538: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256
+0x1230053c: 0x60020100: CONSTANT_BUFFER: valid
+0x12300540: 0x00000442: offset: 0x00000440, length: 192 bytes
+0x12300544: 0x7b001404: 3DPRIMITIVE: tri strip sequential
+0x12300548: 0x00000016: vertex count
+0x1230054c: 0x00000052: start vertex
+0x12300550: 0x00000001: instance count
+0x12300554: 0x00000000: start instance
+0x12300558: 0x00000000: index bias
+0x1230055c: 0x78000005: 3DSTATE_PIPELINED_POINTERS
+0x12300560: 0x00007620: VS state
+0x12300564: 0x000075c1: GS state
+0x12300568: 0x000075e1: Clip state
+0x1230056c: 0x00007640: SF state
+0x12300570: 0x00007660: WM state
+0x12300574: 0x00007cc0: CC state
+0x12300578: 0x00000000: MI_NOOP
+0x1230057c: 0x00000000: MI_NOOP
+0x12300580: 0x60003f01: URB_FENCE: cs vfe sf clip gs vs
+0x12300584: 0x0320a020: vs fence: 32, clip_fence: 50, gs_fence: 40
+0x12300588: 0x10000042: sf fence: 66, vfe_fence: 0, cs_fence: 256
+0x1230058c: 0x78080003: 3DSTATE_VERTEX_BUFFERS
+0x12300590: 0x0000000c: buffer 0: sequential, pitch 12b
+0x12300594: 0x000033f0: buffer address
+0x12300598: 0x00000000: max index
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