New branch 'ubuntu+1' available with the following commits:
commit 89ab1db5ff6836d2dc278c8d8b2993793206702b
Author: Christopher James Halse Rogers <christopher.halse.rog...@canonical.com>
Date: Mon Dec 19 19:08:03 2011 +1100
Merge new upstream version; drop plymouth patch merged upstream
commit cedf8e557f38250ebd72085555024928dbbbf834
Merge: 6ca55ff aacbd62
Author: Christopher James Halse Rogers <christopher.halse.rog...@canonical.com>
Date: Mon Dec 19 18:57:38 2011 +1100
Merge branch 'upstream-ubuntu' into ubuntu
commit 6ca55ffb3f952d34a202a6daec60618330e8d2f8
Merge: 08760e2 aac10a1
Author: Christopher James Halse Rogers <christopher.halse.rog...@canonical.com>
Date: Mon Dec 19 18:49:55 2011 +1100
Merge remote-tracking branch 'origin/debian-unstable' into ubuntu
commit aacbd629b02cbee3f9e6a0ee452b4e3f21376bd3
Author: Alex Deucher <alexdeuc...@gmail.com>
Date: Mon Dec 12 09:32:30 2011 -0500
radeon: add some new pci ids
fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=43739
Signed-off-by: Alex Deucher <alexdeuc...@gmail.com>
commit bc54e415e2fd344939c5c788ea0686133a7e2c69
Author: Dave Airlie <airl...@redhat.com>
Date: Tue Dec 6 15:47:45 2011 +0000
radeon: add original radeon to always tiled.
and actually enable it for M7, previous commit only did one function.
Signed-off-by: Dave Airlie <airl...@redhat.com>
commit ba46c7b0cf72d157748981eb3224d5eefb6200aa
Author: Dave Airlie <airl...@redhat.com>
Date: Tue Dec 6 13:42:49 2011 +0000
radeon: refine always tiled depth check
So it appears the M7 family always tiles its depth buffer also.
Signed-off-by: Dave Airlie <airl...@redhat.com>
commit 98b2d5fe1722a43c4bbe7711ed7180a3fb65305f
Author: Dave Airlie <airl...@redhat.com>
Date: Mon Dec 5 18:44:28 2011 +0000
radeon: r200 depth buffers are always tiled
When we do the allocations we need to make sure the always tiled
nature is taken into account.
Signed-off-by: Dave Airlie <airl...@redhat.com>
commit 7dcefc69d9fbceae27cd03083c815e01a19b527e
Author: Alex Deucher <alexdeuc...@gmail.com>
Date: Mon Dec 5 09:21:48 2011 -0500
Xv: Evergreen+ asics support 16k surfaces
Signed-off-by: Alex Deucher <alexdeuc...@gmail.com>
commit 72e386d42516e7cd3c2cbf2fffc9174cd3ec8451
Author: Alex Deucher <alexander.deuc...@amd.com>
Date: Wed Nov 30 19:38:35 2011 -0500
radeon: add some new pci ids
Signed-off-by: Alex Deucher <alexander.deuc...@amd.com>
commit 3853c3020d05175ae180b9a188dec7c425bdd0b8
Author: Dave Airlie <airl...@redhat.com>
Date: Mon Nov 28 18:38:30 2011 +0000
fixup xinerama since 9151f3b1c2ebcc34e63195888ba696f2183ba5e2
since the driver would call RRFirstOutput without checking if randr has
been enabled, and it would crash in privates code.
reported by vereteran on #radeon
Signed-off-by: Dave Airlie <airl...@redhat.com>
Acked-on-irc-by: Michel Dänzer <michel.daen...@amd.com>
commit d669c34f140c000f88c4b4e464e44e6c8694f581
Author: Benjamin Herrenschmidt <b...@kernel.crashing.org>
Date: Mon Nov 21 11:35:40 2011 +1100
ddx/evergreen: Fix endian of ALU constants
The constants are written directly into a buffer object shared with the
card and we "forget" to swap them. This patch fixes it by doing the swap
in evergreen_set_alu_consts() in-place (ie, it modifies the buffer),
which should be fine with the way we use it in the ddx.
This makes everything work fine on my caicos card on a G5 including some
quik tests with Xv, gnome3 shell, etc...
Thanks a lot to Jerome Glisse for holding my hand through debugging that
(and finding the actual bug).
Signed-off-by: Benjamin Herrenschmidt <b...@kernel.crashing.org>
Signed-off-by: Alex Deucher <alexdeuc...@gmail.com>
commit 422bdd4fe6cb728e1dd08a56f6ee2d0f009cbfcb
Author: Alex Deucher <alexdeuc...@gmail.com>
Date: Mon Nov 14 09:39:16 2011 -0500
radeon: add missing FireMV pci id
Signed-off-by: Alex Deucher <alexdeuc...@gmail.com>
commit 534fb6e413a909a9d1afd57d1c711844b7c5ddf4
Author: Dave Airlie <airl...@redhat.com>
Date: Fri Nov 11 10:26:51 2011 +0000
ati: enable bg none when fbcon succeeds and we are built against ABI after
10.
One less patch to keep carrying in Fedora.
Signed-off-by: Dave Airlie <airl...@redhat.com>
commit 89452c08048c98fb5cc3dc551b3824be40d52cf2
Author: Michel Dänzer <michel.daen...@amd.com>
Date: Tue Nov 8 11:23:11 2011 +0100
UMS: Guard references to PCITAG / pciTag with XSERVER_LIBPCIACCESS (bug
#42690)
Should fix https://bugs.freedesktop.org/show_bug.cgi?id=42690 .
Signed-off-by: Michel Dänzer <michel.daen...@amd.com>
commit 5ec34ed95948f7164184551615c1fc4c3eef3b98
Author: Ilija Hadzic <ihad...@research.bell-labs.com>
Date: Thu Nov 3 20:16:47 2011 -0400
DRI/DRI2: remove hard-coded limitation to 6 crtcs
DRM's hard limit to the number of CRTCs is 32. ATI DDX unnecessarily
clips this limit to 6 by hard coding initial assumption for
output->possible_crtcs mask to 0x7f (before it gets trimmed down to
what's really possible for a given output) and by allocating only 6
entries for for cursor_bo[] array in RADEONInfoRec.
Fix this and thus allow the ATI DDX to deal with as many CRTCs
as the DRM allows (32), so it is ready if anything with >6 CRTCs
comes out.
Signed-off-by: Ilija Hadzic <ihad...@research.bell-labs.com>
commit 4853ab2cdc3b97948c7cd69eaf4fff54f59774fc
Author: Michel Dänzer <michel.daen...@amd.com>
Date: Fri Nov 4 12:15:53 2011 +0100
Turn compile time check into runtime check.
Signed-off-by: Michel Dänzer <michel.daen...@amd.com>
commit bcdb54fe16ebf2e239b84eebf20e8adfe5094bff
Author: Alex Deucher <alexdeuc...@gmail.com>
Date: Thu Oct 20 11:11:35 2011 -0400
check for xserver 1.9.4.901 to enable tiling by default
Previous xservers had a bug in the EXA code which caused
display corruption in some cases.
See:
https://bugs.freedesktop.org/show_bug.cgi?id=33929
Signed-off-by: Alex Deucher <alexdeuc...@gmail.com>
commit edde94cba5321e6e51e7fd4d79dde5abc4944495
Author: Michel Dänzer <michel.daen...@amd.com>
Date: Wed Nov 2 13:40:05 2011 +0100
Bump version post release.
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