configure.ac | 2
man/radeon.man | 9
src/ati_pciids_gen.h | 14 +
src/atombios_output.c | 5
src/drmmode_display.c | 48 +++-
src/evergreen_accel.c | 67 +++++-
src/evergreen_exa.c | 401 ++++++++++++------------------------
src/evergreen_reg.h | 3
src/evergreen_shader.c | 60 ++++-
src/evergreen_shader.h | 66 ++---
src/evergreen_state.h | 22 +
src/evergreen_textured_videofuncs.c | 61 ++---
src/pcidb/ati_pciids.csv | 14 +
src/r600_exa.c | 332 ++++++++++++++---------------
src/r600_reg.h | 21 +
src/r600_shader.c | 60 ++++-
src/r600_shader.h | 80 +++----
src/r600_state.h | 7
src/r600_textured_videofuncs.c | 45 ++--
src/r6xx_accel.c | 77 ++++++
src/radeon.h | 5
src/radeon_atombios.c | 28 +-
src/radeon_chipinfo_gen.h | 14 +
src/radeon_chipset_gen.h | 14 +
src/radeon_dri2.c | 17 +
src/radeon_driver.c | 5
src/radeon_exa.c | 5
src/radeon_exa_render.c | 6
src/radeon_kms.c | 92 +++++---
src/radeon_legacy_memory.c | 2
src/radeon_output.c | 8
src/radeon_pci_chipset_gen.h | 14 +
src/radeon_pci_device_match_gen.h | 14 +
src/radeon_textured_video.c | 48 ++--
src/radeon_video.h | 1
35 files changed, 980 insertions(+), 687 deletions(-)
New commits:
commit 38d9368e59b2990bf32a028ece2132451b402350
Author: Alex Deucher <alexdeuc...@gmail.com>
Date: Thu Mar 17 18:59:55 2011 -0400
bump for release
Signed-off-by: Alex Deucher <alexdeuc...@gmail.com>
diff --git a/configure.ac b/configure.ac
index ec54478..6f72c2d 100644
--- a/configure.ac
+++ b/configure.ac
@@ -23,7 +23,7 @@
# Initialize Autoconf
AC_PREREQ([2.60])
AC_INIT([xf86-video-ati],
- [6.14.99],
+ [6.14.1],
[https://bugs.freedesktop.org/enter_bug.cgi?product=xorg],
[xf86-video-ati])
commit cdfc007eccc9b130fc08012deef304488eb6e469
Author: Dave Airlie <airl...@redhat.com>
Date: Wed Mar 16 10:40:42 2011 +1000
radeon/exa: correct function name
this corrects the function name so it matches the contents.
Signed-off-by: Dave Airlie <airl...@redhat.com>
diff --git a/src/evergreen_exa.c b/src/evergreen_exa.c
index 553f05e..ae73e38 100644
--- a/src/evergreen_exa.c
+++ b/src/evergreen_exa.c
@@ -731,7 +731,7 @@ static Bool EVERGREENCheckCompositeTexture(PicturePtr pPict,
RADEON_FALLBACK(("REPEAT_NONE unsupported for transformed xRGB
source\n"));
}
- if (!radeon_transform_is_affine(pPict->transform))
+ if (!radeon_transform_is_affine_or_scaled(pPict->transform))
RADEON_FALLBACK(("non-affine transforms not supported\n"));
return TRUE;
diff --git a/src/r600_exa.c b/src/r600_exa.c
index 57e5c0f..0ed0ced 100644
--- a/src/r600_exa.c
+++ b/src/r600_exa.c
@@ -910,7 +910,7 @@ static Bool R600CheckCompositeTexture(PicturePtr pPict,
RADEON_FALLBACK(("REPEAT_NONE unsupported for transformed xRGB
source\n"));
}
- if (!radeon_transform_is_affine(pPict->transform))
+ if (!radeon_transform_is_affine_or_scaled(pPict->transform))
RADEON_FALLBACK(("non-affine transforms not supported\n"));
return TRUE;
diff --git a/src/radeon.h b/src/radeon.h
index 4f5095d..a6d20d7 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -1290,7 +1290,7 @@ extern void RADEONPMFini(ScrnInfoPtr pScrn);
#ifdef USE_EXA
/* radeon_exa.c */
extern Bool RADEONSetupMemEXA(ScreenPtr pScreen);
-extern Bool radeon_transform_is_affine(PictTransformPtr t);
+extern Bool radeon_transform_is_affine_or_scaled(PictTransformPtr t);
/* radeon_exa_funcs.c */
extern void RADEONCopyCP(PixmapPtr pDst, int srcX, int srcY, int dstX,
diff --git a/src/radeon_exa.c b/src/radeon_exa.c
index 4f31b82..1c647b9 100644
--- a/src/radeon_exa.c
+++ b/src/radeon_exa.c
@@ -179,7 +179,7 @@ Bool RADEONGetPixmapOffsetPitch(PixmapPtr pPix, uint32_t
*pitch_offset)
*
* transform may be null.
*/
-Bool radeon_transform_is_affine(PictTransformPtr t)
+Bool radeon_transform_is_affine_or_scaled(PictTransformPtr t)
{
if (t == NULL)
return TRUE;
diff --git a/src/radeon_exa_render.c b/src/radeon_exa_render.c
index 2e13b00..43d3555 100644
--- a/src/radeon_exa_render.c
+++ b/src/radeon_exa_render.c
@@ -379,7 +379,7 @@ static Bool R100CheckCompositeTexture(PicturePtr pPict,
RADEON_FALLBACK(("REPEAT_NONE unsupported for transformed xRGB
source\n"));
}
- if (!radeon_transform_is_affine(pPict->transform))
+ if (!radeon_transform_is_affine_or_scaled(pPict->transform))
RADEON_FALLBACK(("non-affine transforms not supported\n"));
return TRUE;
@@ -781,7 +781,7 @@ static Bool R200CheckCompositeTexture(PicturePtr pPict,
RADEON_FALLBACK(("REPEAT_NONE unsupported for transformed xRGB
source\n"));
}
- if (!radeon_transform_is_affine(pPict->transform))
+ if (!radeon_transform_is_affine_or_scaled(pPict->transform))
RADEON_FALLBACK(("non-affine transforms not supported\n"));
return TRUE;
@@ -1168,7 +1168,7 @@ static Bool R300CheckCompositeTexture(PicturePtr pPict,
RADEON_FALLBACK(("REPEAT_NONE unsupported for transformed xRGB
source\n"));
}
- if (!radeon_transform_is_affine(pPict->transform))
+ if (!radeon_transform_is_affine_or_scaled(pPict->transform))
RADEON_FALLBACK(("non-affine transforms not supported\n"));
return TRUE;
commit b93d7658f669f6dc1cfacebcfe955a1e113a537c
Author: Dave Airlie <airl...@redhat.com>
Date: Wed Mar 16 10:37:22 2011 +1000
radeon/exa: fix scaling check
This caused a regression in firefox, as these numbers are xFixed
values hence 1 is actually 65536.
Should fix: https://bugzilla.redhat.com/show_bug.cgi?id=685084
Signed-off-by: Dave Airlie <airl...@redhat.com>
diff --git a/src/radeon_exa.c b/src/radeon_exa.c
index aa3d55e..4f31b82 100644
--- a/src/radeon_exa.c
+++ b/src/radeon_exa.c
@@ -184,7 +184,7 @@ Bool radeon_transform_is_affine(PictTransformPtr t)
if (t == NULL)
return TRUE;
/* the shaders don't handle scaling either */
- return t->matrix[2][0] == 0 && t->matrix[2][1] == 0 && t->matrix[2][2]
== 1;
+ return t->matrix[2][0] == 0 && t->matrix[2][1] == 0 && t->matrix[2][2]
== IntToxFixed(1);
}
#if X_BYTE_ORDER == X_BIG_ENDIAN
commit 8567b8cd9e136ef69906e02286b3752db2404741
Author: Alex Deucher <alexdeuc...@gmail.com>
Date: Tue Mar 15 13:13:06 2011 -0400
APU: no tiling yet
Signed-off-by: Alex Deucher <alexdeuc...@gmail.com>
diff --git a/src/radeon_kms.c b/src/radeon_kms.c
index 125a132..0760170 100644
--- a/src/radeon_kms.c
+++ b/src/radeon_kms.c
@@ -651,6 +651,10 @@ Bool RADEONPreInit_KMS(ScrnInfoPtr pScrn, int flags)
} else
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"R6xx+ KMS Color Tiling requires radeon drm 2.6.0 or
newer\n");
+
+ /* don't support tiling on APUs yet */
+ if (info->ChipFamily == CHIP_FAMILY_PALM)
+ info->allowColorTiling = FALSE;
} else
info->allowColorTiling = xf86ReturnOptValBool(info->Options,
OPTION_COLOR_TILING,
colorTilingDefault);
commit 4d350497012fa31a417ada662006e2d64db2a4b5
Author: Dave Airlie <airl...@redhat.com>
Date: Tue Mar 15 10:32:19 2011 +1000
radeon: exa shaders don't handle scaling either.
rendercheck tsrccoords test fails.
Signed-off-by: Dave Airlie <airl...@redhat.com>
diff --git a/src/radeon_exa.c b/src/radeon_exa.c
index 3dbdcae..aa3d55e 100644
--- a/src/radeon_exa.c
+++ b/src/radeon_exa.c
@@ -183,7 +183,8 @@ Bool radeon_transform_is_affine(PictTransformPtr t)
{
if (t == NULL)
return TRUE;
- return t->matrix[2][0] == 0 && t->matrix[2][1] == 0;
+ /* the shaders don't handle scaling either */
+ return t->matrix[2][0] == 0 && t->matrix[2][1] == 0 && t->matrix[2][2]
== 1;
}
#if X_BYTE_ORDER == X_BIG_ENDIAN
commit 6319a33cb7bd8dba1eaf47bee1e2608cee5d7600
Author: Alex Deucher <alexdeuc...@gmail.com>
Date: Wed Mar 2 19:38:04 2011 -0500
kms: add cayman pci ids
Signed-off-by: Alex Deucher <alexdeuc...@gmail.com>
diff --git a/src/ati_pciids_gen.h b/src/ati_pciids_gen.h
index f7b7569..598dd72 100644
--- a/src/ati_pciids_gen.h
+++ b/src/ati_pciids_gen.h
@@ -500,6 +500,20 @@
#define PCI_CHIP_CEDAR_68F8 0x68F8
#define PCI_CHIP_CEDAR_68F9 0x68F9
#define PCI_CHIP_CEDAR_68FE 0x68FE
+#define PCI_CHIP_CAYMAN_6700 0x6700
+#define PCI_CHIP_CAYMAN_6701 0x6701
+#define PCI_CHIP_CAYMAN_6702 0x6702
+#define PCI_CHIP_CAYMAN_6703 0x6703
+#define PCI_CHIP_CAYMAN_6704 0x6704
+#define PCI_CHIP_CAYMAN_6705 0x6705
+#define PCI_CHIP_CAYMAN_6706 0x6706
+#define PCI_CHIP_CAYMAN_6707 0x6707
+#define PCI_CHIP_CAYMAN_6708 0x6708
+#define PCI_CHIP_CAYMAN_6709 0x6709
+#define PCI_CHIP_CAYMAN_6718 0x6718
+#define PCI_CHIP_CAYMAN_6719 0x6719
+#define PCI_CHIP_CAYMAN_671C 0x671C
+#define PCI_CHIP_CAYMAN_671D 0x671D
#define PCI_CHIP_BARTS_6720 0x6720
#define PCI_CHIP_BARTS_6721 0x6721
#define PCI_CHIP_BARTS_6722 0x6722
diff --git a/src/pcidb/ati_pciids.csv b/src/pcidb/ati_pciids.csv
index e8bfb4c..07454af 100644
--- a/src/pcidb/ati_pciids.csv
+++ b/src/pcidb/ati_pciids.csv
@@ -501,6 +501,20 @@
"0x68F8","CEDAR_68F8","CEDAR",,,,,,"CEDAR"
"0x68F9","CEDAR_68F9","CEDAR",,,,,,"ATI Radeon HD 5450"
"0x68FE","CEDAR_68FE","CEDAR",,,,,,"CEDAR"
+"0x6700","CAYMAN_6700","CAYMAN",,,,,,"CAYMAN"
+"0x6701","CAYMAN_6701","CAYMAN",,,,,,"CAYMAN"
+"0x6702","CAYMAN_6702","CAYMAN",,,,,,"CAYMAN"
+"0x6703","CAYMAN_6703","CAYMAN",,,,,,"CAYMAN"
+"0x6704","CAYMAN_6704","CAYMAN",,,,,,"CAYMAN"
+"0x6705","CAYMAN_6705","CAYMAN",,,,,,"CAYMAN"
+"0x6706","CAYMAN_6706","CAYMAN",,,,,,"CAYMAN"
+"0x6707","CAYMAN_6707","CAYMAN",,,,,,"CAYMAN"
+"0x6708","CAYMAN_6708","CAYMAN",,,,,,"CAYMAN"
+"0x6709","CAYMAN_6709","CAYMAN",,,,,,"CAYMAN"
+"0x6718","CAYMAN_6718","CAYMAN",,,,,,"AMD Radeon HD 6900 Series"
+"0x6719","CAYMAN_6719","CAYMAN",,,,,,"AMD Radeon HD 6900 Series"
+"0x671C","CAYMAN_671C","CAYMAN",,,,,,"CAYMAN"
+"0x671D","CAYMAN_671D","CAYMAN",,,,,,"CAYMAN"
"0x6720","BARTS_6720","BARTS",1,,,,,"AMD Radeon HD 6900M Series"
"0x6721","BARTS_6721","BARTS",1,,,,,"Mobility Radeon HD 6000 Series"
"0x6722","BARTS_6722","BARTS",,,,,,"BARTS"
diff --git a/src/radeon_chipinfo_gen.h b/src/radeon_chipinfo_gen.h
index a90fae7..2caeed9 100644
--- a/src/radeon_chipinfo_gen.h
+++ b/src/radeon_chipinfo_gen.h
@@ -420,6 +420,20 @@ static RADEONCardInfo RADEONCards[] = {
{ 0x68F8, CHIP_FAMILY_CEDAR, 0, 0, 0, 0, 0 },
{ 0x68F9, CHIP_FAMILY_CEDAR, 0, 0, 0, 0, 0 },
{ 0x68FE, CHIP_FAMILY_CEDAR, 0, 0, 0, 0, 0 },
+ { 0x6700, CHIP_FAMILY_CAYMAN, 0, 0, 0, 0, 0 },
+ { 0x6701, CHIP_FAMILY_CAYMAN, 0, 0, 0, 0, 0 },
+ { 0x6702, CHIP_FAMILY_CAYMAN, 0, 0, 0, 0, 0 },
+ { 0x6703, CHIP_FAMILY_CAYMAN, 0, 0, 0, 0, 0 },
+ { 0x6704, CHIP_FAMILY_CAYMAN, 0, 0, 0, 0, 0 },
+ { 0x6705, CHIP_FAMILY_CAYMAN, 0, 0, 0, 0, 0 },
+ { 0x6706, CHIP_FAMILY_CAYMAN, 0, 0, 0, 0, 0 },
+ { 0x6707, CHIP_FAMILY_CAYMAN, 0, 0, 0, 0, 0 },
+ { 0x6708, CHIP_FAMILY_CAYMAN, 0, 0, 0, 0, 0 },
+ { 0x6709, CHIP_FAMILY_CAYMAN, 0, 0, 0, 0, 0 },
+ { 0x6718, CHIP_FAMILY_CAYMAN, 0, 0, 0, 0, 0 },
+ { 0x6719, CHIP_FAMILY_CAYMAN, 0, 0, 0, 0, 0 },
+ { 0x671C, CHIP_FAMILY_CAYMAN, 0, 0, 0, 0, 0 },
+ { 0x671D, CHIP_FAMILY_CAYMAN, 0, 0, 0, 0, 0 },
{ 0x6720, CHIP_FAMILY_BARTS, 1, 0, 0, 0, 0 },
{ 0x6721, CHIP_FAMILY_BARTS, 1, 0, 0, 0, 0 },
{ 0x6722, CHIP_FAMILY_BARTS, 0, 0, 0, 0, 0 },
diff --git a/src/radeon_chipset_gen.h b/src/radeon_chipset_gen.h
index 2af046c..e4c38f0 100644
--- a/src/radeon_chipset_gen.h
+++ b/src/radeon_chipset_gen.h
@@ -420,6 +420,20 @@ static SymTabRec RADEONChipsets[] = {
{ PCI_CHIP_CEDAR_68F8, "CEDAR" },
{ PCI_CHIP_CEDAR_68F9, "ATI Radeon HD 5450" },
{ PCI_CHIP_CEDAR_68FE, "CEDAR" },
+ { PCI_CHIP_CAYMAN_6700, "CAYMAN" },
+ { PCI_CHIP_CAYMAN_6701, "CAYMAN" },
+ { PCI_CHIP_CAYMAN_6702, "CAYMAN" },
+ { PCI_CHIP_CAYMAN_6703, "CAYMAN" },
+ { PCI_CHIP_CAYMAN_6704, "CAYMAN" },
+ { PCI_CHIP_CAYMAN_6705, "CAYMAN" },
+ { PCI_CHIP_CAYMAN_6706, "CAYMAN" },
+ { PCI_CHIP_CAYMAN_6707, "CAYMAN" },
+ { PCI_CHIP_CAYMAN_6708, "CAYMAN" },
+ { PCI_CHIP_CAYMAN_6709, "CAYMAN" },
+ { PCI_CHIP_CAYMAN_6718, "AMD Radeon HD 6900 Series" },
+ { PCI_CHIP_CAYMAN_6719, "AMD Radeon HD 6900 Series" },
+ { PCI_CHIP_CAYMAN_671C, "CAYMAN" },
+ { PCI_CHIP_CAYMAN_671D, "CAYMAN" },
{ PCI_CHIP_BARTS_6720, "AMD Radeon HD 6900M Series" },
{ PCI_CHIP_BARTS_6721, "Mobility Radeon HD 6000 Series" },
{ PCI_CHIP_BARTS_6722, "BARTS" },
diff --git a/src/radeon_pci_chipset_gen.h b/src/radeon_pci_chipset_gen.h
index b4b2a79..1165049 100644
--- a/src/radeon_pci_chipset_gen.h
+++ b/src/radeon_pci_chipset_gen.h
@@ -420,6 +420,20 @@ PciChipsets RADEONPciChipsets[] = {
{ PCI_CHIP_CEDAR_68F8, PCI_CHIP_CEDAR_68F8, RES_SHARED_VGA },
{ PCI_CHIP_CEDAR_68F9, PCI_CHIP_CEDAR_68F9, RES_SHARED_VGA },
{ PCI_CHIP_CEDAR_68FE, PCI_CHIP_CEDAR_68FE, RES_SHARED_VGA },
+ { PCI_CHIP_CAYMAN_6700, PCI_CHIP_CAYMAN_6700, RES_SHARED_VGA },
+ { PCI_CHIP_CAYMAN_6701, PCI_CHIP_CAYMAN_6701, RES_SHARED_VGA },
+ { PCI_CHIP_CAYMAN_6702, PCI_CHIP_CAYMAN_6702, RES_SHARED_VGA },
+ { PCI_CHIP_CAYMAN_6703, PCI_CHIP_CAYMAN_6703, RES_SHARED_VGA },
+ { PCI_CHIP_CAYMAN_6704, PCI_CHIP_CAYMAN_6704, RES_SHARED_VGA },
+ { PCI_CHIP_CAYMAN_6705, PCI_CHIP_CAYMAN_6705, RES_SHARED_VGA },
+ { PCI_CHIP_CAYMAN_6706, PCI_CHIP_CAYMAN_6706, RES_SHARED_VGA },
+ { PCI_CHIP_CAYMAN_6707, PCI_CHIP_CAYMAN_6707, RES_SHARED_VGA },
+ { PCI_CHIP_CAYMAN_6708, PCI_CHIP_CAYMAN_6708, RES_SHARED_VGA },
+ { PCI_CHIP_CAYMAN_6709, PCI_CHIP_CAYMAN_6709, RES_SHARED_VGA },
+ { PCI_CHIP_CAYMAN_6718, PCI_CHIP_CAYMAN_6718, RES_SHARED_VGA },
+ { PCI_CHIP_CAYMAN_6719, PCI_CHIP_CAYMAN_6719, RES_SHARED_VGA },
+ { PCI_CHIP_CAYMAN_671C, PCI_CHIP_CAYMAN_671C, RES_SHARED_VGA },
+ { PCI_CHIP_CAYMAN_671D, PCI_CHIP_CAYMAN_671D, RES_SHARED_VGA },
{ PCI_CHIP_BARTS_6720, PCI_CHIP_BARTS_6720, RES_SHARED_VGA },
{ PCI_CHIP_BARTS_6721, PCI_CHIP_BARTS_6721, RES_SHARED_VGA },
{ PCI_CHIP_BARTS_6722, PCI_CHIP_BARTS_6722, RES_SHARED_VGA },
diff --git a/src/radeon_pci_device_match_gen.h
b/src/radeon_pci_device_match_gen.h
index aa50306..4bebfeb 100644
--- a/src/radeon_pci_device_match_gen.h
+++ b/src/radeon_pci_device_match_gen.h
@@ -420,6 +420,20 @@ static const struct pci_id_match radeon_device_match[] = {
ATI_DEVICE_MATCH( PCI_CHIP_CEDAR_68F8, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_CEDAR_68F9, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_CEDAR_68FE, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_CAYMAN_6700, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_CAYMAN_6701, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_CAYMAN_6702, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_CAYMAN_6703, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_CAYMAN_6704, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_CAYMAN_6705, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_CAYMAN_6706, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_CAYMAN_6707, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_CAYMAN_6708, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_CAYMAN_6709, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_CAYMAN_6718, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_CAYMAN_6719, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_CAYMAN_671C, 0 ),
+ ATI_DEVICE_MATCH( PCI_CHIP_CAYMAN_671D, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_BARTS_6720, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_BARTS_6721, 0 ),
ATI_DEVICE_MATCH( PCI_CHIP_BARTS_6722, 0 ),
commit fd65def45a57e3242596274d270791df8abc8e29
Author: Alex Deucher <alexdeuc...@gmail.com>
Date: Thu Jan 13 17:02:31 2011 -0500
kms: no accel yet for cayman
Signed-off-by: Alex Deucher <alexdeuc...@gmail.com>
diff --git a/src/radeon_kms.c b/src/radeon_kms.c
index b618045..125a132 100644
--- a/src/radeon_kms.c
+++ b/src/radeon_kms.c
@@ -258,6 +258,7 @@ static Bool RADEONPreInitAccel_KMS(ScrnInfoPtr pScrn)
}
if (xf86ReturnOptValBool(info->Options, OPTION_NOACCEL, FALSE) ||
+ (info->ChipFamily >= CHIP_FAMILY_CAYMAN) ||
(!RADEONIsAccelWorking(pScrn))) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"GPU accel disabled or not working, using shadowfb for
KMS\n");
commit 585e2a3b803b6d3e070f2427e9cb49bab0949239
Author: Alex Deucher <alexdeuc...@gmail.com>
Date: Thu Jan 13 16:58:01 2011 -0500
kms: add cayman chip family
KMS only. No UMS support for cayman.
Signed-off-by: Alex Deucher <alexdeuc...@gmail.com>
diff --git a/src/radeon.h b/src/radeon.h
index 4c43717..4f5095d 100644
--- a/src/radeon.h
+++ b/src/radeon.h
@@ -363,6 +363,7 @@ typedef enum {
CHIP_FAMILY_BARTS,
CHIP_FAMILY_TURKS,
CHIP_FAMILY_CAICOS,
+ CHIP_FAMILY_CAYMAN,
CHIP_FAMILY_LAST
} RADEONChipFamily;
commit 6835e22256ba7a74c02504383f63baaba7e87156
Author: Alex Deucher <alexdeuc...@gmail.com>
Date: Wed Mar 2 12:20:45 2011 -0500
r6xx+: truncate point sampled coordinates
By default the hardware rounds texcoords. However,
for point sampled textures, the expected behavior is
to truncate. When we have point sampled textures,
set the truncate bit in the sampler.
Signed-off-by: Alex Deucher <alexdeuc...@gmail.com>
diff --git a/src/evergreen_exa.c b/src/evergreen_exa.c
index e5e7559..553f05e 100644
--- a/src/evergreen_exa.c
+++ b/src/evergreen_exa.c
@@ -325,6 +325,7 @@ EVERGREENDoPrepareCopy(ScrnInfoPtr pScrn)
tex_samp.clamp_z = SQ_TEX_WRAP;
tex_samp.xy_mag_filter = SQ_TEX_XY_FILTER_POINT;
tex_samp.xy_min_filter = SQ_TEX_XY_FILTER_POINT;
+ tex_samp.mc_coord_truncate = 1;
tex_samp.z_filter = SQ_TEX_Z_FILTER_NONE;
tex_samp.mip_filter = 0; /* no mipmap */
evergreen_set_tex_sampler (pScrn, &tex_samp);
@@ -973,6 +974,7 @@ static Bool EVERGREENTextureSetup(PicturePtr pPict,
PixmapPtr pPix,
case PictFilterNearest:
tex_samp.xy_mag_filter = SQ_TEX_XY_FILTER_POINT;
tex_samp.xy_min_filter = SQ_TEX_XY_FILTER_POINT;
+ tex_samp.mc_coord_truncate = 1;
break;
case PictFilterBilinear:
tex_samp.xy_mag_filter = SQ_TEX_XY_FILTER_BILINEAR;
diff --git a/src/r600_exa.c b/src/r600_exa.c
index ab5e33b..57e5c0f 100644
--- a/src/r600_exa.c
+++ b/src/r600_exa.c
@@ -467,6 +467,7 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn)
tex_samp.clamp_z = SQ_TEX_WRAP;
tex_samp.xy_mag_filter = SQ_TEX_XY_FILTER_POINT;
tex_samp.xy_min_filter = SQ_TEX_XY_FILTER_POINT;
+ tex_samp.mc_coord_truncate = 1;
tex_samp.z_filter = SQ_TEX_Z_FILTER_NONE;
tex_samp.mip_filter = 0; /* no mipmap */
r600_set_tex_sampler(pScrn, accel_state->ib, &tex_samp);
@@ -1115,6 +1116,7 @@ static Bool R600TextureSetup(PicturePtr pPict, PixmapPtr
pPix,
case PictFilterNearest:
tex_samp.xy_mag_filter = SQ_TEX_XY_FILTER_POINT;
tex_samp.xy_min_filter = SQ_TEX_XY_FILTER_POINT;
+ tex_samp.mc_coord_truncate = 1;
break;
case PictFilterBilinear:
tex_samp.xy_mag_filter = SQ_TEX_XY_FILTER_BILINEAR;
commit 8a8862e4165dc5be779bce5e327a31da4826db3b
Author: Sedat Dilek <sedat.di...@googlemail.com>
Date: Sat Feb 26 21:04:22 2011 +0100
kms: Fix warning XNFprintf is deprecated (v2)
The first take of my patch missed the breakage against pre-1.10
xservers and now I know XNFasprintf() is not a 1:1 replacement
for XNFprintf().
The idea for the fix seemed to be so obvious, but as usual "really"
test the patch you are sending to any ML.
I am awfully sorry for the overhasty bad hack.
Thanks to Alan and Alex for the help to fix it correctly, now.
Tested-By: Sedat Dilek <sedat.di...@gmail.com>
Signed-off-by: Sedat Dilek <sedat.di...@gmail.com>
diff --git a/src/radeon_kms.c b/src/radeon_kms.c
index 4f6f120..b618045 100644
--- a/src/radeon_kms.c
+++ b/src/radeon_kms.c
@@ -409,8 +409,13 @@ static Bool radeon_open_drm_master(ScrnInfoPtr pScrn)
goto out;
}
+#if XORG_VERSION_CURRENT >= XORG_VERSION_NUMERIC(1,9,99,901,0)
+ XNFasprintf(&busid, "pci:%04x:%02x:%02x.%d",
+ dev->domain, dev->bus, dev->dev, dev->func);
+#else
busid = XNFprintf("pci:%04x:%02x:%02x.%d",
dev->domain, dev->bus, dev->dev, dev->func);
+#endif
info->dri2.drm_fd = drmOpen("radeon", busid);
if (info->dri2.drm_fd == -1) {
commit 88304fe9c0ce69012d44a77a5368c35236511dac
Author: Alex Deucher <alexdeuc...@gmail.com>
Date: Mon Feb 28 11:29:19 2011 -0500
kms: don't rotate if acceleration is not enabled
Signed-off-by: Alex Deucher <alexdeuc...@gmail.com>
diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index a972389..7873d57 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -445,6 +445,8 @@ drmmode_show_cursor (xf86CrtcPtr crtc)
static void *
drmmode_crtc_shadow_allocate(xf86CrtcPtr crtc, int width, int height)
{
+ ScrnInfoPtr pScrn = crtc->scrn;
+ RADEONInfoPtr info = RADEONPTR(pScrn);
drmmode_crtc_private_ptr drmmode_crtc = crtc->driver_private;
drmmode_ptr drmmode = drmmode_crtc->drmmode;
int size;
@@ -453,6 +455,13 @@ drmmode_crtc_shadow_allocate(xf86CrtcPtr crtc, int width,
int height)
unsigned long rotate_pitch;
int base_align;
+ /* rotation requires acceleration */
+ if (info->r600_shadow_fb) {
+ xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
+ "Rotation requires acceleration!\n");
+ return NULL;
+ }
+
rotate_pitch =
RADEON_ALIGN(width, drmmode_get_pitch_align(crtc->scrn,
drmmode->cpp, 0)) * drmmode->cpp;
height = RADEON_ALIGN(height, drmmode_get_height_align(crtc->scrn, 0));
commit 99141761e947e2153ed1a3bc485dc5716a22acb1
Author: Alex Deucher <alexdeuc...@gmail.com>
Date: Mon Feb 28 11:20:44 2011 -0500
kms: don't enable tiling if accel is off
Signed-off-by: Alex Deucher <alexdeuc...@gmail.com>
diff --git a/src/radeon_kms.c b/src/radeon_kms.c
index 158dc57..4f6f120 100644
--- a/src/radeon_kms.c
+++ b/src/radeon_kms.c
@@ -625,25 +625,31 @@ Bool RADEONPreInit_KMS(ScrnInfoPtr pScrn, int flags)
goto fail;
}
- colorTilingDefault = info->ChipFamily >= CHIP_FAMILY_R300 &&
- info->ChipFamily <= CHIP_FAMILY_RS740;
-
- if (info->ChipFamily >= CHIP_FAMILY_R600) {
- /* set default group bytes, overridden by kernel info below */
- info->group_bytes = 256;
- info->have_tiling_info = FALSE;
- if (info->dri->pKernelDRMVersion->version_minor >= 6) {
- if (r600_get_tile_config(pScrn))
- info->allowColorTiling = xf86ReturnOptValBool(info->Options,
-
OPTION_COLOR_TILING, colorTilingDefault);
- else
- info->allowColorTiling = FALSE;
+ if (!RADEONPreInitAccel_KMS(pScrn)) goto fail;
+
+ /* don't enable tiling if accel is not enabled */
+ if (!info->r600_shadow_fb) {
+ colorTilingDefault = info->ChipFamily >= CHIP_FAMILY_R300 &&
+ info->ChipFamily <= CHIP_FAMILY_RS740;
+
+ if (info->ChipFamily >= CHIP_FAMILY_R600) {
+ /* set default group bytes, overridden by kernel info below */
+ info->group_bytes = 256;
+ info->have_tiling_info = FALSE;
+ if (info->dri->pKernelDRMVersion->version_minor >= 6) {
+ if (r600_get_tile_config(pScrn))
+ info->allowColorTiling = xf86ReturnOptValBool(info->Options,
+
OPTION_COLOR_TILING, colorTilingDefault);
+ else
+ info->allowColorTiling = FALSE;
+ } else
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "R6xx+ KMS Color Tiling requires radeon drm 2.6.0 or
newer\n");
} else
- xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "R6xx+ KMS Color Tiling requires radeon drm 2.6.0 or
newer\n");
+ info->allowColorTiling = xf86ReturnOptValBool(info->Options,
+ OPTION_COLOR_TILING,
colorTilingDefault);
} else
- info->allowColorTiling = xf86ReturnOptValBool(info->Options,
- OPTION_COLOR_TILING,
colorTilingDefault);
+ info->allowColorTiling = FALSE;
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"KMS Color Tiling: %sabled\n", info->allowColorTiling ? "en" : "dis");
@@ -740,8 +746,6 @@ Bool RADEONPreInit_KMS(ScrnInfoPtr pScrn, int flags)
if (!xf86LoadSubModule(pScrn, "ramdac")) return FALSE;
}
- if (!RADEONPreInitAccel_KMS(pScrn)) goto fail;
-
if (pScrn->modes == NULL) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "No modes.\n");
goto fail;
commit 7928c120fb629a782846bcd5734d9fa14cbb099d
Author: Dave Airlie <airl...@redhat.com>
Date: Mon Feb 28 14:11:57 2011 +1000
xv: fix height alignments for U/V planes
The kernel CS checks showed we were incorrectly aligning the
U/V allocations for when we used them as texture sources.
This should fix
https://bugs.freedesktop.org/show_bug.cgi?id=34567
Signed-off-by: Dave Airlie <airl...@redhat.com>
diff --git a/src/radeon_textured_video.c b/src/radeon_textured_video.c
index 65a4871..c886ed0 100644
--- a/src/radeon_textured_video.c
+++ b/src/radeon_textured_video.c
@@ -248,7 +248,7 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
BoxRec dstBox;
int dst_width = width, dst_height = height;
int aligned_height;
-
+ int h_align = drmmode_get_height_align(pScrn, 0);
/* make the compiler happy */
s2offset = s3offset = srcPitch2 = 0;
@@ -299,7 +299,7 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
pPriv->hw_align = 64;
}
- aligned_height = RADEON_ALIGN(dst_height, drmmode_get_height_align(pScrn,
0));
+ aligned_height = RADEON_ALIGN(dst_height, h_align);
switch(id) {
case FOURCC_YV12:
@@ -323,7 +323,7 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
break;
}
- size = dstPitch * aligned_height + 2 * dstPitch2 * ((aligned_height + 1)
>> 1);
+ size = dstPitch * aligned_height + 2 * dstPitch2 *
RADEON_ALIGN(((aligned_height + 1) >> 1), h_align);
size = RADEON_ALIGN(size, pPriv->hw_align);
if (size != pPriv->size) {
@@ -401,9 +401,9 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
}
pPriv->src_pitch = dstPitch;
- pPriv->planeu_offset = dstPitch * dst_height;
+ pPriv->planeu_offset = dstPitch * aligned_height;
pPriv->planeu_offset = RADEON_ALIGN(pPriv->planeu_offset, pPriv->hw_align);
- pPriv->planev_offset = pPriv->planeu_offset + dstPitch2 * ((dst_height +
1) >> 1);
+ pPriv->planev_offset = pPriv->planeu_offset + dstPitch2 *
RADEON_ALIGN(((aligned_height + 1) >> 1), h_align);
pPriv->planev_offset = RADEON_ALIGN(pPriv->planev_offset, pPriv->hw_align);
pPriv->size = size;
commit e55520c0e582f2a500b3b01c2cb78750e15256ca
Author: Michel Dänzer <daen...@vmware.com>
Date: Sat Feb 26 15:27:59 2011 +0100
Revert "kms: Fix warning XNFprintf is deprecated"
This reverts commit cb4dc7ab66016d0c980800f8dbf71bbe993889d3.
Looks like this caused https://bugs.freedesktop.org/attachment.cgi?id=43852
,
but even if it didn't, the following needs to be addressed first:
cc1: warnings being treated as errors
../../src/radeon_kms.c: In function ‘radeon_open_drm_master’:
../../src/radeon_kms.c:413: error: passing argument 1 of ‘XNFasprintf’ from
incompatible pointer type
/usr/local/include/xorg/Xprintf.h:57: note: expected ‘char **’ but argument
is of type ‘char *’
../../src/radeon_kms.c:413: error: passing argument 2 of ‘XNFasprintf’
makes pointer from integer without a cast
/usr/local/include/xorg/Xprintf.h:57: note: expected ‘const char *
restrict’ but argument is of type ‘uint16_t’
../../src/radeon_kms.c:413: error: assignment makes pointer from integer
without a cast
make[2]: *** [radeon_kms.lo] Error 1
diff --git a/src/radeon_kms.c b/src/radeon_kms.c
index 82ee660..158dc57 100644
--- a/src/radeon_kms.c
+++ b/src/radeon_kms.c
@@ -408,13 +408,9 @@ static Bool radeon_open_drm_master(ScrnInfoPtr pScrn)
info->dri2.drm_fd = pRADEONEnt->fd;
goto out;
}
-#if XORG_VERSION_CURRENT >= XORG_VERSION_NUMERIC(1,9,99,901,0)
- busid = XNFasprintf("pci:%04x:%02x:%02x.%d",
- dev->domain, dev->bus, dev->dev, dev->func);
-#else
+
busid = XNFprintf("pci:%04x:%02x:%02x.%d",
dev->domain, dev->bus, dev->dev, dev->func);
-#endif
info->dri2.drm_fd = drmOpen("radeon", busid);
if (info->dri2.drm_fd == -1) {
commit cb4dc7ab66016d0c980800f8dbf71bbe993889d3
Author: Sedat Dilek <sedat.di...@gmail.com>
Date: Fri Feb 25 17:21:52 2011 -0500
kms: Fix warning XNFprintf is deprecated
Noticed when building ati/radeon ddx against xserver 1.10-rc3.
[ build.log ]
../../src/radeon_kms.c:412:5: warning: 'XNFprintf' is deprecated (declared
at /usr/include/xorg/os.h:273)
agd5f: don't break the build against pre-1.10 xservers.
Signed-off-by: Sedat Dilek <sedat.di...@gmail.com>
Signed-off-by: Alex Deucher <alexdeuc...@gmail.com>
diff --git a/src/radeon_kms.c b/src/radeon_kms.c
index 158dc57..82ee660 100644
--- a/src/radeon_kms.c
+++ b/src/radeon_kms.c
@@ -408,9 +408,13 @@ static Bool radeon_open_drm_master(ScrnInfoPtr pScrn)
info->dri2.drm_fd = pRADEONEnt->fd;
goto out;
}
-
+#if XORG_VERSION_CURRENT >= XORG_VERSION_NUMERIC(1,9,99,901,0)
+ busid = XNFasprintf("pci:%04x:%02x:%02x.%d",
+ dev->domain, dev->bus, dev->dev, dev->func);
+#else
busid = XNFprintf("pci:%04x:%02x:%02x.%d",
dev->domain, dev->bus, dev->dev, dev->func);
+#endif
info->dri2.drm_fd = drmOpen("radeon", busid);
if (info->dri2.drm_fd == -1) {
commit ecfdb209afe2aafc378baab8c511f5df7b000270
Author: Sedat Dilek <sedat.di...@googlemail.com>
Date: Fri Feb 25 21:48:14 2011 +0100
UMS: Fix build against xserver 1.10-rc3
This issue was introduced due to last minute backout of RandR-1.4
in xserver 1.10-rc3.
Switch to "#ifdef RANDR_14_INTERFACE" as suggested by Keith Packard.
See also <http://lists.x.org/archives/xorg-devel/2011-February/019643.html>.
Note:
The ddx needs a rebuild as the X video driver ABI changed to version 10.0.
Reported-by: Alex Deucher <alexdeuc...@gmail.com>
CC: Keith Packard <kei...@keithp.com>
Signed-off-by: Sedat Dilek <sedat.di...@gmail.com>
diff --git a/src/radeon_output.c b/src/radeon_output.c
index 15cef06..ccde346 100644
--- a/src/radeon_output.c
+++ b/src/radeon_output.c
@@ -1622,7 +1622,7 @@ radeon_set_mode_for_property(xf86OutputPtr output)
xf86CrtcPtr crtc = output->crtc;
if (crtc->enabled) {
-#if XORG_VERSION_CURRENT >= XORG_VERSION_NUMERIC(1,9,99,901,0)
+#ifdef RANDR_14_INTERFACE
xf86CrtcSetRec crtc_set_rec;
crtc_set_rec.flags = (XF86CrtcSetMode |
commit 04293a3a84acd96ccdf8e5e865cf973325ca43a1
Author: Alex Deucher <alexdeuc...@gmail.com>
Date: Thu Feb 24 02:33:41 2011 -0500
dri2: disable pageflipping for transformed displays
Based on Ben's nouveau patch.
Signed-off-by: Alex Deucher <alexdeuc...@gmail.com>
diff --git a/src/radeon_dri2.c b/src/radeon_dri2.c
index e8e16ff..66df03c 100644
--- a/src/radeon_dri2.c
+++ b/src/radeon_dri2.c
@@ -626,12 +626,21 @@ radeon_dri2_schedule_flip(ScrnInfoPtr scrn, ClientPtr
client,
}
static Bool
-can_exchange(DRI2BufferPtr front, DRI2BufferPtr back)
+can_exchange(ScrnInfoPtr pScrn,
+ DRI2BufferPtr front, DRI2BufferPtr back)
{
struct dri2_buffer_priv *front_priv = front->driverPrivate;
struct dri2_buffer_priv *back_priv = back->driverPrivate;
PixmapPtr front_pixmap = front_priv->pixmap;
PixmapPtr back_pixmap = back_priv->pixmap;
+ xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
+ int i;
+
+ for (i = 0; i < xf86_config->num_crtc; i++) {
+ xf86CrtcPtr crtc = xf86_config->crtc[i];
+ if (crtc->enabled && crtc->rotatedData)
+ return FALSE;
+ }
if (front_pixmap->drawable.width != back_pixmap->drawable.width)
return FALSE;
@@ -712,7 +721,7 @@ void radeon_dri2_frame_event_handler(unsigned int frame,
unsigned int tv_sec,
case DRI2_FLIP:
if (info->allowPageFlip &&
DRI2CanFlip(drawable) &&
- can_exchange(event->front, event->back) &&
+ can_exchange(scrn, event->front, event->back) &&
radeon_dri2_schedule_flip(scrn,
event->client,
drawable,
@@ -727,7 +736,7 @@ void radeon_dri2_frame_event_handler(unsigned int frame,
unsigned int tv_sec,
/* else fall through to exchange/blit */
case DRI2_SWAP:
if (DRI2CanExchange(drawable) &&
- can_exchange(event->front, event->back)) {
+ can_exchange(scrn, event->front, event->back)) {
radeon_dri2_exchange_buffers(drawable, event->front, event->back);
swap_type = DRI2_EXCHANGE_COMPLETE;
} else {
@@ -1075,7 +1084,7 @@ static int radeon_dri2_schedule_swap(ClientPtr client,
DrawablePtr draw,
/* Flips need to be submitted one frame before */
if (info->allowPageFlip &&
DRI2CanFlip(draw) &&
- can_exchange(front, back)) {
+ can_exchange(scrn, front, back)) {
swap_type = DRI2_FLIP;
flip = 1;
}
commit 91070cfd75d5607c4a72ace780f830f0ddb40e84
Author: Alex Deucher <alexdeuc...@gmail.com>
Date: Wed Feb 23 00:55:28 2011 -0500
Xv: use aligned height to calculate Xv buffer size
Make sure it's large enough for the tiling mode so the
CS checker doesn't complain. Should fix:
https://bugs.freedesktop.org/show_bug.cgi?id=34567
Signed-off-by: Alex Deucher <alexdeuc...@gmail.com>
diff --git a/src/radeon_textured_video.c b/src/radeon_textured_video.c
index f2c8f6a..65a4871 100644
--- a/src/radeon_textured_video.c
+++ b/src/radeon_textured_video.c
@@ -247,6 +247,7 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
int top, nlines, size;
BoxRec dstBox;
int dst_width = width, dst_height = height;
+ int aligned_height;
/* make the compiler happy */
s2offset = s3offset = srcPitch2 = 0;
@@ -298,6 +299,8 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
pPriv->hw_align = 64;
}
+ aligned_height = RADEON_ALIGN(dst_height, drmmode_get_height_align(pScrn,
0));
+
switch(id) {
case FOURCC_YV12:
case FOURCC_I420:
@@ -320,7 +323,7 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
break;
}
- size = dstPitch * dst_height + 2 * dstPitch2 * ((dst_height + 1) >> 1);
+ size = dstPitch * aligned_height + 2 * dstPitch2 * ((aligned_height + 1)
>> 1);
size = RADEON_ALIGN(size, pPriv->hw_align);
if (size != pPriv->size) {
commit acd54a48a6680956ed903fc890204c0c910b6712
Author: Mark Kettenis <kette...@openbsd.org>
Date: Sun Feb 20 22:51:04 2011 +0100
Properly restore CLOCK_CNTL_INDEX register
RADEONRestore() restores the CLOCK_CNTL_INDEX register before calling
RADEONRestorePLLRegisters(), which modifies the CLOCK_CNTL_INDEX register
to access the PLL registers. As a result we may end up with the wrong clock
being selected when exiting X. This happens on platforms where the driver
doesn't save and restore the VGA state.
Signed-off-by: Mark Kettenis <kette...@openbsd.org>
diff --git a/src/radeon_driver.c b/src/radeon_driver.c
index 20a81e6..35c2761 100644
--- a/src/radeon_driver.c
+++ b/src/radeon_driver.c
@@ -5825,8 +5825,6 @@ static void RADEONRestore(ScrnInfoPtr pScrn)
RADEONRestoreMemMapRegisters(pScrn, restore);
avivo_restore(pScrn, restore);
} else {
- OUTREG(RADEON_CLOCK_CNTL_INDEX, restore->clock_cntl_index);
- RADEONPllErrataAfterIndex(info);
OUTREG(RADEON_RBBM_SOFT_RESET, restore->rbbm_soft_reset);
OUTREG(RADEON_DP_DATATYPE, restore->dp_datatype);
OUTREG(RADEON_GRPH_BUFFER_CNTL, restore->grph_buffer_cntl);
@@ -5852,6 +5850,9 @@ static void RADEONRestore(ScrnInfoPtr pScrn)
RADEONRestoreTVRegisters(pScrn, restore);
}
+ OUTREG(RADEON_CLOCK_CNTL_INDEX, restore->clock_cntl_index);
+ RADEONPllErrataAfterIndex(info);
+
RADEONRestoreBIOSRegisters(pScrn, restore);
}
commit d7c2ba4286ea32401c0026cb92ec167f7b5753d8
Author: Alex Deucher <alexdeuc...@gmail.com>
Date: Wed Feb 16 18:30:34 2011 -0500
man: add btc chips to the list
Signed-off-by: Alex Deucher <alexdeuc...@gmail.com>
diff --git a/man/radeon.man b/man/radeon.man
index 285cb39..295b194 100644
--- a/man/radeon.man
+++ b/man/radeon.man
@@ -184,6 +184,15 @@ Radeon HD 5970
.TP 12
.B PALM
Radeon HD 6310/6250
+.TP 12
+.B BARTS
+Radeon HD 6850/6870
+.TP 12
+.B TURKS
+Radeon HD 6570/6670
+.TP 12
+.B CAICOS
+Radeon HD 6450
.PD
.SH CONFIGURATION DETAILS
Please refer to __xconfigfile__(__filemansuffix__) for general configuration
commit d0f8bffbbc26818eccdd305ef142387dc4975bba
Author: Alex Deucher <alexdeuc...@gmail.com>
Date: Wed Feb 16 15:09:20 2011 -0500
kms: add tiling support for evergreen/NI
- requires 2.6.37 or newer
- 1D only at the moment
- disabled by default
Signed-off-by: Alex Deucher <alexdeuc...@gmail.com>
diff --git a/src/radeon_kms.c b/src/radeon_kms.c
index 269a850..158dc57 100644
--- a/src/radeon_kms.c
+++ b/src/radeon_kms.c
@@ -472,8 +472,38 @@ static Bool r600_get_tile_config(ScrnInfoPtr pScrn)
info->tile_config = tmp;
info->r7xx_bank_op = 0;
if (info->ChipFamily >= CHIP_FAMILY_CEDAR) {
- /* for now */
- return FALSE;
+ if (info->dri->pKernelDRMVersion->version_minor >= 7) {
+ switch (info->tile_config & 0xf) {
+ case 0:
+ info->num_channels = 1;
+ break;
+ case 1:
--
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