configure.ac | 7
debian/changelog | 24
debian/control | 2
debian/patches/100_radeon-6.9.0-bgnr-enable.patch | 31
debian/patches/101_select_between_classic_and_gallium_dri.patch | 6
man/ati.man | 2
man/radeon.man | 187
src/Makefile.am | 7
src/ati_pciids_gen.h | 40
src/atombios_crtc.c | 26
src/atombios_output.c | 54
src/drmmode_display.c | 312
src/drmmode_display.h | 16
src/evergreen_accel.c | 1201 ++
src/evergreen_exa.c | 1953 ++++
src/evergreen_reg.h | 247
src/evergreen_reg_auto.h | 4039
++++++++++
src/evergreen_shader.c | 3124 +++++++
src/evergreen_shader.h | 292
src/evergreen_state.h | 341
src/evergreen_textured_videofuncs.c | 556 +
src/pcidb/ati_pciids.csv | 42
src/r600_exa.c | 169
src/r600_shader.c | 766 +
src/r600_shader.h | 4
src/r600_state.h | 42
src/r600_textured_videofuncs.c | 64
src/r6xx_accel.c | 124
src/radeon.h | 60
src/radeon_accel.c | 9
src/radeon_atombios.c | 5
src/radeon_bios.c | 1
src/radeon_chipinfo_gen.h | 40
src/radeon_chipset_gen.h | 42
src/radeon_commonfuncs.c | 2
src/radeon_crtc.c | 4
src/radeon_cursor.c | 41
src/radeon_dri2.c | 542 +
src/radeon_dri2.h | 2
src/radeon_driver.c | 903 +-
src/radeon_exa.c | 60
src/radeon_exa_render.c | 9
src/radeon_exa_shared.c | 51
src/radeon_exa_shared.h | 3
src/radeon_kms.c | 91
src/radeon_legacy_memory.c | 3
src/radeon_output.c | 3
src/radeon_pci_chipset_gen.h | 40
src/radeon_pci_device_match_gen.h | 40
src/radeon_probe.c | 1
src/radeon_probe.h | 50
src/radeon_reg.h | 6
src/radeon_textured_video.c | 36
src/radeon_textured_videofuncs.c | 2
src/radeon_vbo.c | 48
src/radeon_vbo.h | 54
src/radeon_video.c | 46
src/radeon_video.h | 1
58 files changed, 14800 insertions(+), 1073 deletions(-)
New commits:
commit f4fec3b25e4e99d3b6e363ad091176cb7a9495dd
Author: Christopher James Halse Rogers <christopher.halse.rog...@canonical.com>
Date: Mon Jan 31 19:02:31 2011 +1100
Merge Bryce's debian changes into git
diff --git a/debian/changelog b/debian/changelog
index 58fdb9e..6218a66 100644
--- a/debian/changelog
+++ b/debian/changelog
@@ -1,12 +1,22 @@
-xserver-xorg-video-ati (1:6.13.2-1ubuntu2) natty; urgency=low
+xserver-xorg-video-ati (1:6.13.2+git20110124.fadee040-0ubuntu1) natty;
urgency=low
- * debian/patches/101_select_between_classic_and_gallium_dri.patch
- + Select between r300c/r300g and r600c/r600g as the DRI driver. Classic
- drivers are selected when KMS is unavailable. Gallium is default for
- r300, classic for r600. This also adds a ForceGallium xorg.conf option
- to select between the two DRI drivers.
+ * Checkout from git 20110124 (master branch) up to commit
+ fadee0409a8e13b78bbccb83dd70f590fee23d57
+ - Enable 3D support for HD5670 and other late model cards
- -- Christopher James Halse Rogers <r...@ubuntu.com> Wed, 24 Nov 2010
11:00:48 +1100
+ [Bryce Harrington]
+ * debian/control: Drop 'linux-any' qualifier for libdrm dependency. Causes
FTBS
+ in pbuilder. (see deb bug 600823)
+ * Refresh 100_radeon-6.9.0-bgnr-enable.patch and address ABI change.
+
+ [Christopher James Halse Rogers]
+ * Add debian/patches/101_select_between_classic_and_gallium_dri.patch:
+ Select between r300c/r300g and r600c/r600g as the DRI driver. Classic
+ drivers are selected when KMS is unavailable. Gallium is default for
+ r300, classic for r600. This also adds a ForceGallium xorg.conf
+ option to select between the two DRI drivers.
+
+ -- Bryce Harrington <br...@ubuntu.com> Thu, 27 Jan 2011 16:23:33 -0800
xserver-xorg-video-ati (1:6.13.2-1ubuntu1) natty; urgency=low
diff --git a/debian/control b/debian/control
index 437da1e..62671d3 100644
--- a/debian/control
+++ b/debian/control
@@ -19,7 +19,7 @@ Build-Depends:
libdrm-dev (>= 2.4.17) [!hurd-i386],
x11proto-dri2-dev,
x11proto-xf86dri-dev,
- libudev-dev [linux-any],
+ libudev-dev,
dpkg-dev (>= 1.14.17),
automake,
libtool,
diff --git a/debian/patches/100_radeon-6.9.0-bgnr-enable.patch
b/debian/patches/100_radeon-6.9.0-bgnr-enable.patch
index eb1c135..a671a5f 100644
--- a/debian/patches/100_radeon-6.9.0-bgnr-enable.patch
+++ b/debian/patches/100_radeon-6.9.0-bgnr-enable.patch
@@ -1,18 +1,15 @@
-Description: Turn on option to allow xserver to skip drawing the root
background
- window for the radeon driver. This will make the boot up sequence smoother by
- eliminating one flicker.
- TESTERS: Watch for corruption or other ill effects during boot up.
-Author: Bryce Harrington <br...@ubuntu.com>
-
---- xserver-xorg-video-ati-6.12.191.orig/src/radeon_kms.c 2010-03-02
01:24:11.000000000 +0100
-+++ xserver-xorg-video-ati-6.12.191/src/radeon_kms.c 2010-03-07
22:33:18.244660337 +0100
-@@ -375,6 +375,9 @@
- if (pScrn->numEntities != 1) return FALSE;
- if (!RADEONGetRec(pScrn)) return FALSE;
+diff -Nurp patched//src/radeon_kms.c working//src/radeon_kms.c
+--- patched//src/radeon_kms.c 2011-01-27 19:20:35.454881380 -0800
++++ working//src/radeon_kms.c 2011-01-27 19:54:54.411057080 -0800
+@@ -840,6 +840,11 @@ Bool RADEONScreenInit_KMS(int scrnIndex,
+ int ret;
-+ /* kms bg root enable */
-+ pScrn->canDoBGNoneRoot = 1;
-+
- info = RADEONPTR(pScrn);
- info->MMIO = NULL;
- info->IsSecondary = FALSE;
+ pScrn->fbOffset = 0;
++#if GET_ABI_MAJOR(ABI_VIDEODRV_VERSION) >= 9
++ pScrn->pScreen->canDoBGNoneRoot = TRUE
++#else
++ pScrn->canDoBGNoneRoot = TRUE;
++#endif
+
+ miClearVisualTypes();
+ if (!miSetVisualTypes(pScrn->depth,
diff --git a/debian/patches/101_select_between_classic_and_gallium_dri.patch
b/debian/patches/101_select_between_classic_and_gallium_dri.patch
index 812116d..56351c8 100644
--- a/debian/patches/101_select_between_classic_and_gallium_dri.patch
+++ b/debian/patches/101_select_between_classic_and_gallium_dri.patch
@@ -14,9 +14,9 @@ Index: xserver-xorg-video-ati/src/radeon.h
OPTION_DYNAMIC_PM,
OPTION_NEW_PLL,
+ OPTION_FORCE_GALLIUM,
- OPTION_ZAPHOD_HEADS
- } RADEONOpts;
-
+ OPTION_ZAPHOD_HEADS,
+ OPTION_SWAPBUFFERS_WAIT
+ } RADEONOpts;
@@ -918,6 +919,7 @@
/* accel */
commit fadee0409a8e13b78bbccb83dd70f590fee23d57
Author: Alex Deucher <alexdeuc...@gmail.com>
Date: Fri Jan 21 17:30:28 2011 -0500
vbo: balance radeon_vbo_get() and radeon_vbo_put()
bo_ref() and bo_map() in radeon_vbo_get()
bo_unmap() and bo_unref() in radeon_vbo_put()
rather than doing the bo_map() separately in
radeon_vbo_space().
diff --git a/src/radeon_vbo.c b/src/radeon_vbo.c
index c0a668f..a72224f 100644
--- a/src/radeon_vbo.c
+++ b/src/radeon_vbo.c
@@ -56,8 +56,15 @@ void radeon_vbo_put(ScrnInfoPtr pScrn, struct
radeon_vbo_object *vbo)
void radeon_vbo_get(ScrnInfoPtr pScrn, struct radeon_vbo_object *vbo)
{
+ int ret;
vbo->vb_bo = radeon_vbo_get_bo(pScrn);
+ if (vbo->vb_bo) {
+ radeon_bo_ref(vbo->vb_bo);
+ ret = radeon_bo_map(vbo->vb_bo, 1);
+ if (ret)
+ FatalError("Failed to map vb %d\n", ret);
+ }
vbo->vb_total = VBO_SIZE;
vbo->vb_offset = 0;
@@ -195,7 +202,6 @@ again_alloc:
}
bo = first_elem(&accel_state->bo_reserved)->bo;
- radeon_bo_ref(bo);
return bo;
}
diff --git a/src/radeon_vbo.h b/src/radeon_vbo.h
index f64930e..583f262 100644
--- a/src/radeon_vbo.h
+++ b/src/radeon_vbo.h
@@ -35,19 +35,9 @@ radeon_vbo_space(ScrnInfoPtr pScrn,
vbo->vb_op_vert_size = vert_size;
#if defined(XF86DRM_MODE)
- if (info->cs) {
- int ret;
- struct radeon_bo *bo = vbo->vb_bo;
-
- if (!bo->ptr) {
- ret = radeon_bo_map(bo, 1);
- if (ret) {
- FatalError("Failed to map vb %d\n", ret);
- return NULL;
- }
- }
- vb = (pointer)((char *)bo->ptr + vbo->vb_offset);
- } else
+ if (info->cs)
+ vb = (pointer)((char *)vbo->vb_bo->ptr + vbo->vb_offset);
+ else
#endif
vb = (pointer)((char *)vbo->vb_ptr + vbo->vb_offset);
return vb;
commit af7d81625a8cf873e6efc881489b3eda9861bd03
Author: Alex Deucher <alexdeuc...@gmail.com>
Date: Fri Jan 21 17:01:25 2011 -0500
evergreen: use vb_offset rather than vb_start_op for cbuf offset
diff --git a/src/evergreen_exa.c b/src/evergreen_exa.c
index bb68577..93fa267 100644
--- a/src/evergreen_exa.c
+++ b/src/evergreen_exa.c
@@ -281,6 +281,8 @@ EVERGREENPrepareSolid(PixmapPtr pPix, int alu, Pixel pm,
Pixel fg)
ps_const_conf.size_bytes = 256;
ps_const_conf.type = SHADER_TYPE_PS;
ps_alu_consts = radeon_vbo_space(pScrn, &accel_state->cbuf, 256);
+ ps_const_conf.bo = accel_state->cbuf.vb_bo;
+ ps_const_conf.const_addr = accel_state->cbuf.vb_mc_addr +
accel_state->cbuf.vb_offset;
if (accel_state->dst_obj.bpp == 16) {
r = (fg >> 11) & 0x1f;
g = (fg >> 5) & 0x3f;
@@ -306,9 +308,6 @@ EVERGREENPrepareSolid(PixmapPtr pPix, int alu, Pixel pm,
Pixel fg)
ps_alu_consts[3] = (float)a / 255; /* A */
}
radeon_vbo_commit(pScrn, &accel_state->cbuf);
-
- ps_const_conf.bo = accel_state->cbuf.vb_bo;
- ps_const_conf.const_addr = accel_state->cbuf.vb_mc_addr +
accel_state->cbuf.vb_start_op;
evergreen_set_alu_consts(pScrn, &ps_const_conf, RADEON_GEM_DOMAIN_GTT);
if (accel_state->vsync)
@@ -1412,16 +1411,14 @@ static Bool EVERGREENPrepareComposite(int op,
PicturePtr pSrcPicture,
vs_const_conf.size_bytes = 256;
vs_const_conf.type = SHADER_TYPE_VS;
cbuf = radeon_vbo_space(pScrn, &accel_state->cbuf, 256);
+ vs_const_conf.bo = accel_state->cbuf.vb_bo;
+ vs_const_conf.const_addr = accel_state->cbuf.vb_mc_addr +
accel_state->cbuf.vb_offset;
EVERGREENXFormSetup(pSrcPicture, pSrc, 0, cbuf);
if (pMask)
EVERGREENXFormSetup(pMaskPicture, pMask, 1, cbuf);
radeon_vbo_commit(pScrn, &accel_state->cbuf);
-
- /* VS alu constants */
- vs_const_conf.bo = accel_state->cbuf.vb_bo;
- vs_const_conf.const_addr = accel_state->cbuf.vb_mc_addr +
accel_state->cbuf.vb_start_op;
evergreen_set_alu_consts(pScrn, &vs_const_conf, RADEON_GEM_DOMAIN_GTT);
if (accel_state->vsync)
diff --git a/src/evergreen_textured_videofuncs.c
b/src/evergreen_textured_videofuncs.c
index aa3c527..d60d194 100644
--- a/src/evergreen_textured_videofuncs.c
+++ b/src/evergreen_textured_videofuncs.c
@@ -452,6 +452,8 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn,
RADEONPortPrivPtr pPriv)
ps_const_conf.size_bytes = 256;
ps_const_conf.type = SHADER_TYPE_PS;
ps_alu_consts = radeon_vbo_space(pScrn, &accel_state->cbuf, 256);
+ ps_const_conf.bo = accel_state->cbuf.vb_bo;
+ ps_const_conf.const_addr = accel_state->cbuf.vb_mc_addr +
accel_state->cbuf.vb_offset;
ps_alu_consts[0] = off[0];
ps_alu_consts[1] = off[1];
@@ -469,16 +471,14 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn,
RADEONPortPrivPtr pPriv)
ps_alu_consts[11] = 0.0;
radeon_vbo_commit(pScrn, &accel_state->cbuf);
-
- /* PS alu constants */
- ps_const_conf.bo = accel_state->cbuf.vb_bo;
- ps_const_conf.const_addr = accel_state->cbuf.vb_mc_addr +
accel_state->cbuf.vb_start_op;
evergreen_set_alu_consts(pScrn, &ps_const_conf, RADEON_GEM_DOMAIN_GTT);
/* VS alu constants */
vs_const_conf.size_bytes = 256;
vs_const_conf.type = SHADER_TYPE_VS;
vs_alu_consts = radeon_vbo_space(pScrn, &accel_state->cbuf, 256);
+ vs_const_conf.bo = accel_state->cbuf.vb_bo;
+ vs_const_conf.const_addr = accel_state->cbuf.vb_mc_addr +
accel_state->cbuf.vb_offset;
vs_alu_consts[0] = 1.0 / pPriv->w;
vs_alu_consts[1] = 1.0 / pPriv->h;
@@ -486,10 +486,6 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn,
RADEONPortPrivPtr pPriv)
vs_alu_consts[3] = 0.0;
radeon_vbo_commit(pScrn, &accel_state->cbuf);
-
- /* VS alu constants */
- vs_const_conf.bo = accel_state->cbuf.vb_bo;
- vs_const_conf.const_addr = accel_state->cbuf.vb_mc_addr +
accel_state->cbuf.vb_start_op + 256;
evergreen_set_alu_consts(pScrn, &vs_const_conf, RADEON_GEM_DOMAIN_GTT);
if (pPriv->vsync) {
commit 4817fac5f728b777939e2e2bee16b842c9e1367b
Author: Alex Deucher <alexdeuc...@gmail.com>
Date: Fri Jan 21 15:59:32 2011 -0500
vbo: remove useless radeon_vb_discard()
We already reset vb_start_op to -1 in the
UMS/KMS ib discard functions.
diff --git a/src/evergreen_accel.c b/src/evergreen_accel.c
index b46e61d..4f5a120 100644
--- a/src/evergreen_accel.c
+++ b/src/evergreen_accel.c
@@ -1162,8 +1162,6 @@ void evergreen_finish_op(ScrnInfoPtr pScrn, int vtx_size)
if (accel_state->vbo.vb_offset == accel_state->vbo.vb_start_op) {
radeon_ib_discard(pScrn);
radeon_cs_flush_indirect(pScrn);
- radeon_vb_discard(pScrn, &accel_state->vbo);
- radeon_vb_discard(pScrn, &accel_state->cbuf);
return;
}
diff --git a/src/evergreen_exa.c b/src/evergreen_exa.c
index 0fe00d8..bb68577 100644
--- a/src/evergreen_exa.c
+++ b/src/evergreen_exa.c
@@ -1291,8 +1291,6 @@ static Bool EVERGREENPrepareComposite(int op, PicturePtr
pSrcPicture,
if (!EVERGREENTextureSetup(pSrcPicture, pSrc, 0)) {
radeon_ib_discard(pScrn);
radeon_cs_flush_indirect(pScrn);
- radeon_vb_discard(pScrn, &accel_state->vbo);
- radeon_vb_discard(pScrn, &accel_state->cbuf);
return FALSE;
}
@@ -1300,8 +1298,6 @@ static Bool EVERGREENPrepareComposite(int op, PicturePtr
pSrcPicture,
if (!EVERGREENTextureSetup(pMaskPicture, pMask, 1)) {
radeon_ib_discard(pScrn);
radeon_cs_flush_indirect(pScrn);
- radeon_vb_discard(pScrn, &accel_state->vbo);
- radeon_vb_discard(pScrn, &accel_state->cbuf);
return FALSE;
}
} else
diff --git a/src/r600_exa.c b/src/r600_exa.c
index 5dfc770..f652ab6 100644
--- a/src/r600_exa.c
+++ b/src/r600_exa.c
@@ -1334,14 +1334,12 @@ static Bool R600PrepareComposite(int op, PicturePtr
pSrcPicture,
if (!R600TextureSetup(pSrcPicture, pSrc, 0)) {
R600IBDiscard(pScrn, accel_state->ib);
- radeon_vb_discard(pScrn, &accel_state->vbo);
return FALSE;
}
if (pMask) {
if (!R600TextureSetup(pMaskPicture, pMask, 1)) {
R600IBDiscard(pScrn, accel_state->ib);
- radeon_vb_discard(pScrn, &accel_state->vbo);
return FALSE;
}
} else
@@ -1644,7 +1642,6 @@ R600CopyToVRAM(ScrnInfoPtr pScrn,
}
R600IBDiscard(pScrn, scratch);
- radeon_vb_discard(pScrn, &accel_state->vbo);
return TRUE;
}
@@ -1758,7 +1755,6 @@ R600DownloadFromScreen(PixmapPtr pSrc, int x, int y, int
w, int h,
}
R600IBDiscard(pScrn, scratch);
- radeon_vb_discard(pScrn, &accel_state->vbo);
return TRUE;
diff --git a/src/r6xx_accel.c b/src/r6xx_accel.c
index e436514..0c7714a 100644
--- a/src/r6xx_accel.c
+++ b/src/r6xx_accel.c
@@ -71,6 +71,9 @@ void R600CPFlushIndirect(ScrnInfoPtr pScrn, drmBufPtr ib)
END_BATCH();
}
+ info->accel_state->vbo.vb_offset = 0;
+ info->accel_state->vbo.vb_start_op = -1;
+
//ErrorF("buffer bytes: %d\n", buffer->used);
indirect.idx = buffer->idx;
@@ -1173,7 +1176,6 @@ void r600_finish_op(ScrnInfoPtr pScrn, int vtx_size)
if (accel_state->vbo.vb_offset == accel_state->vbo.vb_start_op) {
R600IBDiscard(pScrn, accel_state->ib);
- radeon_vb_discard(pScrn, &accel_state->vbo);
return;
}
diff --git a/src/radeon_exa_shared.c b/src/radeon_exa_shared.c
index 2ef0751..be1d2fa 100644
--- a/src/radeon_exa_shared.c
+++ b/src/radeon_exa_shared.c
@@ -141,11 +141,6 @@ static Bool radeon_vb_get(ScrnInfoPtr pScrn)
return TRUE;
}
-void radeon_vb_discard(ScrnInfoPtr pScrn, struct radeon_vbo_object *vbo)
-{
- vbo->vb_start_op = -1;
-}
-
int radeon_cp_start(ScrnInfoPtr pScrn)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
diff --git a/src/radeon_exa_shared.h b/src/radeon_exa_shared.h
index 489e3b0..7b8b5ca 100644
--- a/src/radeon_exa_shared.h
+++ b/src/radeon_exa_shared.h
@@ -72,7 +72,6 @@ static inline void radeon_add_pixmap(struct radeon_cs *cs,
PixmapPtr pPix, int r
extern void radeon_ib_discard(ScrnInfoPtr pScrn);
#endif /* XF86DRM_MODE */
-extern void radeon_vb_discard(ScrnInfoPtr pScrn, struct radeon_vbo_object
*vbo);
extern int radeon_cp_start(ScrnInfoPtr pScrn);
extern void radeon_vb_no_space(ScrnInfoPtr pScrn, struct radeon_vbo_object
*vbo, int vert_size);
extern void radeon_vbo_done_composite(PixmapPtr pDst);
commit 0a03f03a65aad925ba2d9c76b1d3356184607bf9
Author: Alex Deucher <alexdeuc...@gmail.com>
Date: Thu Jan 20 17:07:32 2011 -0500
evergreen/ni: fix Xv artifacts
Port of the 6xx/7xx fix to evergreen. Bad texture size
for texture cache flush.
diff --git a/src/evergreen_textured_videofuncs.c
b/src/evergreen_textured_videofuncs.c
index 428876f..aa3c527 100644
--- a/src/evergreen_textured_videofuncs.c
+++ b/src/evergreen_textured_videofuncs.c
@@ -295,7 +295,7 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn,
RADEONPortPrivPtr pPriv)
tex_res.base = accel_state->src_obj[0].offset +
pPriv->planev_offset;
tex_res.mip_base = accel_state->src_obj[0].offset +
pPriv->planev_offset;
- tex_res.size = accel_state->src_size[0] / 4;
+ tex_res.size = tex_res.pitch * (pPriv->h >> 1);
evergreen_set_tex_resource(pScrn, &tex_res,
accel_state->src_obj[0].domain);
/* U or V sampler */
@@ -316,7 +316,7 @@ EVERGREENDisplayTexturedVideo(ScrnInfoPtr pScrn,
RADEONPortPrivPtr pPriv)
tex_res.base = accel_state->src_obj[0].offset +
pPriv->planeu_offset;
tex_res.mip_base = accel_state->src_obj[0].offset +
pPriv->planeu_offset;
- tex_res.size = accel_state->src_size[0] / 4;
+ tex_res.size = tex_res.pitch * (pPriv->h >> 1);
evergreen_set_tex_resource(pScrn, &tex_res,
accel_state->src_obj[0].domain);
/* UV sampler */
commit f41cf83750ba9a2e0797fdb21ea9104b85ce53aa
Author: Marton Balint <c...@fazekas.hu>
Date: Thu Jan 20 17:04:56 2011 -0500
r6xx/7xx: fix Xv artifacts
bad textures size for cache flushes.
Fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=22007
diff --git a/src/r600_textured_videofuncs.c b/src/r600_textured_videofuncs.c
index 88073ac..f71a61b 100644
--- a/src/r600_textured_videofuncs.c
+++ b/src/r600_textured_videofuncs.c
@@ -310,7 +310,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn,
RADEONPortPrivPtr pPriv)
tex_res.base = accel_state->src_obj[0].offset +
pPriv->planev_offset;
tex_res.mip_base = accel_state->src_obj[0].offset +
pPriv->planev_offset;
- tex_res.size = accel_state->src_size[0] / 4;
+ tex_res.size = tex_res.pitch * (pPriv->h >> 1);
r600_set_tex_resource(pScrn, accel_state->ib, &tex_res,
accel_state->src_obj[0].domain);
/* U or V sampler */
@@ -331,7 +331,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn,
RADEONPortPrivPtr pPriv)
tex_res.base = accel_state->src_obj[0].offset +
pPriv->planeu_offset;
tex_res.mip_base = accel_state->src_obj[0].offset +
pPriv->planeu_offset;
- tex_res.size = accel_state->src_size[0] / 4;
+ tex_res.size = tex_res.pitch * (pPriv->h >> 1);
r600_set_tex_resource(pScrn, accel_state->ib, &tex_res,
accel_state->src_obj[0].domain);
/* UV sampler */
commit 57fbddfc21d8c6794f378489b764cc2a0ad4a48c
Author: Michel Dänzer <daen...@vmware.com>
Date: Tue Jan 18 16:07:52 2011 +0100
Fix crash freeing KMS video memory.
Where's that brown paper bag? :}
diff --git a/src/radeon_video.c b/src/radeon_video.c
index 4355f8b..58e3920 100644
--- a/src/radeon_video.c
+++ b/src/radeon_video.c
@@ -1656,7 +1656,7 @@ RADEONFreeVideoMemory(ScrnInfoPtr pScrn,
RADEONPortPrivPtr pPriv)
if (info->cs && pPriv->textured) {
pPriv->src_bo[0] = NULL;
- radeon_legacy_free_memory(pScrn, (void*)&pPriv->src_bo[1]);
+ radeon_legacy_free_memory(pScrn, pPriv->src_bo[1]);
pPriv->src_bo[1] = NULL;
}
}
commit 6548bb9836253c586023ffe5ad1497ddabaa50fc
Author: Michel Dänzer <daen...@vmware.com>
Date: Tue Jan 18 10:23:41 2011 +0100
Fix KMS textured video leaks (bug #33193).
v2: Fix radeon_legacy_free_memory() argument type error pointed out by
Marton Balint, refactor video memory freeing logic into helper function.
Fixes https://bugs.freedesktop.org/show_bug.cgi?id=33193 .
diff --git a/src/radeon_legacy_memory.c b/src/radeon_legacy_memory.c
index 3e75291..32d8c79 100644
--- a/src/radeon_legacy_memory.c
+++ b/src/radeon_legacy_memory.c
@@ -26,6 +26,9 @@ radeon_legacy_allocate_memory(ScrnInfoPtr pScrn,
if (info->cs) {
struct radeon_bo *video_bo;
+ if (*mem_struct)
+ radeon_legacy_free_memory(pScrn, *mem_struct);
+
video_bo = radeon_bo_open(info->bufmgr, 0, size, RADEON_GPU_PAGE_SIZE,
domain, 0);
*mem_struct = video_bo;
diff --git a/src/radeon_textured_video.c b/src/radeon_textured_video.c
index 36bcb56..163ee48 100644
--- a/src/radeon_textured_video.c
+++ b/src/radeon_textured_video.c
@@ -314,9 +314,8 @@ RADEONPutImageTextured(ScrnInfoPtr pScrn,
size = dstPitch * dst_height + 2 * dstPitch2 * ((dst_height + 1) >> 1);
size = RADEON_ALIGN(size, hw_align);
- if (pPriv->video_memory != NULL && size != pPriv->size) {
- radeon_legacy_free_memory(pScrn, pPriv->video_memory);
- pPriv->video_memory = NULL;
+ if (size != pPriv->size) {
+ RADEONFreeVideoMemory(pScrn, pPriv);
}
if (pPriv->video_memory == NULL) {
diff --git a/src/radeon_video.c b/src/radeon_video.c
index 0bb5ab3..4355f8b 100644
--- a/src/radeon_video.c
+++ b/src/radeon_video.c
@@ -1646,6 +1646,23 @@ RADEONSetupImageVideo(ScreenPtr pScreen)
}
void
+RADEONFreeVideoMemory(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
+{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+
+ if (pPriv->video_memory != NULL) {
+ radeon_legacy_free_memory(pScrn, pPriv->video_memory);
+ pPriv->video_memory = NULL;
+
+ if (info->cs && pPriv->textured) {
+ pPriv->src_bo[0] = NULL;
+ radeon_legacy_free_memory(pScrn, (void*)&pPriv->src_bo[1]);
+ pPriv->src_bo[1] = NULL;
+ }
+ }
+}
+
+void
RADEONStopVideo(ScrnInfoPtr pScrn, pointer data, Bool cleanup)
{
RADEONInfoPtr info = RADEONPTR(pScrn);
@@ -1654,10 +1671,7 @@ RADEONStopVideo(ScrnInfoPtr pScrn, pointer data, Bool
cleanup)
if (pPriv->textured) {
if (cleanup) {
- if (pPriv->video_memory != NULL) {
- radeon_legacy_free_memory(pScrn, pPriv->video_memory);
- pPriv->video_memory = NULL;
- }
+ RADEONFreeVideoMemory(pScrn, pPriv);
}
return;
}
@@ -1679,10 +1693,7 @@ RADEONStopVideo(ScrnInfoPtr pScrn, pointer data, Bool
cleanup)
if(pPriv->uda1380 != NULL) xf86_uda1380_mute(pPriv->uda1380,
TRUE);
if(pPriv->i2c != NULL) RADEON_board_setmisc(pPriv);
}
- if (pPriv->video_memory != NULL) {
- radeon_legacy_free_memory(pScrn, pPriv->video_memory);
- pPriv->video_memory = NULL;
- }
+ RADEONFreeVideoMemory(pScrn, pPriv);
pPriv->videoStatus = 0;
} else {
if(pPriv->videoStatus & CLIENT_VIDEO_ON) {
@@ -3152,10 +3163,7 @@ RADEONVideoTimerCallback(ScrnInfoPtr pScrn, Time now)
}
} else { /* FREE_TIMER */
if(pPriv->freeTime < now) {
- if (pPriv->video_memory != NULL) {
- radeon_legacy_free_memory(pScrn, pPriv->video_memory);
- pPriv->video_memory = NULL;
- }
+ RADEONFreeVideoMemory(pScrn, pPriv);
pPriv->videoStatus = 0;
info->VideoTimerCallback = NULL;
}
diff --git a/src/radeon_video.h b/src/radeon_video.h
index ab0c433..c315bbb 100644
--- a/src/radeon_video.h
+++ b/src/radeon_video.h
@@ -150,6 +150,7 @@ void RADEONVIP_reset(ScrnInfoPtr pScrn, RADEONPortPrivPtr
pPriv);
int RADEONSetPortAttribute(ScrnInfoPtr, Atom, INT32, pointer);
int RADEONGetPortAttribute(ScrnInfoPtr, Atom ,INT32 *, pointer);
+void RADEONFreeVideoMemory(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv);
void RADEONStopVideo(ScrnInfoPtr, pointer, Bool);
void RADEONQueryBestSize(ScrnInfoPtr, Bool, short, short, short, short,
unsigned int *, unsigned int *, pointer);
commit edc3496b55577ee8509ddd9188e6f2bcdf7169a1
Author: Dave Airlie <airl...@redhat.com>
Date: Mon Jan 17 07:55:29 2011 +1000
radeon: add back flush in block handler.
this is also needed for certain things like stipple rendering.
Signed-off-by: Dave Airlie <airl...@redhat.com>
diff --git a/src/radeon_kms.c b/src/radeon_kms.c
index 59f8281..fbdb530 100644
--- a/src/radeon_kms.c
+++ b/src/radeon_kms.c
@@ -207,6 +207,7 @@ static void RADEONBlockHandler_KMS(int i, pointer blockData,
if (info->VideoTimerCallback)
(*info->VideoTimerCallback)(pScrn, currentTime.milliseconds);
+ radeon_cs_flush_indirect(pScrn);
}
static void
commit 63d7dece3f4be8b14012b3a2bedd850831c0437b
Author: Alex Deucher <alexdeuc...@gmail.com>
Date: Thu Jan 13 11:24:26 2011 -0500
rs880 fix typo in HD 4250 string
Noticed by Nigel Taylor
Fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=33057
diff --git a/src/pcidb/ati_pciids.csv b/src/pcidb/ati_pciids.csv
index 61b04b9..1f4756a 100644
--- a/src/pcidb/ati_pciids.csv
+++ b/src/pcidb/ati_pciids.csv
@@ -458,7 +458,7 @@
"0x9712","RS880_9712","RS880",1,1,,,1,"ATI Mobility Radeon HD 4200"
"0x9713","RS880_9713","RS880",1,1,,,1,"ATI Mobility Radeon 4100"
"0x9714","RS880_9714","RS880",,1,,,1,"ATI Radeon HD 4290"
-"0x9715","RS880_9715","RS880",,1,,,1,"ATI Radeon HD 4290"
+"0x9715","RS880_9715","RS880",,1,,,1,"ATI Radeon HD 4250"
"0x9802","PALM_9802","PALM",,1,,,1,"AMD Radeon HD 6310 Graphics"
"0x9803","PALM_9803","PALM",,1,,,1,"AMD Radeon HD 6310 Graphics"
"0x9804","PALM_9804","PALM",,1,,,1,"AMD Radeon HD 6250 Graphics"
diff --git a/src/radeon_chipset_gen.h b/src/radeon_chipset_gen.h
index 66655e2..09a957e 100644
--- a/src/radeon_chipset_gen.h
+++ b/src/radeon_chipset_gen.h
@@ -377,7 +377,7 @@ static SymTabRec RADEONChipsets[] = {
{ PCI_CHIP_RS880_9712, "ATI Mobility Radeon HD 4200" },
{ PCI_CHIP_RS880_9713, "ATI Mobility Radeon 4100" },
{ PCI_CHIP_RS880_9714, "ATI Radeon HD 4290" },
- { PCI_CHIP_RS880_9715, "ATI Radeon HD 4290" },
+ { PCI_CHIP_RS880_9715, "ATI Radeon HD 4250" },
{ PCI_CHIP_PALM_9802, "AMD Radeon HD 6310 Graphics" },
{ PCI_CHIP_PALM_9803, "AMD Radeon HD 6310 Graphics" },
{ PCI_CHIP_PALM_9804, "AMD Radeon HD 6250 Graphics" },
commit c5b3db18d888552328e9718ea022794fc5bde352
Author: Alex Deucher <alexdeuc...@gmail.com>
Date: Tue Jan 11 16:21:18 2011 -0500
kms: fix pitch aligment for scanout
Display has slightly stricter pitch alignment requirements
than other blocks. Factor that in when aligning pitch.
Fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=32997
diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index b7d01c4..2ab4510 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -1118,14 +1118,25 @@ int drmmode_get_pitch_align(ScrnInfoPtr scrn, int bpe,
uint32_t tiling)
int pitch_align = 1;
if (info->ChipFamily >= CHIP_FAMILY_R600) {
- if (tiling & RADEON_TILING_MACRO)
+ if (tiling & RADEON_TILING_MACRO) {
+ /* general surface requirements */
pitch_align = MAX(info->num_banks,
(((info->group_bytes / 8) / bpe) *
info->num_banks)) * 8;
- else if (tiling & RADEON_TILING_MICRO)
+ /* further restrictions for scanout */
+ pitch_align = MAX(info->num_banks * 8, pitch_align);
+ } else if (tiling & RADEON_TILING_MICRO) {
+ /* general surface requirements */
pitch_align = MAX(8, (info->group_bytes / (8 * bpe)));
- else
+ /* further restrictions for scanout */
+ pitch_align = MAX(info->group_bytes / bpe, pitch_align);
+ } else {
+ /* general surface requirements */
pitch_align = info->group_bytes / bpe;
+ /* further restrictions for scanout */
+ pitch_align = MAX(32, pitch_align);
+ }
} else {
+ /* general surface requirements */
if (tiling)
pitch_align = 256 / bpe;
else
commit bbd7adce889359b5eb3239b73e904b3ede283e12
Author: Alex Deucher <alexdeuc...@gmail.com>
Date: Tue Jan 11 15:41:03 2011 -0500
radeon: fix yet another pitch align
diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index 55e76ff..b7d01c4 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -204,7 +204,8 @@ void drmmode_copy_fb(ScrnInfoPtr pScrn, drmmode_ptr drmmode)
ScreenPtr pScreen = pScrn->pScreen;
int crtc_id = 0;
int i;
- int pitch = pScrn->displayWidth * info->CurrentLayout.pixel_bytes;
+ int pitch;
+ uint32_t tiling_flags = 0;
Bool ret;
if (info->accelOn == FALSE)
@@ -223,6 +224,17 @@ void drmmode_copy_fb(ScrnInfoPtr pScrn, drmmode_ptr
drmmode)
if (!src)
return;
+ if (info->allowColorTiling) {
+ if (info->ChipFamily >= CHIP_FAMILY_R600)
+ tiling_flags |= RADEON_TILING_MICRO;
+ else
+ tiling_flags |= RADEON_TILING_MACRO;
+ }
+
+ pitch = RADEON_ALIGN(pScrn->displayWidth,
+ drmmode_get_pitch_align(pScrn,
info->CurrentLayout.pixel_bytes, tiling_flags)) *
+ info->CurrentLayout.pixel_bytes;
+
dst = drmmode_create_bo_pixmap(pScreen, pScrn->virtualX,
pScrn->virtualY, pScrn->depth,
pScrn->bitsPerPixel, pitch,
commit af2e6d7d2f1b3d8f8f6b0acfb2b7b0cfaff7bcdb
Author: Alex Deucher <alexdeuc...@gmail.com>
Date: Tue Jan 11 14:42:17 2011 -0500
radeon: fix pitch align in pageflip code
diff --git a/src/drmmode_display.c b/src/drmmode_display.c
index 9248cb0..55e76ff 100644
--- a/src/drmmode_display.c
+++ b/src/drmmode_display.c
@@ -1604,7 +1604,7 @@ Bool radeon_do_pageflip(ScrnInfoPtr scrn, struct
radeon_bo *new_front, void *dat
xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(scrn);
drmmode_crtc_private_ptr drmmode_crtc = config->crtc[0]->driver_private;
drmmode_ptr drmmode = drmmode_crtc->drmmode;
- unsigned int pitch = scrn->displayWidth *
info->CurrentLayout.pixel_bytes;
+ unsigned int pitch;
int i, old_fb_id;
uint32_t tiling_flags = 0;
int height;
@@ -1617,7 +1617,8 @@ Bool radeon_do_pageflip(ScrnInfoPtr scrn, struct
radeon_bo *new_front, void *dat
tiling_flags |= RADEON_TILING_MACRO;
}
- pitch = RADEON_ALIGN(pitch, drmmode_get_pitch_align(scrn,
info->CurrentLayout.pixel_bytes, tiling_flags));
+ pitch = RADEON_ALIGN(scrn->displayWidth, drmmode_get_pitch_align(scrn,
info->CurrentLayout.pixel_bytes, tiling_flags)) *
+ info->CurrentLayout.pixel_bytes;
height = RADEON_ALIGN(scrn->virtualY, drmmode_get_height_align(scrn,
tiling_flags));
/*
commit 0e432dff9e06a183acaeb20db29cbd03ff0f4b82
Author: Alex Deucher <alexdeuc...@gmail.com>
Date: Thu Jan 6 20:56:45 2011 -0500
NI: add pci ids
diff --git a/src/ati_pciids_gen.h b/src/ati_pciids_gen.h
index 80c60a8..5e5ced6 100644
--- a/src/ati_pciids_gen.h
+++ b/src/ati_pciids_gen.h
@@ -501,3 +501,39 @@
#define PCI_CHIP_CEDAR_68F8 0x68F8
#define PCI_CHIP_CEDAR_68F9 0x68F9
#define PCI_CHIP_CEDAR_68FE 0x68FE
+#define PCI_CHIP_BARTS_6720 0x6720
+#define PCI_CHIP_BARTS_6721 0x6721
+#define PCI_CHIP_BARTS_6722 0x6722
+#define PCI_CHIP_BARTS_6723 0x6723
+#define PCI_CHIP_BARTS_6724 0x6724
+#define PCI_CHIP_BARTS_6725 0x6725
+#define PCI_CHIP_BARTS_6726 0x6726
+#define PCI_CHIP_BARTS_6727 0x6727
+#define PCI_CHIP_BARTS_6728 0x6728
+#define PCI_CHIP_BARTS_6729 0x6729
+#define PCI_CHIP_BARTS_6738 0x6738
+#define PCI_CHIP_BARTS_6739 0x6739
+#define PCI_CHIP_TURKS_6740 0x6740
+#define PCI_CHIP_TURKS_6741 0x6741
+#define PCI_CHIP_TURKS_6742 0x6742
+#define PCI_CHIP_TURKS_6743 0x6743
+#define PCI_CHIP_TURKS_6744 0x6744
+#define PCI_CHIP_TURKS_6745 0x6745
+#define PCI_CHIP_TURKS_6746 0x6746
+#define PCI_CHIP_TURKS_6747 0x6747
+#define PCI_CHIP_TURKS_6748 0x6748
+#define PCI_CHIP_TURKS_6749 0x6749
+#define PCI_CHIP_TURKS_6750 0x6750
+#define PCI_CHIP_TURKS_6758 0x6758
+#define PCI_CHIP_TURKS_6759 0x6759
+#define PCI_CHIP_CAICOS_6760 0x6760
+#define PCI_CHIP_CAICOS_6761 0x6761
+#define PCI_CHIP_CAICOS_6762 0x6762
+#define PCI_CHIP_CAICOS_6763 0x6763
+#define PCI_CHIP_CAICOS_6764 0x6764
+#define PCI_CHIP_CAICOS_6765 0x6765
+#define PCI_CHIP_CAICOS_6766 0x6766
+#define PCI_CHIP_CAICOS_6767 0x6767
+#define PCI_CHIP_CAICOS_6768 0x6768
+#define PCI_CHIP_CAICOS_6770 0x6770
+#define PCI_CHIP_CAICOS_6779 0x6779
diff --git a/src/pcidb/ati_pciids.csv b/src/pcidb/ati_pciids.csv
index 060063b..61b04b9 100644
--- a/src/pcidb/ati_pciids.csv
+++ b/src/pcidb/ati_pciids.csv
@@ -502,3 +502,39 @@
"0x68F8","CEDAR_68F8","CEDAR",,,,,,"CEDAR"
"0x68F9","CEDAR_68F9","CEDAR",,,,,,"ATI Radeon HD 5450"
"0x68FE","CEDAR_68FE","CEDAR",,,,,,"CEDAR"
+"0x6720","BARTS_6720","BARTS",1,,,,,"AMD Radeon HD 6900M Series"
+"0x6721","BARTS_6721","BARTS",1,,,,,"Mobility Radeon HD 6000 Series"
+"0x6722","BARTS_6722","BARTS",,,,,,"BARTS"
+"0x6723","BARTS_6723","BARTS",,,,,,"BARTS"
+"0x6724","BARTS_6724","BARTS",1,,,,,"Mobility Radeon HD 6000 Series"
+"0x6725","BARTS_6725","BARTS",1,,,,,"Mobility Radeon HD 6000 Series"
+"0x6726","BARTS_6726","BARTS",,,,,,"BARTS"
+"0x6727","BARTS_6727","BARTS",,,,,,"BARTS"
+"0x6728","BARTS_6728","BARTS",,,,,,"BARTS"
+"0x6729","BARTS_6729","BARTS",,,,,,"BARTS"
+"0x6738","BARTS_6738","BARTS",,,,,,"AMD Radeon HD 6800 Series"
+"0x6739","BARTS_6739","BARTS",,,,,,"AMD Radeon HD 6800 Series"
+"0x6740","TURKS_6740","TURKS",1,,,,,"TURKS"
+"0x6741","TURKS_6741","TURKS",1,,,,,"TURKS"
+"0x6742","TURKS_6742","TURKS",1,,,,,"TURKS"
+"0x6743","TURKS_6743","TURKS",1,,,,,"TURKS"
+"0x6744","TURKS_6744","TURKS",1,,,,,"TURKS"
+"0x6745","TURKS_6745","TURKS",1,,,,,"TURKS"
+"0x6746","TURKS_6746","TURKS",,,,,,"TURKS"
+"0x6747","TURKS_6747","TURKS",,,,,,"TURKS"
+"0x6748","TURKS_6748","TURKS",,,,,,"TURKS"
+"0x6749","TURKS_6749","TURKS",,,,,,"TURKS"
+"0x6750","TURKS_6750","TURKS",,,,,,"TURKS"
+"0x6758","TURKS_6758","TURKS",,,,,,"TURKS"
+"0x6759","TURKS_6759","TURKS",,,,,,"TURKS"
+"0x6760","CAICOS_6760","CAICOS",1,,,,,"CAICOS"
+"0x6761","CAICOS_6761","CAICOS",1,,,,,"CAICOS"
+"0x6762","CAICOS_6762","CAICOS",,,,,,"CAICOS"
+"0x6763","CAICOS_6763","CAICOS",,,,,,"CAICOS"
+"0x6764","CAICOS_6764","CAICOS",1,,,,,"CAICOS"
+"0x6765","CAICOS_6765","CAICOS",1,,,,,"CAICOS"
+"0x6766","CAICOS_6766","CAICOS",,,,,,"CAICOS"
+"0x6767","CAICOS_6767","CAICOS",,,,,,"CAICOS"
+"0x6768","CAICOS_6768","CAICOS",,,,,,"CAICOS"
+"0x6770","CAICOS_6770","CAICOS",,,,,,"CAICOS"
+"0x6779","CAICOS_6779","CAICOS",,,,,,"CAICOS"
diff --git a/src/radeon_chipinfo_gen.h b/src/radeon_chipinfo_gen.h
index 42e0d5d..352fa99 100644
--- a/src/radeon_chipinfo_gen.h
+++ b/src/radeon_chipinfo_gen.h
@@ -421,4 +421,40 @@ static RADEONCardInfo RADEONCards[] = {
{ 0x68F8, CHIP_FAMILY_CEDAR, 0, 0, 0, 0, 0 },
{ 0x68F9, CHIP_FAMILY_CEDAR, 0, 0, 0, 0, 0 },
{ 0x68FE, CHIP_FAMILY_CEDAR, 0, 0, 0, 0, 0 },
+ { 0x6720, CHIP_FAMILY_BARTS, 1, 0, 0, 0, 0 },
+ { 0x6721, CHIP_FAMILY_BARTS, 1, 0, 0, 0, 0 },
+ { 0x6722, CHIP_FAMILY_BARTS, 0, 0, 0, 0, 0 },
+ { 0x6723, CHIP_FAMILY_BARTS, 0, 0, 0, 0, 0 },
+ { 0x6724, CHIP_FAMILY_BARTS, 1, 0, 0, 0, 0 },
+ { 0x6725, CHIP_FAMILY_BARTS, 1, 0, 0, 0, 0 },
+ { 0x6726, CHIP_FAMILY_BARTS, 0, 0, 0, 0, 0 },
+ { 0x6727, CHIP_FAMILY_BARTS, 0, 0, 0, 0, 0 },
+ { 0x6728, CHIP_FAMILY_BARTS, 0, 0, 0, 0, 0 },
+ { 0x6729, CHIP_FAMILY_BARTS, 0, 0, 0, 0, 0 },
+ { 0x6738, CHIP_FAMILY_BARTS, 0, 0, 0, 0, 0 },
+ { 0x6739, CHIP_FAMILY_BARTS, 0, 0, 0, 0, 0 },
+ { 0x6740, CHIP_FAMILY_TURKS, 1, 0, 0, 0, 0 },
+ { 0x6741, CHIP_FAMILY_TURKS, 1, 0, 0, 0, 0 },
+ { 0x6742, CHIP_FAMILY_TURKS, 1, 0, 0, 0, 0 },
+ { 0x6743, CHIP_FAMILY_TURKS, 1, 0, 0, 0, 0 },
+ { 0x6744, CHIP_FAMILY_TURKS, 1, 0, 0, 0, 0 },
+ { 0x6745, CHIP_FAMILY_TURKS, 1, 0, 0, 0, 0 },
+ { 0x6746, CHIP_FAMILY_TURKS, 0, 0, 0, 0, 0 },
+ { 0x6747, CHIP_FAMILY_TURKS, 0, 0, 0, 0, 0 },
+ { 0x6748, CHIP_FAMILY_TURKS, 0, 0, 0, 0, 0 },
+ { 0x6749, CHIP_FAMILY_TURKS, 0, 0, 0, 0, 0 },
+ { 0x6750, CHIP_FAMILY_TURKS, 0, 0, 0, 0, 0 },
+ { 0x6758, CHIP_FAMILY_TURKS, 0, 0, 0, 0, 0 },
+ { 0x6759, CHIP_FAMILY_TURKS, 0, 0, 0, 0, 0 },
+ { 0x6760, CHIP_FAMILY_CAICOS, 1, 0, 0, 0, 0 },
+ { 0x6761, CHIP_FAMILY_CAICOS, 1, 0, 0, 0, 0 },
+ { 0x6762, CHIP_FAMILY_CAICOS, 0, 0, 0, 0, 0 },
+ { 0x6763, CHIP_FAMILY_CAICOS, 0, 0, 0, 0, 0 },
+ { 0x6764, CHIP_FAMILY_CAICOS, 1, 0, 0, 0, 0 },
+ { 0x6765, CHIP_FAMILY_CAICOS, 1, 0, 0, 0, 0 },
+ { 0x6766, CHIP_FAMILY_CAICOS, 0, 0, 0, 0, 0 },
+ { 0x6767, CHIP_FAMILY_CAICOS, 0, 0, 0, 0, 0 },
+ { 0x6768, CHIP_FAMILY_CAICOS, 0, 0, 0, 0, 0 },
+ { 0x6770, CHIP_FAMILY_CAICOS, 0, 0, 0, 0, 0 },
+ { 0x6779, CHIP_FAMILY_CAICOS, 0, 0, 0, 0, 0 },
};
diff --git a/src/radeon_chipset_gen.h b/src/radeon_chipset_gen.h
index 7b7f795..66655e2 100644
--- a/src/radeon_chipset_gen.h
+++ b/src/radeon_chipset_gen.h
@@ -421,5 +421,41 @@ static SymTabRec RADEONChipsets[] = {
{ PCI_CHIP_CEDAR_68F8, "CEDAR" },
{ PCI_CHIP_CEDAR_68F9, "ATI Radeon HD 5450" },
{ PCI_CHIP_CEDAR_68FE, "CEDAR" },
+ { PCI_CHIP_BARTS_6720, "AMD Radeon HD 6900M Series" },
+ { PCI_CHIP_BARTS_6721, "Mobility Radeon HD 6000 Series" },
+ { PCI_CHIP_BARTS_6722, "BARTS" },
+ { PCI_CHIP_BARTS_6723, "BARTS" },
+ { PCI_CHIP_BARTS_6724, "Mobility Radeon HD 6000 Series" },
+ { PCI_CHIP_BARTS_6725, "Mobility Radeon HD 6000 Series" },
+ { PCI_CHIP_BARTS_6726, "BARTS" },
+ { PCI_CHIP_BARTS_6727, "BARTS" },
+ { PCI_CHIP_BARTS_6728, "BARTS" },
+ { PCI_CHIP_BARTS_6729, "BARTS" },
+ { PCI_CHIP_BARTS_6738, "AMD Radeon HD 6800 Series" },
+ { PCI_CHIP_BARTS_6739, "AMD Radeon HD 6800 Series" },
--
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