Bug#1032847: marked as done (unblock: intel-microcode/3.20230214.1)

[Debian Bug Tracking System]

Your message dated Thu, 16 Mar 2023 16:36:24 +0100
with message-id <19c1f9e1-a1c7-d285-aba0-2bcce31d3...@debian.org>
and subject line Re: Bug#1032847: unblock: intel-microcode/3.20230214.1
has caused the Debian Bug report #1032847,
regarding unblock: intel-microcode/3.20230214.1
to be marked as done.

This means that you claim that the problem has been dealt with.
If this is not the case it is now your responsibility to reopen the
Bug report if necessary, and/or fix the problem forthwith.

(NB: If you are a system administrator and have no idea what this
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-- 
1032847: https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=1032847
Debian Bug Tracking System
Contact ow...@bugs.debian.org with problems

--- Begin Message ---

Package: release.debian.org
Severity: normal
User: release.debian....@packages.debian.org
Usertags: unblock
X-Debbugs-Cc: intel-microc...@packages.debian.org, t...@security.debian.org
Control: affects -1 + src:intel-microcode

I've uploaded intel-microcode to DELAYED/5, ETA will be Mar 17 ~18:00 CET
Please unblock package intel-microcode once it hits unstable.

The upload updates intel microcodes to target (See #1031334)
       - INTEL-SA-00700: CVE-2022-21216
       - INTEL-SA-00730: CVE-2022-33972
       - INTEL-SA-00738: CVE-2022-33196
       - INTEL-SA-00767: CVE-2022-38090

the CVEs are information disclosure via local access vulnerbilities and
potential privilege escalations.

I plan to provide updated packages for bullseye (security team in CC).
As well as LTS (buster) and ELTS (stretch an jessie) as part of the freexian 
LTS/ELTS project)

To keep the fixes consistent, I'd like to let them flow from sid -> jessie…

[ Tests ]
I've tested that the package works on Intel hardware that I have access to.


[ Checklist ]
  [x] all changes are documented in the d/changelog
  [x] I reviewed all changes and I approve them
  [x] attach debdiff against the package in testing


unblock intel-microcode/3.20230214.1

-- 
tobi

diff -Nru intel-microcode-3.20221108.2/debian/changelog 
intel-microcode-3.20230214.1/debian/changelog
--- intel-microcode-3.20221108.2/debian/changelog       2023-02-17 
01:12:52.000000000 +0100
+++ intel-microcode-3.20230214.1/debian/changelog       2023-03-12 
18:16:50.000000000 +0100
@@ -1,3 +1,52 @@
+intel-microcode (3.20230214.1) unstable; urgency=medium
+
+  * Non-maintainer upload.
+  * New upstream microcode datafile 20230214
+    - Includes Fixes for: (Closes: #1031334)
+       - INTEL-SA-00700: CVE-2022-21216
+       - INTEL-SA-00730: CVE-2022-33972
+       - INTEL-SA-00738: CVE-2022-33196
+       - INTEL-SA-00767: CVE-2022-38090
+  * New Microcodes:
+    sig 0x000806f4, pf_mask 0x10, 2022-12-19, rev 0x2c000170
+    sig 0x000806f4, pf_mask 0x87, 2022-12-27, rev 0x2b000181
+    sig 0x000806f5, pf_mask 0x10, 2022-12-19, rev 0x2c000170
+    sig 0x000806f5, pf_mask 0x87, 2022-12-27, rev 0x2b000181
+    sig 0x000806f6, pf_mask 0x10, 2022-12-19, rev 0x2c000170
+    sig 0x000806f6, pf_mask 0x87, 2022-12-27, rev 0x2b000181
+    sig 0x000806f7, pf_mask 0x87, 2022-12-27, rev 0x2b000181
+    sig 0x000806f8, pf_mask 0x10, 2022-12-19, rev 0x2c000170
+    sig 0x000806f8, pf_mask 0x10, 2022-12-19, rev 0x2c000170, size 600064
+    sig 0x000806f8, pf_mask 0x87, 2022-12-27, rev 0x2b000181
+    sig 0x000806f8, pf_mask 0x87, 2022-12-27, rev 0x2b000181, size 561152
+    sig 0x000b06a2, pf_mask 0xc0, 2022-12-08, rev 0x410e
+    sig 0x000b06a2, pf_mask 0xc0, 2022-12-08, rev 0x410e, size 212992
+    sig 0x000b06a3, pf_mask 0xc0, 2022-12-08, rev 0x410e
+  * Updated Microcodes:
+    sig 0x00050653, pf_mask 0x97, 2022-08-30, rev 0x1000161, size 36864
+    sig 0x00050656, pf_mask 0xbf, 2022-08-26, rev 0x4003303, size 37888
+    sig 0x00050657, pf_mask 0xbf, 2022-08-26, rev 0x5003303, size 37888
+    sig 0x0005065b, pf_mask 0xbf, 2022-08-26, rev 0x7002503, size 29696
+    sig 0x000606a6, pf_mask 0x87, 2022-10-09, rev 0xd000389, size 296960
+    sig 0x000606c1, pf_mask 0x10, 2022-09-23, rev 0x1000211, size 289792
+    sig 0x000706a1, pf_mask 0x01, 2022-09-16, rev 0x003e, size 75776
+    sig 0x000706a8, pf_mask 0x01, 2022-09-20, rev 0x0022, size 76800
+    sig 0x000706e5, pf_mask 0x80, 2022-08-31, rev 0x00b8, size 113664
+    sig 0x000806a1, pf_mask 0x10, 2022-09-07, rev 0x0032, size 34816
+    sig 0x00090672, pf_mask 0x07, 2023-01-04, rev 0x002c
+    sig 0x00090672, pf_mask 0x07, 2023-01-04, rev 0x002c, size 219136
+    sig 0x00090675, pf_mask 0x07, 2023-01-04, rev 0x002c
+    sig 0x000906a3, pf_mask 0x80, 2023-01-11, rev 0x0429
+    sig 0x000906a3, pf_mask 0x80, 2023-01-11, rev 0x0429, size 218112
+    sig 0x000906a4, pf_mask 0x80, 2023-01-11, rev 0x0429
+    sig 0x000906c0, pf_mask 0x01, 2022-09-02, rev 0x24000024, size 20480
+    sig 0x000a0671, pf_mask 0x02, 2022-08-31, rev 0x0057, size 103424
+    sig 0x000b0671, pf_mask 0x32, 2022-12-19, rev 0x0112, size 207872
+    sig 0x000b06f2, pf_mask 0x07, 2023-01-04, rev 0x002c
+    sig 0x000b06f5, pf_mask 0x07, 2023-01-04, rev 0x002c
+
+ -- Tobias Frost <t...@debian.org>  Sun, 12 Mar 2023 18:16:50 +0100
+
 intel-microcode (3.20221108.2) unstable; urgency=medium
 
   * Move source and binary from non-free/admin to non-free-firmware/admin
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-1e-05 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-1e-05 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-25-02 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-25-02 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-25-05 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-25-05 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-26-01 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-26-01 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-2a-07 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-2a-07 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-2c-02 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-2c-02 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-2d-06 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-2d-06 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-2d-07 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-2d-07 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-2e-06 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-2e-06 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-2f-02 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-2f-02 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-37-08 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-37-08 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-37-09 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-37-09 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-3a-09 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-3a-09 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-3c-03 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-3c-03 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-3d-04 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-3d-04 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-3e-04 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-3e-04 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-3e-06 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-3e-06 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-3e-07 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-3e-07 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-3f-02 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-3f-02 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-3f-04 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-3f-04 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-45-01 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-45-01 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-46-01 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-46-01 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-47-01 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-47-01 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-4c-03 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-4c-03 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-4c-04 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-4c-04 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-4d-08 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-4d-08 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-4e-03 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-4e-03 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-55-03 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-55-03 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-55-04 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-55-04 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-55-05 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-55-05 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-55-06 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-55-06 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-55-07 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-55-07 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-55-0b and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-55-0b 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-56-02 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-56-02 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-56-03 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-56-03 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-56-04 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-56-04 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-56-05 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-56-05 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-5c-02 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-5c-02 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-5c-09 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-5c-09 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-5c-0a and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-5c-0a 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-5e-03 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-5e-03 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-5f-01 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-5f-01 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-66-03 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-66-03 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-6a-05 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-6a-05 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-6a-06 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-6a-06 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-6c-01 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-6c-01 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-7a-01 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-7a-01 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-7a-08 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-7a-08 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-7e-05 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-7e-05 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-8a-01 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-8a-01 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-8c-01 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-8c-01 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-8c-02 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-8c-02 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-8d-01 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-8d-01 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-8e-09 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-8e-09 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-8e-0a and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-8e-0a 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-8e-0b and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-8e-0b 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-8e-0c and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-8e-0c 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-96-01 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-96-01 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-97-02 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-97-02 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-97-05 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-97-05 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-9a-03 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-9a-03 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-9a-04 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-9a-04 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-9c-00 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-9c-00 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-9e-09 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-9e-09 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-9e-0a and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-9e-0a 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-9e-0b and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-9e-0b 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-9e-0c and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-9e-0c 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-9e-0d and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-9e-0d 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-a5-02 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-a5-02 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-a5-03 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-a5-03 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-a5-05 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-a5-05 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-a6-00 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-a6-00 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-a6-01 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-a6-01 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-a7-01 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-a7-01 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-b7-01 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-b7-01 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-bf-02 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-bf-02 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/06-bf-05 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/06-bf-05 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/0f-00-07 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/0f-00-07 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/0f-00-0a and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/0f-00-0a 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/0f-01-02 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/0f-01-02 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/0f-02-04 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/0f-02-04 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/0f-02-05 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/0f-02-05 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/0f-02-06 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/0f-02-06 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/0f-02-07 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/0f-02-07 
differ
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/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/microcode-20221108.d/0f-02-09 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/microcode-20221108.d/0f-02-09 
differ
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diff -Nru intel-microcode-3.20221108.2/releasenote.md 
intel-microcode-3.20230214.1/releasenote.md
--- intel-microcode-3.20221108.2/releasenote.md 2023-01-17 00:02:26.000000000 
+0100
+++ intel-microcode-3.20230214.1/releasenote.md 2023-03-10 18:45:19.000000000 
+0100
@@ -1,4 +1,50 @@
 # Release Notes
+## 
[microcode-20230214](https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/releases/tag/microcode-20230214)
+
+### Purpose
+
+- Security updates for 
[INTEL-SA-00767](https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00767.html)
+- Security updates for 
[INTEL-SA-00738](https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00738.html)
+- Security updates for 
[INTEL-SA-00700](https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00700.html)
+
+### New Platforms
+
+| Processor      | Stepping | F-M-S/PI    | Old Ver  | New Ver  | Products
+|:---------------|:---------|:------------|:---------|:---------|:---------
+| SPR-SP         | E2       | 06-8f-05/87 |          | 2b000181 | Xeon 
Scalable Gen4
+| SPR-SP         | E3       | 06-8f-06/87 |          | 2b000181 | Xeon 
Scalable Gen4
+| SPR-SP         | E4       | 06-8f-07/87 |          | 2b000181 | Xeon 
Scalable Gen4
+| SPR-SP         | E5       | 06-8f-08/87 |          | 2b000181 | Xeon 
Scalable Gen4
+| SPR-HBM        | B3       | 06-8f-08/10 |          | 2c000170 | Xeon Max
+| RPL-P 6+8      | J0       | 06-ba-02/07 |          | 0000410e | Core Gen13
+| RPL-H 6+8      | J0       | 06-ba-02/07 |          | 0000410e | Core Gen13
+| RPL-U 2+8      | Q0       | 06-ba-02/07 |          | 0000410e | Core Gen13
+
+### Updated Platforms
+
+| Processor      | Stepping | F-M-S/PI    | Old Ver  | New Ver  | Products
+|:---------------|:---------|:------------|:---------|:---------|:---------
+| ADL            | C0       | 06-97-02/07 | 00000026 | 0000002c | Core Gen12
+| ADL            | C0       | 06-97-05/07 | 00000026 | 0000002c | Core Gen12
+| ADL            | C0       | 06-bf-02/07 | 00000026 | 0000002c | Core Gen12
+| ADL            | C0       | 06-bf-05/07 | 00000026 | 0000002c | Core Gen12
+| ADL            | L0       | 06-9a-03/80 | 00000424 | 00000429 | Core Gen12
+| ADL            | L0       | 06-9a-04/80 | 00000424 | 00000429 | Core Gen12
+| CLX-SP         | B0       | 06-55-06/bf | 04003302 | 04003303 | Xeon 
Scalable Gen2
+| CLX-SP         | B1       | 06-55-07/bf | 05003302 | 05003303 | Xeon 
Scalable Gen2
+| CPX-SP         | A1       | 06-55-0b/bf | 07002501 | 07002503 | Xeon 
Scalable Gen3
+| GLK            | B0       | 06-7a-01/01 | 0000003c | 0000003e | Pentium 
Silver N/J5xxx, Celeron N/J4xxx
+| GLK-R          | R0       | 06-7a-08/01 | 00000020 | 00000022 | Pentium 
J5040/N5030, Celeron J4125/J4025/N4020/N4120
+| ICL-D          | B0       | 06-6c-01/10 | 01000201 | 01000211 | Xeon D-17xx, 
D-27xx
+| ICL-U/Y        | D1       | 06-7e-05/80 | 000000b6 | 000000b8 | Core Gen10 
Mobile
+| ICX-SP         | D0       | 06-6a-06/87 | 0d000375 | 0d000389 | Xeon 
Scalable Gen3
+| JSL            | A0/A1    | 06-9c-00/01 | 24000023 | 24000024 | Pentium 
N6000/N6005, Celeron N4500/N4505/N5100/N5105
+| LKF            | B2/B3    | 06-8a-01/10 | 00000031 | 00000032 | Core 
w/Hybrid Technology
+| RKL-S          | B0       | 06-a7-01/02 | 00000056 | 00000057 | Core Gen11
+| RPL-S          | S0       | 06-b7-01/32 | 0000010e | 00000112 | Core Gen13
+| SKX-SP         | B1       | 06-55-03/97 | 0100015e | 01000161 | Xeon Scalable
+
+# Release Notes
 ## 
[microcode-20221108](https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/releases/tag/microcode-20221108)
 
 ### Purpose
@@ -111,7 +157,7 @@
 
 | Processor      | Stepping | F-M-S/PI    | Old Ver  | New Ver  | Products
 |:---------------|:---------|:------------|:---------|:---------|:---------
-| VLV            | D0       | 06-37-09/0f | 0000090c | 0000090d | Atom E38xx
+| VLV            | D0       | 06-37-09/0F | 0000090c | 0000090d | Atom E38xx
 | SKL-U/Y        | D0       | 06-4e-03/c0 | 000000ec | 000000f0 | Core Gen6 
Mobile
 | SKX-SP         | B1       | 06-55-03/97 | 0100015c | 0100015d | Xeon Scalable
 | SKX-SP         | H0/M0/U0 | 06-55-04/b7 | 02006c0a | 02006d05 | Xeon Scalable
Binary files 
/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/supplementary-ucode-20221108_BDX-ML.bin
 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/supplementary-ucode-20221108_BDX-ML.bin
 differ
Binary files 
/tmp/qNbFv9J1ty/intel-microcode-3.20221108.2/supplementary-ucode-20230214_BDX-ML.bin
 and 
/tmp/Ekjb2KZejs/intel-microcode-3.20230214.1/supplementary-ucode-20230214_BDX-ML.bin
 differ

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Hi,

On 12-03-2023 18:56, Tobias Frost wrote:

unblock intel-microcode/3.20230214.1

unblocked and age to 10 days.

Paul

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