Hello! Some time ago, Antonio Messina posted a patch to 2.5-benh aimed to make the ibook/M3 external CRT work using benh's m3mirror utility (see [1]). His patch was based upon some previous patch to 2.4-benh [2].
Since I haven't quite understood how to use Antonio's patch (it looks like one needs to apply the 2.4 patch before applying his!), I put together my own (attached below). It's to be applied to 2.6.5-rc3-ben0 (current benh bitkeeper tree). Note that I'm not an aty128 hacker at all, I just put this patch together based on both the 2.4 patch and Antonio's patch. It works for me; but if it does not for you I probably won't be able to fix it. PS: please CC: me. [1] http://lists.debian.org/debian-powerpc/2003/12/msg00205.html [2] http://stampflee.com/kernel/aty128fb-m3fixes.diff -- Eric --- drivers/video/aty/aty128fb.c 2004-07-11 11:12:28.657131662 +0200 +++ drivers/video/aty/aty128fb.c.new 2004-07-11 11:12:05.318715166 +0200 @@ -395,6 +395,11 @@ struct aty128_crtc crtc; struct aty128_pll pll; struct aty128_ddafifo fifo_reg; +#ifdef CONFIG_PMAC_PBOOK + struct aty128_crtc crtc2; + struct aty128_pll pll2; + struct aty128_ddafifo fifo_reg2; +#endif u32 accel_flags; struct aty128_constants constants; /* PLL and others */ void *regbase; /* remapped mmio */ @@ -1036,6 +1041,23 @@ aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~(0x00030000)); } +/* Program the CRTC registers */ +static void +aty128_set_crtc2(const struct aty128_crtc *crtc, + const struct aty128fb_par *par) +{ + aty_st_le32(CRTC2_GEN_CNTL, crtc->gen_cntl); + + /* FIXME - Hardcoded */ + aty_st_le32(CRTC2_H_TOTAL_DISP, crtc->h_total & ~0xf | 0xa); + aty_st_le32(CRTC2_H_SYNC_STRT_WID, crtc->h_sync_strt_wid & ~0xff | 0x10); + + aty_st_le32(CRTC2_V_TOTAL_DISP, crtc->v_total); + aty_st_le32(CRTC2_V_SYNC_STRT_WID, crtc->v_sync_strt_wid); + aty_st_le32(CRTC2_PITCH, crtc->pitch); + aty_st_le32(CRTC2_OFFSET, crtc->offset); + aty_st_le32(CRTC2_OFFSET_CNTL, crtc->offset_cntl); +} static int aty128_var_to_crtc(const struct fb_var_screeninfo *var, struct aty128_crtc *crtc, @@ -1289,7 +1311,7 @@ { if (on) { aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) | CRT_CRTC_ON); - aty_st_le32(DAC_CNTL, (aty_ld_le32(DAC_CNTL) | DAC_PALETTE2_SNOOP_EN)); + aty_st_le32(DAC_CNTL, (aty_ld_le32(DAC_CNTL) | DAC_PALETTE2_SNOOP_EN | DAC_CLK_SEL)); } else aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) & ~CRT_CRTC_ON); } @@ -1359,6 +1381,41 @@ aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~PPLL_RESET); } +static void +aty128_set_pll2(struct aty128_pll *pll, const struct aty128fb_par *par) +{ + u32 div; + + unsigned char post_conv[] = /* register values for post dividers */ + { 2, 0, 1, 4, 2, 2, 6, 2, 3, 2, 2, 2, 7 }; + + /* reset PLL */ + aty_st_pll(P2PLL_CNTL, + aty_ld_pll(P2PLL_CNTL) | PPLL_RESET | PPLL_ATOMIC_UPDATE_EN); + + /* write the reference divider */ + aty_pll_wait_readupdate(par); + aty_st_pll(P2PLL_REF_DIV, par->constants.ref_divider & 0x3ff); + aty_pll_writeupdate(par); + + div = aty_ld_pll(P2PLL_DIV_0); + div &= ~XPLL_FB_DIV_MASK; + div |= pll->feedback_divider; + div |= post_conv[pll->post_divider] << 16; + div |= 0x00040000; /* magic value */ + + /* write feedback and post dividers */ + aty_pll_wait_readupdate(par); + aty_st_pll(P2PLL_DIV_0, div); + aty_pll_writeupdate(par); + + aty_pll_wait_readupdate(par); + aty_st_pll(HTOTAL_CNTL, 0); /* no horiz crtc adjustment */ + aty_pll_writeupdate(par); + + /* clear the reset, just in case */ + aty_st_pll(P2PLL_CNTL, aty_ld_pll(P2PLL_CNTL) & ~PPLL_RESET); +} static int aty128_var_to_pll(u32 period_in_ps, struct aty128_pll *pll, const struct aty128fb_par *par) @@ -1417,6 +1474,15 @@ aty_st_le32(DDA_ON_OFF, dsp->dda_on_off); } +static void +aty128_set_fifo2(const struct aty128_ddafifo *dsp, + const struct aty128fb_par *par) +{ + /* FIXME - Hardcoded */ + aty_st_le32(DDA2_CONFIG, 0x010502aa); + aty_st_le32(DDA2_ON_OFF, 0x11805a74); +} + static int aty128_ddafifo(struct aty128_ddafifo *dsp, const struct aty128_pll *pll, @@ -1510,6 +1576,14 @@ aty128_set_pll(&par->pll, par); aty128_set_fifo(&par->fifo_reg, par); +#ifdef CONFIG_PMAC_PBOOK + if(par->chip_gen == rage_M3) { + aty128_set_crtc2(&par->crtc2, par); + aty128_set_pll2(&par->pll2, par); + aty128_set_fifo2(&par->fifo_reg2, par); + } +#endif + config = aty_ld_le32(CONFIG_CNTL) & ~3; #if defined(__BIG_ENDIAN) @@ -1556,6 +1630,11 @@ struct aty128_crtc crtc; struct aty128_pll pll; struct aty128_ddafifo fifo_reg; +#if CONFIG_PMAC_PBOOK + struct aty128_crtc crtc2; + struct aty128_pll pll2; + struct aty128_ddafifo fifo_reg2; +#endif if ((err = aty128_var_to_crtc(var, &crtc, par))) return err; @@ -1566,9 +1645,27 @@ if ((err = aty128_ddafifo(&fifo_reg, &pll, crtc.depth, par))) return err; +#ifdef CONFIG_PMAC_PBOOK + if ((err = aty128_var_to_crtc(var, &crtc2, par))) + return err; + + if ((err = aty128_var_to_pll(var->pixclock, &pll2, par))) + return err; + + if ((err = aty128_ddafifo(&fifo_reg2, &pll2, crtc2.depth, par))) + return err; +#endif + par->crtc = crtc; par->pll = pll; par->fifo_reg = fifo_reg; + +#ifdef CONFIG_PMAC_PBOOK + par->crtc2 = crtc2; + par->pll2 = pll2; + par->fifo_reg2 = fifo_reg2; +#endif + par->accel_flags = var->accel_flags; return 0; @@ -1650,7 +1747,7 @@ struct aty128fb_par *par) { if (par->chip_gen == rage_M3) { -#if 0 +#ifdef CONFIG_PMAC_PBOOK /* Note: For now, on M3, we set palette on both heads, which may * be useless. Can someone with a M3 check this ? *
