On Tue, 2003-07-15 at 16:29, Benjamin Herrenschmidt wrote:
> > > >>> latest CVS build (by myself) as of yesterday (4.3.99...)
> > > >>
>
> When did you try exactly ? I've seen more fixes for TMDS getting
> in the CVS recently. I'm not sure what's up here, definitely not
> something the doc explains. I suspect it's the path of pixel
> data from the framebuffer to the TMDS transmitter that has an
> endian problem, I fail to see why SURFACE_CNTL thing would fail,
> or maybe it's a problem related to surface translation getting in
> our way ?
I suspected that as well. If current CVS still doesn't work (works
perfectly here with an external CRT on an M9 in a TiBook IV), please try
this patch and post the RADEONInitCommonRegisters output.
Or maybe it's something like http://bugs.xfree86.org/show_bug.cgi?id=521
?
--
Earthling Michel Dänzer \ Debian (powerpc), XFree86 and DRI developer
Software libre enthusiast \ http://svcs.affero.net/rm.php?r=daenzer
Index: programs/Xserver/hw/xfree86/drivers/ati/radeon_driver.c
===================================================================
RCS file: /home/x-cvs/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_driver.c,v
retrieving revision 1.103
diff -p -u -r1.103 radeon_driver.c
--- programs/Xserver/hw/xfree86/drivers/ati/radeon_driver.c 24 Jul 2003 13:50:23 -0000 1.103
+++ programs/Xserver/hw/xfree86/drivers/ati/radeon_driver.c 26 Jul 2003 11:02:28 -0000
@@ -5341,8 +5341,10 @@ static void RADEONRestore(ScrnInfoPtr pS
}
/* Define common registers for requested video mode */
-static void RADEONInitCommonRegisters(RADEONSavePtr save, RADEONInfoPtr info)
+static void RADEONInitCommonRegisters(ScrnInfoPtr pScrn, RADEONSavePtr save)
{
+ RADEONInfoPtr info = RADEONPTR(pScrn);
+
save->ovr_clr = 0;
save->ovr_wid_left_right = 0;
save->ovr_wid_top_bottom = 0;
@@ -5360,6 +5362,49 @@ static void RADEONInitCommonRegisters(RA
*/
if (save->bus_cntl & (RADEON_BUS_READ_BURST))
save->bus_cntl |= RADEON_BUS_RD_DISCARD_EN;
+
+ save->surface_cntl = 0;
+
+#if X_BYTE_ORDER == X_BIG_ENDIAN
+ switch (pScrn->bitsPerPixel) {
+ case 16:
+ save->surface_cntl |= RADEON_NONSURF_AP0_SWP_16BPP | RADEON_NONSURF_AP1_SWP_16BPP;
+ break;
+
+ case 32:
+ save->surface_cntl |= RADEON_NONSURF_AP0_SWP_32BPP | RADEON_NONSURF_AP1_SWP_32BPP;
+ break;
+ }
+
+ {
+ unsigned char *RADEONMMIO = info->MMIO;
+
+ ErrorF("%s: Surface 0: info=0x%x, range=0x%x-0x%x\n", __FUNCTION__,
+ INREG(RADEON_SURFACE0_INFO), INREG(RADEON_SURFACE0_LOWER_BOUND),
+ INREG(RADEON_SURFACE0_UPPER_BOUND));
+ ErrorF("%s: Surface 1: info=0x%x, range=0x%x-0x%x\n", __FUNCTION__,
+ INREG(RADEON_SURFACE1_INFO), INREG(RADEON_SURFACE1_LOWER_BOUND),
+ INREG(RADEON_SURFACE1_UPPER_BOUND));
+ ErrorF("%s: Surface 2: info=0x%x, range=0x%x-0x%x\n", __FUNCTION__,
+ INREG(RADEON_SURFACE2_INFO), INREG(RADEON_SURFACE2_LOWER_BOUND),
+ INREG(RADEON_SURFACE2_UPPER_BOUND));
+ ErrorF("%s: Surface 3: info=0x%x, range=0x%x-0x%x\n", __FUNCTION__,
+ INREG(RADEON_SURFACE3_INFO), INREG(RADEON_SURFACE3_LOWER_BOUND),
+ INREG(RADEON_SURFACE3_UPPER_BOUND));
+ ErrorF("%s: Surface 4: info=0x%x, range=0x%x-0x%x\n", __FUNCTION__,
+ INREG(RADEON_SURFACE4_INFO), INREG(RADEON_SURFACE4_LOWER_BOUND),
+ INREG(RADEON_SURFACE4_UPPER_BOUND));
+ ErrorF("%s: Surface 5: info=0x%x, range=0x%x-0x%x\n", __FUNCTION__,
+ INREG(RADEON_SURFACE5_INFO), INREG(RADEON_SURFACE5_LOWER_BOUND),
+ INREG(RADEON_SURFACE5_UPPER_BOUND));
+ ErrorF("%s: Surface 6: info=0x%x, range=0x%x-0x%x\n", __FUNCTION__,
+ INREG(RADEON_SURFACE6_INFO), INREG(RADEON_SURFACE6_LOWER_BOUND),
+ INREG(RADEON_SURFACE6_UPPER_BOUND));
+ ErrorF("%s: Surface 7: info=0x%x, range=0x%x-0x%x\n", __FUNCTION__,
+ INREG(RADEON_SURFACE7_INFO), INREG(RADEON_SURFACE7_LOWER_BOUND),
+ INREG(RADEON_SURFACE7_UPPER_BOUND));
+ }
+#endif
}
/* Define CRTC registers for requested video mode */
@@ -5487,22 +5532,9 @@ static Bool RADEONInitCrtcRegisters(Scrn
(pScrn->bitsPerPixel * 8));
save->crtc_pitch |= save->crtc_pitch << 16;
- save->surface_cntl = 0;
save->disp_merge_cntl = info->SavedReg.disp_merge_cntl;
save->disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
-#if X_BYTE_ORDER == X_BIG_ENDIAN
- switch (pScrn->bitsPerPixel) {
- case 16:
- save->surface_cntl |= RADEON_NONSURF_AP0_SWP_16BPP;
- break;
-
- case 32:
- save->surface_cntl |= RADEON_NONSURF_AP0_SWP_32BPP;
- break;
- }
-#endif
-
RADEONTRACE(("Pitch = %d bytes (virtualX = %d, displayWidth = %d)\n",
save->crtc_pitch, pScrn->virtualX,
info->CurrentLayout.displayWidth));
@@ -6066,12 +6098,13 @@ static Bool RADEONInit(ScrnInfoPtr pScrn
info->Flags = mode->Flags;
+ RADEONInitCommonRegisters(pScrn, save);
+
if (info->IsSecondary) {
if (!RADEONInitCrtc2Registers(pScrn, save, mode, info))
return FALSE;
RADEONInitPLL2Registers(save, &info->pll, dot_clock);
} else {
- RADEONInitCommonRegisters(save, info);
if (!RADEONInitCrtcRegisters(pScrn, save, mode, info))
return FALSE;
dot_clock = mode->Clock/1000.0;
Index: programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h
===================================================================
RCS file: /home/x-cvs/xc/programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h,v
retrieving revision 1.28
diff -p -u -r1.28 radeon_reg.h
--- programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h 2 Jul 2003 17:31:30 -0000 1.28
+++ programs/Xserver/hw/xfree86/drivers/ati/radeon_reg.h 26 Jul 2003 11:02:29 -0000
@@ -1031,6 +1031,8 @@
# define RADEON_SURF_TRANSLATION_DIS (1 << 8)
# define RADEON_NONSURF_AP0_SWP_16BPP (1 << 20)
# define RADEON_NONSURF_AP0_SWP_32BPP (1 << 21)
+# define RADEON_NONSURF_AP1_SWP_16BPP (1 << 22)
+# define RADEON_NONSURF_AP1_SWP_32BPP (1 << 23)
#define RADEON_SURFACE0_INFO 0x0b0c
#define RADEON_SURFACE0_LOWER_BOUND 0x0b04
#define RADEON_SURFACE0_UPPER_BOUND 0x0b08
