On Wed, Jul 03, 2002 at 04:58:17PM -0700, Tom Rini wrote:
> On Wed, Jul 03, 2002 at 09:02:32PM +0200, Olaf Hering wrote:
>
> > On Mon, Jul 01, Tom Rini wrote:
> >
> > > Lemme know if you still have the correct ammount of memory reported
> > > still. Thanks.
> >
> > ocan you provide a new patch for _devel? I used that one and it doesnt
> > compile
>
> D'oh. I forgot to add <asm/bootinfo.h> to prep_setup.c. New patches
> attached.
D'oh again. Attached are the missing files. I hate regenerating
patches :)
--
Tom Rini (TR1265)
http://gate.crashing.org/~trini/
/*
* arch/ppc/boot/common/mpc10x_common.c
*
* A routine to find out how much memory the machine has.
*
* Based on:
* arch/ppc/kernel/mpc10x_common.c
*
* Author: Mark A. Greer
* [EMAIL PROTECTED]
*
* Copyright 2001-2002 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/pci.h>
#include <asm/types.h>
#include <asm/io.h>
#include "mpc10x.h"
/*
* *** WARNING - A BAT MUST be set to access the PCI config addr/data regs ***
*/
/*
* PCI config space macros, similar to indirect_xxx and early_xxx macros.
* We assume bus 0.
*/
#define MPC10X_CFG_read(val, addr, type, op) *val = op((type)(addr))
#define MPC10X_CFG_write(val, addr, type, op) op((type *)(addr), (val))
#define MPC10X_PCI_OP(rw, size, type, op, mask) \
static void \
mpc10x_##rw##_config_##size(unsigned int *cfg_addr, \
unsigned int *cfg_data, int devfn, int offset, \
type val) \
{ \
out_be32(cfg_addr, \
((offset & 0xfc) << 24) | (devfn << 16) \
| (0 << 8) | 0x80); \
MPC10X_CFG_##rw(val, cfg_data + (offset & mask), type, op); \
return; \
}
MPC10X_PCI_OP(read, byte, u8 *, in_8, 3)
MPC10X_PCI_OP(read, dword, u32 *, in_le32, 0)
/*
* Read the memory controller registers to determine the amount of memory in
* the system. This assumes that the firmware has correctly set up the memory
* controller registers.
*/
unsigned long
mpc10x_get_mem_size(unsigned int mem_map)
{
unsigned int *config_addr, *config_data, val;
unsigned long start, end, total, offset;
int i;
unsigned char bank_enables;
switch (mem_map) {
case MPC10X_MEM_MAP_A:
config_addr = (unsigned int *)MPC10X_MAPA_CNFG_ADDR;
config_data = (unsigned int *)MPC10X_MAPA_CNFG_DATA;
break;
case MPC10X_MEM_MAP_B:
config_addr = (unsigned int *)MPC10X_MAPB_CNFG_ADDR;
config_data = (unsigned int *)MPC10X_MAPB_CNFG_DATA;
break;
default:
return 0;
}
mpc10x_read_config_byte(config_addr, config_data, PCI_DEVFN(0,0),
MPC10X_MCTLR_MEM_BANK_ENABLES, &bank_enables);
total = 0;
for (i = 0; i < 8; i++) {
if (bank_enables & (1 << i)) {
offset = MPC10X_MCTLR_MEM_START_1 + ((i > 3) ? 4 : 0);
mpc10x_read_config_dword(config_addr, config_data,
PCI_DEVFN(0,0), offset, &val);
start = (val >> ((i & 3) << 3)) & 0xff;
offset = MPC10X_MCTLR_EXT_MEM_START_1 + ((i>3) ? 4 : 0);
mpc10x_read_config_dword(config_addr, config_data,
PCI_DEVFN(0,0), offset, &val);
val = (val >> ((i & 3) << 3)) & 0x03;
start = (val << 28) | (start << 20);
offset = MPC10X_MCTLR_MEM_END_1 + ((i > 3) ? 4 : 0);
mpc10x_read_config_dword(config_addr, config_data,
PCI_DEVFN(0,0), offset, &val);
end = (val >> ((i & 3) << 3)) & 0xff;
offset = MPC10X_MCTLR_EXT_MEM_END_1 + ((i > 3) ? 4 : 0);
mpc10x_read_config_dword(config_addr, config_data,
PCI_DEVFN(0,0), offset, &val);
val = (val >> ((i & 3) << 3)) & 0x03;
end = (val << 28) | (end << 20) | 0xfffff;
total += (end - start + 1);
}
}
return total;
}
/*
* arch/ppc/boot/include/mpc10.h
*
* Common defines for the Motorola SPS MPC106/8240/107 Host bridge/Mem
* ctrl/EPIC/etc.
*
* Author: Tom Rini <[EMAIL PROTECTED]>
*
* This is a heavily stripped down version of:
* include/asm-ppc/mpc10x.h
*
* Author: Mark A. Greer
* [EMAIL PROTECTED]
*
* Copyright 2001-2002 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __BOOT_MPC10X_H__
#define __BOOT_MPC10X_H__
/*
* The values here don't completely map everything but should work in most
* cases.
*
* MAP A (PReP Map)
* Processor: 0x80000000 - 0x807fffff -> PCI I/O: 0x00000000 - 0x007fffff
* Processor: 0xc0000000 - 0xdfffffff -> PCI MEM: 0x00000000 - 0x1fffffff
* PCI MEM: 0x80000000 -> Processor System Memory: 0x00000000
* EUMB mapped to: ioremap_base - 0x00100000 (ioremap_base - 1 MB)
*
* MAP B (CHRP Map)
* Processor: 0xfe000000 - 0xfebfffff -> PCI I/O: 0x00000000 - 0x00bfffff
* Processor: 0x80000000 - 0xbfffffff -> PCI MEM: 0x80000000 - 0xbfffffff
* PCI MEM: 0x00000000 -> Processor System Memory: 0x00000000
* EUMB mapped to: ioremap_base - 0x00100000 (ioremap_base - 1 MB)
*/
/* Define the type of map to use */
#define MPC10X_MEM_MAP_A 1
#define MPC10X_MEM_MAP_B 2
/* Map A (PReP Map) Defines */
#define MPC10X_MAPA_CNFG_ADDR 0x80000cf8
#define MPC10X_MAPA_CNFG_DATA 0x80000cfc
/* Map B (CHRP Map) Defines */
#define MPC10X_MAPB_CNFG_ADDR 0xfec00000
#define MPC10X_MAPB_CNFG_DATA 0xfee00000
/* Define offsets for the memory controller registers in the config space */
#define MPC10X_MCTLR_MEM_START_1 0x80 /* Banks 0-3 */
#define MPC10X_MCTLR_MEM_START_2 0x84 /* Banks 4-7 */
#define MPC10X_MCTLR_EXT_MEM_START_1 0x88 /* Banks 0-3 */
#define MPC10X_MCTLR_EXT_MEM_START_2 0x8c /* Banks 4-7 */
#define MPC10X_MCTLR_MEM_END_1 0x90 /* Banks 0-3 */
#define MPC10X_MCTLR_MEM_END_2i 0x94 /* Banks 4-7 */
#define MPC10X_MCTLR_EXT_MEM_END_1 0x98 /* Banks 0-3 */
#define MPC10X_MCTLR_EXT_MEM_END_2 0x9c /* Banks 4-7 */
#define MPC10X_MCTLR_MEM_BANK_ENABLES 0xa0
#endif /* __BOOT_MPC10X_H__ */
