Michel Lanners writes:
> On 22 May, this message from Albert D. Cahalan echoed through cyberspace:
>> Michel Lanners writes:
>>> On 22 May, this message from Albert D. Cahalan echoed through cyberspace:
>>>> =?iso-8859-1?Q?Rog writes:
>>> And don't forget the loop counter and some increment...
>>> Or code it with a decrement operator and copy backwards?
>>
>> I didn't forget; look again. This is PowerPC. :-)
>> Here's the assembly with C code:
>>
>> dcbt eight,src // prefetch the cache line with src[1]...src[4]
>> loop_top: do{
>> dcba eight,dst // allocate a cache line for dst[1]...dst[4]
>> lfd f11,8,(src) double_1 = src[1];
>> lfd f12,16,(src) double_2 = src[2];
>> lfd f13,24,(src) double_3 = src[3];
>> lfdu f14,32,(src) double_4 = src[4]; src += 4;
>> dcbi r0,src // would like to discard the src[-3]...src[0]
>> dcbt eight,src // prefetch the cache line with src[1]...src[4]
>> stfd f11,8,(dst) src[1] = double_1;
>> stfd f12,16,(dst) src[2] = double_2;
>> stfd f13,24,(dst) src[3] = double_3;
>> stfdu f14,32,(dst) dst[4] = double_4; dst += 4;
>> dcbf r0,dst // write back dst[-3]...dst[0] if needed, then
>> invalidate it
>> bdnz loop_top }while(--ctr);
>
> OK, but then you're not showing initialization of ctr, are you?
That's right.
srwi rX,rX,5 n /= 32; // select rX to be a caller-save in register
mtctr rX ctr = n; // ctr is a special-purpose register
"mtctr rD" is short for "mtspr 9,rD". As is usual for Motorola,
you won't find this in the index or in the instruction listing.
Look in appendix F, section F.8, page F-21 of "The Programming
Environments for 32-bit Microprocessors". The same goes for the
"srwi rX,rX,5" which is "rlwinm rX,rX,27,5,31"; see F.4 page F-5.
Reminder: Motorola even numbers the bits backwards. Bit 0 is
most significant.
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