I suspect that this issue might be caused by a lack of MIPS memory
barriers in cacao.
The following code is in cacao-0.99.4/src/vm/jit/mips/md-atomic.hpp:
/**
* A memory
barrier.
*/
inline static void Atomic_memory_barrier(void)
{
__asm__ __volatile__ ("" : : : "memory");
}
#define STORE_ORDER_BARRIER() __asm__ __volatile__ ("" : : : "memory");
#define MEMORY_BARRIER_AFTER_ATOMIC() __asm__ __volatile__ ("" : : :
"memory");
The Cavium Octeon chip I am using has weak memory ordering -- The "sync"
instruction
is required for memory barriers. I am going to attempt a rebuild with
this in place and see
if that fixes this problem.
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