On Tue, 2025-03-18 at 16:59 +0100, Daniel Gröber wrote: > Actually we really ought to look into doing some more un-vendoring in yosys > in general.
It looks like at least in yosys they apply their own patches so it might not be that easy. Some progress on making 32-bit work again. I've managed to figure out the iverilog out of memory problem. This ancient iverilog issue: https://github.com/steveicarus/iverilog/issues/60 Refers to this commit: https://github.com/YosysHQ/yosys/commit/95944eb69e45837516ff9c0cba54f77ab89af754 which fixed up $mem for the same issue. At some point $print got added and it needs the same fix. See attached patch. That only leaves the cxxrtl tests failing. I don't think fixing them will be as straightforward. Cheers, Scott
--- techlibs/common/simlib.v 2025-03-18 10:41:02.865922396 +0000 +++ /home/scott/simlib.v 2025-03-18 19:07:40.217912869 +0000 @@ -2110,10 +2110,10 @@ parameter PRIORITY = 0; parameter FORMAT = ""; -parameter ARGS_WIDTH = 0; +parameter signed ARGS_WIDTH = 0; parameter TRG_ENABLE = 1; -parameter TRG_WIDTH = 0; +parameter signed TRG_WIDTH = 0; parameter TRG_POLARITY = 0; input EN;
