Bug#295935: verilog: Assertion failure in eval_expr.c:269

[Keith Dunwoody]

Package: verilog
Version: 0.8-1
Severity: normal


When compiling the verilog code given below, iverilog asserts with the 
error: ivl: eval_expr.c:269: draw_binary_expr_eq: Assertion 
`ivl_expr_value(re) == IVL_VT_VECTOR' failed.

I appologize for the excessively long example case.

-- BEGIN FILE --

// Module for 62256 32Kx8 SRAM

module sram(A, IO, _WE, _OE, _CS);
   parameter size = 16'h8000;
      
   input [14:0] A;
   inout [7:0]  IO;
   input        _WE, _OE, _CS;
   
   reg [7:0]    mem [0:size-1];

   initial begin: initialize
      $readmemb("init.ram", mem);
   end

   // control output state
   assign IO = (!_CS && !_OE) ? mem[A] : 8'bz;
      
   always @(_OE or _CS or _WE) begin: write
     if (_OE && !_CS && !_WE)
       mem[A] = IO;
   end

   always @(_WE or _OE)
     if (!_WE && !_OE)
       $display("Operational error in ram chi; OE and WE both active");
         
endmodule // sram


module test;
   reg [14:0] address;
   wire [7:0] data;
   reg        _WE, _OE, _CS;
   
   reg        drive_data;
   reg [7:0]  data_buf;

   reg [7:0]  real_val [16'h7FFF:0];
   reg [7:0]  out_data;

   sram test_mem(address, data, _WE, _OE, _CS);
   
   assign     data = (drive_data ? data_buf : 8'bz);

   initial begin: test
      _CS = 1;
      address = 0;
      _WE = 1;
      _OE = 1;
      drive_data = 0;

      $readmemb("init.ram", test_mem);
            
      $display("Checking for high-impedence when deselected...");
      #1;
      if (data !== 8'bz) begin
         $display("FAILED");
         $stop;
      end
      
              
      $display("Checking initial data...");
      _WE = 1;
      address = 0;
      #1 _CS = 0;
      #1 out_data = data;
      if (out_data != test_mem[0]) begin
         $display("FAILED at address 0x%x", address);
         $stop;
      end
      
      for (address = 1; address != 0; address = address+1) begin
         #1 out_data = data;
         if (out_data != test_mem[0]) begin
            $display("FAILED at address 0x%x", address);
            $stop;
         end
         #1;
      end

      $stop;
   end // block: test
endmodule // test

-- END FILE --

-- System Information:
Debian Release: 3.1
  APT prefers testing
  APT policy: (500, 'testing')
Architecture: i386 (i686)
Kernel: Linux 2.6.8-2-k7
Locale: LANG=C, LC_CTYPE=C (charmap=ANSI_X3.4-1968)

Versions of packages verilog depends on:
ii  libbz2-1.0                  1.0.2-1      A high-quality block-sorting file 
ii  libc6                       2.3.2.ds1-20 GNU C Library: Shared libraries an
ii  libgcc1                     1:3.4.3-6    GCC support library
ii  libncurses5                 5.4-4        Shared libraries for terminal hand
ii  libreadline4                4.3-11       GNU readline and history libraries
ii  libstdc++5                  1:3.3.5-5    The GNU Standard C++ Library v3
ii  zlib1g                      1:1.2.2-3    compression library - runtime

-- no debconf information


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