Package: gnucap
Version: 1:0.36~20091207-2+b1
Severity: normal
Dear Maintainer,
*** Reporter, please consider answering these questions, where appropriate ***
* What led up to the situation?
Run the program with a .net file generated by the "gnetlist" correctly program
and execute the program seems not to understand the list and ignores leaving
the program without option to simulate.
* What exactly did you do (or not do) that was effective (or
ineffective)?
The program must show either the listing file to run the "list" command and of
course continue simualción after running the "print op ..." and "op" commands.
But it does not get to that part, because it does not load the list.
* What was the outcome of this action?
This is my output:
miguel@debian:~/electronica/gedaesquemas$ gnucap resistencias.net
Gnucap 2009.12.07 RCS 26.136
The Gnu Circuit Analysis Package
Never trust any version less than 1.0
Copyright 1982-2009, Albert Davis
Gnucap comes with ABSOLUTELY NO WARRANTY
This is free software, and you are welcome
to redistribute it under the terms of
the GNU General Public License, version 3 or later.
See the file "COPYING" for details.
V1 1 0 DC 10V
^ ? what's this?
R7 4 0 10
^ ? what's this?
R6 5 0 2300
^ ? what's this?
R5 5 3 750
^ ? what's this?
R3 4 2 230
^ ? what's this?
R4 0 3 3000
^ ? what's this?
R2 3 2 2000
^ ? what's this?
R1 2 1 1000
^ ? what's this?
..end
^ ? what's this?
* What outcome did you expect instead?
something equal to .net file
*** End of the template - remove these template lines ***
-- System Information:
Debian Release: stretch/sid
APT prefers unstable
APT policy: (500, 'unstable')
Architecture: amd64 (x86_64)
Kernel: Linux 4.2.0-1-amd64 (SMP w/4 CPU cores)
Locale: LANG=es_ES.UTF-8, LC_CTYPE=es_ES.UTF-8 (charmap=UTF-8)
Shell: /bin/sh linked to /bin/dash
Init: systemd (via /run/systemd/system)
Versions of packages gnucap depends on:
ii libc6 2.19-22
ii libgcc1 1:5.2.1-22
ii libreadline6 6.3-8+b3
ii libstdc++6 5.2.1-22
gnucap recommends no packages.
gnucap suggests no packages.
-- no debconf information
miguel@debian:~/electronica/gedaesquemas$ cat resistencias.net
* gnetlist -g spice-sdb -o resistencias.net resistencias.sch
*********************************************************
* Spice file generated by gnetlist *
* spice-sdb version 4.28.2007 by SDB -- *
* provides advanced spice netlisting capability. *
* Documentation at http://www.brorson.com/gEDA/SPICE/ *
*********************************************************
*============== Begin SPICE netlist of main design ============
V1 1 0 DC 10V
R7 4 0 10
R6 5 0 2300
R5 5 3 750
R3 4 2 230
R4 0 3 3000
R2 3 2 2000
R1 2 1 1000
..end
miguel@debian:~/electronica/gedaesquemas$
miguel@debian:~/electronica/gedaesquemas$ gnucap resistencias.net
Gnucap 2009.12.07 RCS 26.136
The Gnu Circuit Analysis Package
Never trust any version less than 1.0
Copyright 1982-2009, Albert Davis
Gnucap comes with ABSOLUTELY NO WARRANTY
This is free software, and you are welcome
to redistribute it under the terms of
the GNU General Public License, version 3 or later.
See the file "COPYING" for details.
V1 1 0 DC 10V
^ ? what's this?
R7 4 0 10
^ ? what's this?
R6 5 0 2300
^ ? what's this?
R5 5 3 750
^ ? what's this?
R3 4 2 230
^ ? what's this?
R4 0 3 3000
^ ? what's this?
R2 3 2 2000
^ ? what's this?
R1 2 1 1000
^ ? what's this?
..end
^ ? what's this?
gnucap> list
gnucap> print
tran
ac
dc
op
fourier
gnucap> print op v(1) v(2) v(3) v(4) v(5)
print op v(1) v(2) v(3) v(4) v(5)
^ ? no match
print op v(1) v(2) v(3) v(4) v(5)
^ ? no match
print op v(1) v(2) v(3) v(4) v(5)
^ ? no match
print op v(1) v(2) v(3) v(4) v(5)
^ ? no match
print op v(1) v(2) v(3) v(4) v(5)
^ ? no match
gnucap> quit
miguel@debian:~/electronica/gedaesquemas$
v 20130925 2
C 40000 40000 0 0 0 title-B.sym
C 44000 47700 1 90 0 resistor-1.sym
{
T 43600 48000 5 10 0 0 90 0 1
device=RESISTOR
T 43700 47900 5 10 1 1 90 0 1
refdes=R1
T 44000 47700 5 8 1 1 0 0 1
value=1000
}
C 44000 46000 1 90 0 resistor-1.sym
{
T 43600 46300 5 10 0 0 90 0 1
device=RESISTOR
T 43700 46200 5 10 1 1 90 0 1
refdes=R2
T 44000 46000 5 8 1 1 0 0 1
value=2000
}
C 44000 44300 1 90 0 resistor-1.sym
{
T 43600 44600 5 10 0 0 90 0 1
device=RESISTOR
T 43700 44500 5 10 1 1 90 0 1
refdes=R4
T 44000 44300 5 8 1 1 0 0 1
value=3000
}
C 45600 47300 1 180 0 resistor-1.sym
{
T 45300 46900 5 10 0 0 180 0 1
device=RESISTOR
T 45400 47000 5 10 1 1 180 0 1
refdes=R3
T 45600 47300 5 8 1 1 0 0 1
value=230
}
C 45600 45600 1 180 0 resistor-1.sym
{
T 45300 45200 5 10 0 0 180 0 1
device=RESISTOR
T 45400 45300 5 10 1 1 180 0 1
refdes=R5
T 45600 45600 5 8 1 1 0 0 1
value=750
}
C 46100 45200 1 270 0 resistor-1.sym
{
T 46500 44900 5 10 0 0 270 0 1
device=RESISTOR
T 46400 45000 5 10 1 1 270 0 1
refdes=R6
T 46100 45200 5 8 1 1 0 0 1
value=2300
}
C 47400 46200 1 270 0 resistor-1.sym
{
T 47800 45900 5 10 0 0 270 0 1
device=RESISTOR
T 47700 46000 5 10 1 1 270 0 1
refdes=R7
T 47400 46200 5 8 1 1 0 0 1
value=10
}
C 41300 46000 1 0 0 vdc-1.sym
{
T 42000 46650 5 10 1 1 0 0 1
refdes=V1
T 42000 46850 5 10 0 0 0 0 1
device=VOLTAGE_SOURCE
T 42000 47050 5 10 0 0 0 0 1
footprint=none
T 42000 46450 5 10 1 1 0 0 1
value=DC 10V
}
C 41500 43700 1 0 0 gnd-1.sym
C 43800 43700 1 0 0 gnd-1.sym
C 46100 43700 1 0 0 gnd-1.sym
C 47400 43700 1 0 0 gnd-1.sym
N 41600 47200 41600 48600 4
N 41600 48600 43900 48600 4
N 43900 47700 43900 46900 4
N 43900 46900 44700 46900 4
N 44700 46900 44700 47200 4
N 43900 46000 43900 45200 4
N 43900 45200 44700 45200 4
N 44700 45200 44700 45500 4
N 45600 45500 46200 45500 4
N 46200 45500 46200 45200 4
N 45600 47200 47500 47200 4
N 47500 47200 47500 46200 4
N 47500 45300 47500 44000 4
N 46200 44300 46200 44000 4
N 43900 44300 43900 44000 4
N 41600 44000 41600 46000 4
