Source: klibc Version: 2.0.4-2 Severity: normal Tags: patch upstream Forwarded: http://www.zytor.com/pipermail/klibc/2015-April/003725.html
Hi, For mips and mipsel, the plan is to enable the FPXX ABI when GCC 5 is made the default compiler. See these for more information: https://bugs.debian.org/789612 https://dmz-portal.mips.com/wiki/MIPS_O32_ABI_-_FR0_and_FR1_Interlinking Packages which only use C will compile file and most MIPS assembly will work except for code which uses the odd numbered FPU registers which are now unavailable for direct access. klibc does this when it saves all the FPU registers in its setjmp implementation on MIPS. I've attached a patch which uses the sdc1 / ldc1 instructions when the FPXX ABI is in use which do not need refer to the odd numbered FPU registers. Thanks, James
From 707d943ce379a2a9eafcc970da8fd5318e3763e4 Mon Sep 17 00:00:00 2001 From: James Cowgill <[email protected]> Date: Wed, 22 Apr 2015 16:02:24 +0100 Subject: [PATCH] mips: setjmp: allow working with fpxx/fp64 abi This patch is needed to allow klibc to be compiled on a mips compiler configured to use the FPXX ABI (which is in GCC 5). In that ABI the odd numbered FPU registers cannot be used directly, but they can be accessed using the double word sdc1 and ldc1 instructions. See this page for more info: https://dmz-portal.mips.com/wiki/MIPS_O32_ABI_-_FR0_and_FR1_Interlinking --- usr/klibc/arch/mips/setjmp.S | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/usr/klibc/arch/mips/setjmp.S b/usr/klibc/arch/mips/setjmp.S index 68eed19..c6963c4 100644 --- a/usr/klibc/arch/mips/setjmp.S +++ b/usr/klibc/arch/mips/setjmp.S @@ -29,6 +29,14 @@ LEAF(setjmp) sw s8, 40(a0) sw ra, 44(a0) cfc1 t0,$31 +#if __mips_fpr == 0 || __mips_fpr == 64 + sdc1 $f20,48(a0) + sdc1 $f22,56(a0) + sdc1 $f24,64(a0) + sdc1 $f26,72(a0) + sdc1 $f28,80(a0) + sdc1 $f30,88(a0) +#else swc1 $f20,48(a0) swc1 $f21,52(a0) swc1 $f22,56(a0) @@ -41,6 +49,7 @@ LEAF(setjmp) swc1 $f29,84(a0) swc1 $f30,88(a0) swc1 $f31,92(a0) +#endif sw t0,96(a0) move v0,zero jr ra @@ -61,6 +70,14 @@ LEAF(longjmp) lw s8, 40(a0) lw ra, 44(a0) lw t0, 96(a0) +#if __mips_fpr == 0 || __mips_fpr == 64 + ldc1 $f20,48(a0) + ldc1 $f22,56(a0) + ldc1 $f24,64(a0) + ldc1 $f26,72(a0) + ldc1 $f28,80(a0) + ldc1 $f30,88(a0) +#else lwc1 $f20,48(a0) lwc1 $f21,52(a0) lwc1 $f22,56(a0) @@ -73,6 +90,7 @@ LEAF(longjmp) lwc1 $f29,84(a0) lwc1 $f30,88(a0) lwc1 $f31,92(a0) +#endif ctc1 t0,$31 move v0,a1 jr ra -- 2.1.4
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