Hi, > I had a quick look at the tools. They convert a floorplan description > into a bitstream and back. However for a complete workflow the > following bits are missing: > > * VHDL/verilog compiler to netlist > * place and route tool to turn the netlist into a floorplan > > Is this correct?
Wolfgang, can you comment on this? You can read the full discussion at http://bugs.debian.org/cgi-bin/bugreport.cgi?bug=686949 best regards, Timo Lindfors -- To UNSUBSCRIBE, email to [email protected] with a subject of "unsubscribe". Trouble? Contact [email protected]
