Andreas Schwab responds to my problem report posted at
https://lists.debian.org/debian-68k/2021/07/msg00000.html
>> ...
>> > The cause MIGHT be the incorrect value in <float.h> of LDBL_MIN_EXP:
>> > the M68K system has -16382, whereas test output from every other
>> > system in our farm that supports an 80-bit IEEE 754 format has -16381.
>>
>> This is correct. In the m68881 extended float format, denormals have an
>> exponent bias of 0x3fff, whereas in the i387 extended float format, the
>> bias is 0x3fffe. That means that a normalized number in m68881 ext
>> format can have a biased exponent of zero.
>> ...
I must disagree.
>From the cited M68000 Family Programmer's Reference Manual, on page
1-23, in Table 1-6. Extended-Precision Real Format Summary, the biased
exponent is defined as 15 bits wide, with a bias of +16383 (0x3fff).
In IA-32 Intel Architecture Software Developerâs Manual Volume 1:
Basic Architecture, 2001, page 4-6, below Table 4-3, Floating-Point
Number and NaN Encodings, it says:
>> ...
>> The biasing constant is 127 for the single-precision format, 1023 for
>> the double-precision format, and 16,383 for the double
>> extended-precision format.
>> ...
The Intel IA-64 Application Developer's Architecture Guide, May 1999,
(Order Number: 245188-001) on page 5-1, in Table 5-1 has
>> ...
>> Total memory format width (bits) 32 64 80 128
>> Exponent bias +127 +1023 +16383 +16383
>> ...
IEEE Std 754-1985, IEEE Standard for Floating-Point Arithmetic on page
3, says that the exponent bias for the single and double extended
formats is unspecified. The later 2008 and 2019 IEEE Standards do not
mention the 80-bit format.
The IEEE 754 designers wrote a series of papers in the IEEE journal
Computer in 1980, one of which is
Jerome T. Coonen
An Implementation Guide to a Proposed Standard for Floating-Point
Arithmetic
Computer 13(1) 68--79 (January 1980)
https://doi.org/10.1109/MC.1980.1653344
Its Table 2 on page 70 shows a minimum exponent of the 80-bit format
as less than or equal to -16383 (at the time, CPU designs for IEEE 754
were in progress at Intel and Motorola, and possibly also National
Semiconductor, but those companies had not yet released details, or
chips). The earliest hardware implementing the IEEE 754 draft was the
Intel 8087 floating-point co-processor, which hit the market in the
summer of 1980. It is described in detail in the book
John F. Palmer and Stephen P. Morse
The 8087 Primer
Wiley (1984)
ISBN 0-471-87569-4
The Motorola 68881 floating-point co-processor reached the market in
1984. It is described in
MC68881 Floating-Point Coprocessor User's Manual, second edition
(1985)
See also
https://en.wikipedia.org/wiki/IA-64
https://en.wikipedia.org/wiki/Intel_8087
https://en.wikipedia.org/wiki/Motorola_68881
https://en.wikipedia.org/wiki/NS32000
More information about floating-point designs can be found in this
extensive bibliography of about 6900 literature references:
http://www.math.utah.edu/pub/tex/bib/fparith.bib
http://www.math.utah.edu/pub/tex/bib/fparith.bib
Thus, three independent hardware designs --- M68K, IA-32, and IA-64
--- agree that the bias in the 80-bit format is 16363 (0x3fff). That
in turn means that their in-CPU-register formats for the 80-bit size
are identical, except for the question of what bit patterns are used
for NaNs, which are not relevant for my report.
The test output in my report shows that all three architectures have
the same bit patterns for numbers on either side of the transition
from normals to subnormals. The M68K subnormals in the output should
have values of 2**k, but are in fact printed as half that. The test
loop halves the x value on each iteration (an EXACT operation in
binary floating-point), so the tabulated numbers must fall by exactly
half. They do for x86 and IA-64, but not for M68K once subnormals are
reached.
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