On 12/18/2016 02:14 PM, John Paul Adrian Glaubitz wrote: > On 12/18/2016 02:02 PM, Andreas Schwab wrote: >>> I knew m68k has CAS/CAS2, but my suspicion was that lock-free atomics >>> require LDREX/STREX-alike instructions since older ARM implementations >>> have SWP/SWPB as well. So it shouldn't be too different from the CAS >>> instructions on m68k, should it? >> >> SWP is UP-only, and armv8 doesn't implement it. > > I think the main problem with SWP/SWPB is that they don't allow to implement > real lock-free atomics, isn't it? [1]
After a quick discussion with Michael Karcher, I actually understand the problem now. What ARM prior v6 offers is just a swap instruction, but unlike m68k an actual compare-and-swap instruction. SWP/SWPB is the equivalent to XCHG on i386 which was superceded by CMPXCHG on the 486 and newer x86 variants. With just SWP/XCHG, it's actually more complicated to do things like counting a global variable in multiple threads. With compare-and-swap, it's possible to achieve that lock-free while with just SWP/XCHG, it's always necessary to use additional mutexes. Adrian -- .''`. John Paul Adrian Glaubitz : :' : Debian Developer - glaub...@debian.org `. `' Freie Universitaet Berlin - glaub...@physik.fu-berlin.de `- GPG: 62FF 8A75 84E0 2956 9546 0006 7426 3B37 F5B5 F913
